JPS6043844A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To open a through hole in a self-matching way and to improve the integration degree of an element by a method wherein a second CVD insulating film is formed in a film thickness thicker than a total of the film thickness of a first wiring conductive film and that of a first CVD insulative film, and after that, the second CVD insulating film is flatened and is performed a reactive ion etching under a certain specified condition. CONSTITUTION:A first wiring conductive film 13 is adhered on a silicon oxide film 12 adhered on a silicon substrate 11, whereon an element has been formed, and after that, a silicon oxide film 14, for example, is formed as a first insulating film. A double-layer wiring pattern of the first insulating film 14 and the first wiring conductive film 13 is formed by a reactive ion etching method, and a nitriding film 15, for example, is again formed as a second insulating film. Then, the silicon nitriding film 15 is flatened by a reactive ion etching method. For example, the silicon oxide film 14 in the opening part is etched by a reactive ion etching method, wherein mixed gas of CF4 and H2 is used, until the surface of the aluminum wiring pattern 13 in the lower layer below the silicon oxide film 14 is made to expose in a condition that the etching speed of the silicon oxide film 14 is faster than that of the silicon nitriding film 15.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor device such as a semiconductor element or a semiconductor circuit), and in particular to the formation of a multilayer wiring structure in which the wiring structure has two or more layers. Regarding the method.

[Prior art and its problems]

Conventionally, according to a processing method of creating an opening (through hole) for interconnection between wires in an insulating film between wiring layers, as shown in FIG. When forming the opening, the opening is displaced from the aluminum wiring 3 due to misalignment of the mask pattern, so that a narrow and deep groove is formed in the insulating film 4 at the edge of the opening due to overetching when forming the opening. Because of this groove, when the 21st aluminum wiring layer 5 is formed, the shape of the hole becomes thinner on one side wall of the opening as shown in FIG. This results in a yield of 9 and a decrease in reliability.

In order to prevent this wiring breakage, it is necessary to take into account the pattern misalignment when forming a mask pattern corresponding to the opening, and make the wiring 1 thicker than the opening.
There is. However, in this case, the wiring becomes tight and the degree of integration of the elements decreases.

[Purpose of the invention]

An object of the present invention (d) is to provide a method for manufacturing a semiconductor device that can improve the S density of an element by forming through holes in a self-aligned manner.

[Summary of the invention]

The present invention relates to a method for manufacturing a semiconductor device 1H having a multilayer wiring structure, after a first wiring conductor film is vapor-deposited.

The first CVD insulating film! . The second insulating film is formed to a thickness of 1μ or more of the total thickness of CVD film Fj3Y, and then the second insulating film is planarized using an insulation layer planarization method using reactive ion etching. The first insulation film is subjected to reactive ion etching under conditions where the etching rate of the second insulation film is almost equal, and the first insulation film is exposed to the surface and then transferred to the second insulation film. This is a method in which the first IR insulation film is selectively etched to form holes under conditions where the etching rate of the film is high.

〔Effect of the invention〕

According to the present invention, it is possible to form a connection window having the same size as the width of the first wiring conductor film, and it is possible to improve the degree of wiring integration.

[・Examples of the invention]

Specific embodiments of the present invention will be described below with reference to the drawings.

2(a) to 2(e) are cross-sectional views showing the manufacturing process, and FIGS. 2(f) to 2(li) are plan views. First, Figure 2 (a
) as shown in [1] a silicon substrate 11 on which elements are formed;
For example, a silicon oxide film 12 is coated as an insulating film thereon.
t fl, , make a necessary connection hole, include this hole, jiff fee f' J2 silicon film 12, and place the first wiring conductor lrJ', and use magodron sputtering method to make the thickness ~ 08μ+n c7) Aluminum film 13
After depositing the first insulating film, for example, the first insulating film is grown by a plasma vapor deposition method using SiH4 and N20 gas.
A silicon oxide film 14 is formed to a thickness of 0.8 μm at a temperature of 300°C. Next, a 5-etching mask is formed, and a wiring pattern of the first insulating film 13 and the first wiring conductor 1402 layer is formed by reactive ion etching (LL I B ) method. As the insulating film 2, a silicon nitride film 15 is grown to a thickness of 2 μm at a temperature of ~300° C. using, for example, SiH4 and Ni−+3 gas.
Form the thickness of.

Next, for example, the silicon nitride layer 15 is planarized by utilizing the planarization phenomenon when etching a silicon nitride film by a reactive ion etching method using CF4 and l-12, This etching is continued until the silicon oxide J4 on the upper surface of the aluminum wiring pattern 13 is exposed (FIG. 2(b)).

Next, an etching mask 16 is formed by etching the autoresist 1G as a mask on the silicon nitride l+;'r] 5, as shown in FIG. 2C. In this figure, the width of the opening of the mask pattern is slightly wider than the wiring width of pattern 3 (7 km). Next, as shown in FIG. 2(d), for example, CF
Using the autoresist 16 as a mask, the silicon oxide 14 in the opening is etched by a reactive ion etching method using a mixed gas of 4 and 112 until the surface of the aluminum pattern 13 underneath is exposed. Etching is performed under conditions where the etching speed is faster than the etching speed of the wetted silicone return 15. For example, the CF4 flow rate is 24 cr:, /=, the I2 flow rate is '1 sec/ton,
When the pressure is 1.33 Pa, high frequency, and power is 150 W, the etching rate of silicon oxide is ~400 A.
For /-4=, the etching rate of silicon nitride film is ~
Since the etching speed is as slow as 20 A/=, it is difficult to etch most of the silicon nitride llc% 15, and the aluminum wiring 1
The silicon oxide film on the aluminum wiring 13 can be etched, and the opening is formed in self-alignment with the width of the aluminum wiring 13, as shown in FIG. 3(d).

Next, after covering an aluminum film 17, which is the same as the first aluminum wiring, as a second wiring conductor, for example, the aluminum wiring 17f is patterned by photolithography, as shown in FIG. 2(e). , the first aluminum wiring 13 and the second
aluminum wiring 17 is connected.

In this example, as the first insulating film, a silicon oxide film,
Although a silicon nitride film was used as the second insulating film and an aluminum film was used as the first wiring conductor, this combination is not limited to the example; The present invention becomes effective by using an etching method faster than that of the insulating film string and the first wiring conductor.

The combination is etching method, etching gas,!
? It can be seen that Etching 6 can be selected arbitrarily depending on the situation. In addition to the mixed gas of CF4 and H2, the reactive gas for reactive ion etching includes C2F5 and C3F8.
．． It is possible to fully open the mixed gas of C,li'', U]3r, etc. and I■2, and in addition, instead of 112, C)iF3
may also be used. The etching method is not limited to dry etching, but may also be wet etching. Also.

In this embodiment, an aluminum film is used as the wiring conductor, but Mo, W, Pr, and silicide alloys thereof may also be used.

[Brief explanation of drawings]

FIG. 1 is a top view of a semiconductor device manufactured by a conventional manufacturing method, FIGS. 2(a) to (e) are process cross-sectional views showing an embodiment of the present invention, and (f) to (h) is the same plan view. 11...Silicon substrate, 12...Silicon oxide film, 13...Al) 1 core (aluminum film). 14...First insulating film (silicon oxide film). 15...Second insulating film (silicon nitride film). 16...Auto registration. 17...Second wiring conductor (aluminum film). Representative Patent Attorney Kensuke Norichika (and 1 other person) Figure 1 Figure 2

Claims (1)

[Scope of Claims] After forming a first insulating film on a first wiring conductor, a step of patterning the first wiring, and thereafter. forming a second insulating film to fill the concave portions of the pattern and exposing the upper surface of the first insulating film; applying a resist to the entire surface; and selectively etching by photolithography; After forming the mask, etching of the insulation j of εi↓1 is performed using an etching method in which the etching speed of the first insulation film is moderately higher than that of the second insulation film, and a connection window is formed in the predetermined chain acid. A method for manufacturing a semiconductor device, comprising the step of forming a second wiring conductor after forming a mask and removing the mask.