JPS58169938A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent formation of fine grooves in window sections and thereby to prevent disconnection at through holes by a methd wherein a film with an etching speed higher than an interlayer insulating film is sandwiched between a first wiring layer and said interlayer insulating film. CONSTITUTION:An Al layer 3 and Si3N4 layer 4 are laid down on an SiO2 film 2 covering an Si substrate 1, and a resist mask 5 is provided thereon. Responsive ion etching is performed by using CF4+CCl4, whereafter the resist mask 5 is reduced into ashes by means of plasma and then removed. Next, by reduced pressure CVD in SiH4+O2, an SiO2 film 6 is added, and a resist mask 7 is provided thereon. Responsive ion etching is performed by using CF4+H2, which is continued, even if the resist mask 7 goes out of place, until the top surfaces of the SiO2 film 6 and the Al layer 3 become of the same level. Thereafter, the resist mask 7 is subjected to plasma for reduction into ashes. The Al layer 3 remains completely free of etching, and the Si3N4 layer 4 responds to etching at a speed four times higher than the SiO2 film 6 under certain prescribed conditions. This prevents grooves from forming in the vicinity of the insulating SiO2 film 6. Accordingly, no disconnection is expected to occur at window sections during the process of installing an Al wiring 8, which enhances reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a wiring pattern without disconnection.

[Prior art and its problems]

Conventionally, according to the processing method of forming an opening (through hole) for interconnection between wirings in an insulating film between wiring layers, as shown in FIG. When forming an opening, the opening deviates from the aluminum double pattern s3 due to mask pattern misalignment, so a narrow and deep groove is formed in the insulating film 6 at the edge of the opening due to over-etching when forming the opening. Because of this groove, when the second aluminum wiring layer 8 is formed, its shape is 181
As shown in FIG. 6, since the side wall on one side of the gate part is thin, the wiring is likely to be disconnected, leading to a decrease in the yield and reliability of device manufacturing.

In order to prevent this wiring breakage, it is necessary to take into consideration the misalignment of patterns when forming a mask pattern corresponding to the opening, and to make the size of the inside of the wiring larger than the opening. However, in this case, the wiring becomes large and the degree of integration of the element is reduced.

[Purpose of the invention]

The object of the present invention is to
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent wiring breakage in through holes and improve device reliability.

[Summary of the invention]

A feature of the present invention for achieving the above object is that a film having a higher etching rate than the insulating film between the wiring layers is deposited on the first layer wiring pattern in advance, and when the opening is etched, the film is also etched at the same time. The purpose is to remove the insulating film by etching and to prevent the formation of fine grooves in the insulating film at the openings.

〔Effect of the invention〕

According to the present invention, even if there is a misalignment of the mask pattern when etching the opening, fine grooves in the insulating film are not formed in the opening, resulting in a 2! ! Breakage of the first wiring can be prevented, and element reliability can be improved. Further, since there is no need to increase the wiring width of the first layer, the degree of integration is not reduced, and this is extremely effective for forming through holes in multilayer wiring formation of high-density integrated circuits.

[Embodiments of the invention]

FIG. 2 (ml to le) is a process sectional view showing one embodiment of the present invention. First, as shown in FIG. 2 (al), silicon oxide 1112 is formed on a silicon substrate 1 by a thermal oxidation method, and on this silicon oxide film 2, aluminum 1112 with a thickness of 1 μm, for example, is formed by sputtering as a @11 conductive layer. For example, a silicon nitride film 4 with a thickness of about 0.3 μm is deposited on the aluminum film 3 by plasma vapor deposition using 8iH4 and Mlm as reaction gases, and then a mask is formed on the silicon nitride film 4. For example, after applying a resist 5, patterning is performed to form an etching mask.

Next, the silicon nitride film 4 is etched onto the resist 5 by reactive ion etching using a mixed gas of CF4 and Hl, for example.
For example, CCj is selectively etched as a mask.
After selectively etching the aluminum film 3 by a reactive ion etching method using a mixed gas of , and C4,
FIG. 2 1cl shows a state in which the resist 5 has been removed by O, plasma treatment, or the like. Then, as an insulating film, for example, 8i
H, and 0. A silicon oxide film 6 with a thickness of approximately 1 μm is deposited by a low pressure vapor phase epitaxy method using a gas or a plasma vapor phase epitaxy method using an H4, N, and O gas.
Figure 2 shows the state in which resist is applied as a mask and then patterned to form an etching mask.
Shown in cl. In FIG. 2 (cl), the width of the opening of the mask pattern is the same as that in the wiring of the aluminum film 3, but due to misalignment of the pattern, it becomes undulating as shown in lcl.

Next, using the resist 7 as a mask, the silicon oxide film 6 and the silicon nitride film 4 in the openings are etched by a reactive ion etching method using a mixed gas of CF, H2, etc. until the surface of the aluminum film 3 is exposed and etched. After etching was performed until the surface of the saponified silicon film 6 was approximately at the same height as the surface of the aluminum film 3, the resist was removed by 08 plasma treatment, etc., as shown in FIG.
Shown in d).

In the reactive ion etching method using a mixed gas of CF and Hl, the aluminum film 3 is not etched at all. CF4 flow rate 24cc/min, H, flow rate 3cc/
man, RF power 50W, pressure 0.
Under the condition of 0 I Torr, the etching rate of the silicon nitride film 4 is approximately 4 times the etching rate of the saponified silicon film 6.
Since this is twice as fast, the silicon nitride film 4 on the aluminum film 3 is etched quickly. As shown in FIG. 2 (di), the etched opening does not have a thin groove as shown in FIG. 1. In addition, as shown in FIG. The state in which the aluminum film 8 is formed by a sputtering method or the like is shown.As can be seen from FIG.
It was found that the coverage at the opening provided for connection with the aluminum film 3, which is the conductor layer, was very good, there was no disconnection at the opening, and the four-axis property of the element was improved.

[Other embodiments of the invention]

In the above embodiment, an aluminum film was used as the conductor layer, but it may also be a film of Mo, W, Pt, or a silicide alloy thereof. Although a silicon oxide film was used as an insulating film between wiring layers, a silicate glass film containing phosphorus, arsenic, boron, etc. may also be used. Furthermore, when a silicon nitride film is used as an interlayer insulating film, For example, in a reactive ion etching method using a mixed gas of CF4 and H2, the etching rate of the silicon oxide film or silicate glass film is higher than that of the silicon nitride film. Conditions faster than etching speed, e.g. CF
, z 24cc/min, H, w 12cc/
min, RF power 150W, pressure Q, OI
The opening may be etched under Torr conditions. That is, the combination of the interlayer insulating film and the film previously deposited on the wiring pattern depends on the etching method, etching gas,
It turns out that it can be selected arbitrarily depending on the etching conditions, and the reactive gas for reactive ion etching is CF,
In addition to the mixed gas of CtF@*C5Fa
*A mixed gas of CF, Br, etc. and Hl can be used, and CHF may be used instead of Hl.

Note that in FIG. 2 1dl of the example, etching was performed until the surface of the silicon oxide film 6 after etching at the opening became coplanar with the surface of the aluminum film 3;
Even if you stop etching when the surface of the
The coverage of aluminum M8, which is the conductor layer, is good;
No wire breakage occurs. When etching the opening, there is a margin for controlling the etching time, so the present invention is effective in improving the 4M flexibility of the device.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a conventional example, and FIG. 2 is a process cross-sectional view showing an embodiment of the present invention. ... Silicon oxide film, 3.8 ... Aluminum film, 4 ... Silicon nitride film, 5.7 ... Resist film Figure 2 trL> 21 (e)

Claims (3)

[Claims] (1) Forming a conductor layer on a semiconductor substrate, forming a first film on the conductor layer, and selectively forming a mask on the first film, and then forming a first film on the first film. a step of selectively etching the conductor layer, a step of depositing a second film which is an insulating film after removing the PIIt mask, and a step of selectively forming a mask on the second film, and a step of depositing a second film, which is an insulating film, after removing the PIIt mask. A method for manufacturing a semiconductor device, comprising the step of: exposing the surface of the conductor layer by etching using an etching method in which the etching rate of the second film is faster than the etching rate of the second film. (2) A patented manufacturing method characterized in that a silicon nitride film is used as the first film, and a silicon oxide film or a silicate glass film containing impurities is used as the second film. (3) The semiconductor device according to claim 1, wherein the etching rate of the first film is lower than the etching rate of the @2 film, and a reactive ion etching method is used as the etching method. manufacturing method.