JPH03297134A - Formation method of pattern - Google Patents

Abstract

PURPOSE:To form a pattern of an insulating film having a hole whose shape is optimum for burying a metal interconnection by a method wherein the insulating film is constituted of a film which includes a silicon oxide film and a silicon nitride film. CONSTITUTION:A silicon oxide film 8 is formed on a substrate or an interconnection 1; after that, a silicon nitride film 9 is formed; in addition, a glass film 10 which contains phosphorus or boron is formed; an insulating film 2' is formed. Then, the film 10 is etched to the halfway part of its film thickness. After that, the remaining film 10 is wet-etched by buffered hydrofluoric acid. Since the film 9 is not dissolved by the hydrofluoric acid at this time, the dissolution of the film 10 progresses only in the transverse direction and is stopped at the film 9 in the depth direction. Lastly, the remaining films 9, 8 are dry-etched; a step-shaped taper connecting hole 11 is formed. Consequently, the opening width of the connecting hole can be prescribed only by the time of a wet etching operation, the substrate is not etched excessively and the connecting shape can be formed in an optimum shape.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pattern forming method used in manufacturing various solid-state devices including semiconductor integrated circuits. A taper (commonly known as a contact hole) is used to form a connection hole (commonly known as a contact hole) to connect multilayer wiring (commonly known as a via hole).
The term "taper" here refers to all hole shapes in which the bottom diameter of the hole is smaller than the top diameter of the hole, and a step-like shape is also defined as a taper.

[Conventional technology]

In the manufacturing process of a semiconductor integrated circuit, for example, elements are created on a semiconductor substrate, covered with an insulating film (silicon oxide film), and wiring for connecting the elements is formed. In recent years, the wiring in this case is often multilayered, and two-layer wiring and three-layer wiring are formed. In order to connect between an element and a wiring, or between a wiring (first layer) and a wiring (second layer), it is necessary to form a connection hole in the insulating film and fill the hole with the wiring. However, the insulating film is dry-etched (etching using gas plasma using the resist pattern as a mask: usually using a fluorocarbon-based gas) after normal gluing (resist pattern formation technology using a resist coating process, exposure process, and phenomenon process). If a vertical hole is simply made by drilling a connection hole using reactive ion etching (reactive ion etching method is used), it is difficult for metals such as aluminum used for wiring to enter the hole. Almost no metal enters the vertical hole.

FIG. 4 is an explanatory diagram of the process of forming wiring metal on a structure having an insulating film patterned on a substrate.

This will be explained in detail below. FIG. 4(a) shows a state in which a connection hole 3 is formed in an insulating film 2 on a substrate 1, and FIG. 4(b) shows a state in which a wiring metal 4 is further formed. The wiring metal 4 is not contained in the connection hole 3. To avoid this problem, techniques have been developed to taper the holes. Up until now, there have been roughly two types of methods considered for this taper technology, that is, taper processing technology. One method is to dry-etch the insulating film while gradually receding the resist pattern, and the other method is to dry-etch after forming a taper on the upper part of the insulating film by wet etching. In this case, the latter method is adopted in many processes because it is difficult to significantly set back the resist pattern and it is difficult to obtain a good taper.

This method is specifically illustrated in FIG. FIG. 5 is an explanatory view of a pattern forming method in which the upper part of the insulating film is tapered by wet etching and then dry etched as an example of the process steps of the taper processing technique.

First, as shown in FIG. 5(a), an insulating film 2 is formed on a substrate 1, and a resist pattern 5 is formed by a known lithography method. Next, the insulating film 2 is etched by wet etching using the resist pattern 5 as a mask (FIG. 5(b)). Since wet etching proceeds isotropically, the shape after etching becomes tapered. In this case, buffered hydrofluoric acid, diluted hydrofluoric acid, or the like is used as the etching solution.

Subsequently, as shown in FIG. 5(C), the remaining insulating film is dry-etched to obtain a tapered connection hole 6. For dry etching, CHF3/O! and CF. A reactive ion etching method using a reactive gas such as /H2 or C2F6 is used. In the above-mentioned reactive ion etching method, side etching does not occur and etching progresses anisotropically, so that the etched shape is a vertical hole tapered at the top. When the wiring metal 4 is formed in the tapered connection hole 6 formed in this way by a known sputtering method, the wiring metal 4 enters the tapered connection hole 6, but the taper angle is shallow and only a small amount of metal enters. No (Figure 5(d)). In this case, a large amount of wiring metal will migrate due to subsequent heat treatment, etc., resulting in a decrease in connection yield.

Therefore, recently a method has been proposed in which dry etching is performed a little before wet etching as shown in FIG. For example, "Method for manufacturing semiconductor devices" JP-A-01-194
This is as disclosed in Publication No. 328. That is, FIG. 6 is an explanatory diagram of a pattern forming method using another taper processing technique according to the prior art. In this method, the sixth
As shown in FIG. 5(a), intermediate holes are formed by first dry etching using the resist pattern 5 as a mask. Subsequently, a wet etching process (FIG. 6(b)) and a second dry etching process (FIG. 6(C)) are performed to obtain a tapered connection hole 6''.When the wiring metal 4 is embedded in this hole As shown in FIG. 6(d), FIG. 5(d)
), the wiring metal 4 can fit into the connection hole better. Therefore, a good tapered connection hole can be obtained by the method shown in FIG. 6, but as shown in FIG.
7” will be created.

This "su" will expand during the subsequent heat treatment process, etc., and will cause the film to peel off. Therefore, in order to ideally embed metal, it was necessary to further increase the taper angle.

[Problem to be solved by the invention]

In order to make a good connection between an element and metal or between metals through an insulating film, it is necessary to make a tapered connection hole in the insulating film. As a method for this purpose, a taper processing technique is known in which a resist with a pattern of holes to be opened is formed using known lamination lithography, and then wet etching and then dry etching are performed.However, with this method, a sufficient taper cannot be formed. For this purpose, a method of dry etching before wet etching has been proposed, but even with this method it is not possible to secure a sufficient taper, and with wet etching, the amount of etching varies, so a considerable amount of overetching is required, and diffusion There was a problem of excessive etching of the layer.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a pattern forming method using an insulating film taper processing technique that has an optimal hole shape for filling metal wiring and requires a minimum amount of overetching. Specifically, the insulating film, which normally consists only of a silicon oxide film containing glass containing phosphorus or boron, is changed to a laminated film of silicon oxide film/silicon nitride film/(silicon oxide film).

[Means to solve the problem]

FIG. 7 shows the progress of film deposition when a contact hole is formed by tapering an insulating film by a known method and a metal thin film is formed therein. When the film is deposited by sputtering, not only does the thickness of the metal thin film 4 on the large dust become thinner, but another important problem occurs.

In other words, the deposition rate is slow at the bottom of the hole due to the shadow effect, and the deposition rate in the direction of the arrow is almost the same as that on the flat area, resulting in the formation of "S7" as shown in Figure 7. Put it away.

On the other hand, if the connection hole has a stepped taper as shown in Figure 1,
This problem will go away. That is, FIG. 1 is a structural diagram in which a metal thin film is deposited on a step-like taper connection hole formed using the pattern forming method according to the present invention. This is because the upper part of the connection hole does not accumulate preferentially than the lower part and block the opening. The present invention provides a pattern forming method using this step-like taper forming technique.

The present invention will be explained in detail below. That is, the present invention provides a step in which an insulating film is formed on a substrate or a wiring, and pores are formed in the insulating film by microfabrication technology, the diameter of which is at least smaller than the diameter of the pore top. The present invention relates to a pattern forming method characterized in that the film is a film containing at least a silicon nitride film, and the pattern forming method is characterized in that the film is a film containing at least a silicon nitride film, and the pattern formation method is characterized in that the film is a film containing at least a silicon nitride film. a first step of forming an insulating film for the stopper insulating film; a second step of forming a glass film of a predetermined thickness on the stopper insulating film; and a resist pattern of a predetermined pattern width on the glass film. a fourth step of etching the glass film halfway by dry etching, etching the remaining glass film to expose the stopper insulating film, and laterally etching the glass film. A fifth step of wet etching to form a predetermined step-like taper by etching, and dry etching of the stopper insulating film or the stopper insulating film and the first insulating film to form a predetermined step-like taper connection hole. and a seventh step of forming a predetermined metal wiring after removing the resist pattern. The method relates to a pattern forming method characterized in that the insulating films sequentially formed on the substrate or the wiring are a silicon oxide film/silicon nitride film/glass film of a predetermined thickness; The present invention relates to a pattern forming method characterized in that the insulating films sequentially formed thereon are silicon nitride films/glass films having a predetermined thickness, or the amount of dry etching in the fourth step and the amount of dry etching in the fourth step; 5
The present invention relates to a claim method characterized in that the taper angle θ is arbitrarily defined according to the amount of wet etching in the process, and the opening width of the connection hole is defined only by the wet etching time. This relates to a pattern forming method characterized in that the taper angle θ is 80° or more, or it relates to a pattern forming method characterized in that the amount of overetching is 10% or less in the sixth step. It is.

In the present invention, the term "taper" refers to all hole shapes in which the hole bottom diameter is smaller than the hole top diameter, and is further defined as including the shape of a stepped connecting hole.

〔Example〕

Here, the steps of the present invention will be explained. FIG. 2 is an explanatory diagram of a pattern forming method using the stepped taper processing technique according to the present invention. First, as shown in FIG. 2(a), a silicon oxide film 8 as a first insulating film is formed on the substrate or wiring l, and then a silicon nitride film 9 is formed as a stopper insulating film, and then phosphorus (P) is formed. A multilayer insulating film 2' is formed by forming a glass film (commonly known as PSG or BPSG) 10 containing carbon or boron (B). Next, the glass film IO is etched halfway through its film thickness using a dry etching method (
Figure 2(b)). The amount of etching may vary somewhat as long as it does not reach the silicon nitride film 9. After this, the remaining glass film 10 is wet-etched. Buffered hydrofluoric acid or diluted hydrofluoric acid is used for wet etching. In the case of the present invention, since the silicon nitride film 9 as a stopper insulating film does not dissolve in the hydrofluoric acid, the dissolution of the glass film 10 in the hydrofluoric acid proceeds only in the lateral direction and stops at the silicon nitride film 9 in the depth direction. . As a result, a pattern as shown in FIG. 2(C) is formed. The last remaining silicon nitride film 9 as a stopper insulating film and the silicon oxide film 8 as a first insulating film are dry etched to obtain a step-like tapered connection hole l1 as shown in FIG. 2(d). Therefore, the opening width of the connection hole can be determined only by the wet etching time, and the thickness of the silicon nitride film/silicon oxide film remains constant even if the wet etching time changes, so there is no need to over-etch the substrate due to over-etching. That will no longer be the case.

The present invention will be explained in more detail with further comparison.

FIG. 3 is a comparison diagram of the tapered shape formed by the conventional techniques (a) and (b) and the taper processing technique according to the present invention (C) after a metal thin film is formed. FIG. 3 shows fa) wet etching process and dry etching process, (b) dry etching process and wet etching process when BPSGo, a laminated film of 35 μm/silicon oxide film 0.15 μm is used as the insulating film 2. Dry etching process, (C) Dry etching process, wet etching process, and dry etching process (invention) when inserting a silicon nitride film with a thickness of 0.02 F=0.6
A stage in which a connection hole is opened using a μm-wide resist pattern as a mask (left figure), and an aluminum 0.5 mm width is used as the wiring metal 4.
This is the stage (right figure) where a thickness of 5 μm has been formed. Figure 3(a)
Then, buffered hydrofluoric acid (HF:NH4F=l:10
) for 60 seconds to wet-etch the BPSG, remaining BPSG approximately 0.1 μm/silicon oxide film 0.1
5 μm was subjected to reactive ion etching using CHF3102=10:1 mixed gas plasma (pressure: 50 mTorr). Considering the variation in the amount of wet etching, it is necessary to perform dry etching with an overetching amount of 30%. In FIG. 3(b), BPSG of 100 OA (angstroms) is etched by the above-described reactive ion etching, and a silicon oxide film of 0.15 μm is etched by immersion in buffered hydrofluoric acid for 60 seconds (wet etching). Again, 30% overetching is required. The taper angle θ of both is shown in Fig. 3(a).
θ1-40 degrees in , θ2 = 5 in Fig. 3(b)
At 0 degrees, θ1 < θ2, and it can be seen that the taper angle is larger in the case of Fig. 3 (bl). When wiring metal is formed in these connection holes, a large "s" appears in Fig. 3 (a). In Figure 3(b), this "su" becomes smaller but does not disappear.

On the other hand, in FIG. 3(C), which is the present invention, first, BPSGo
.

After dry etching to a thickness of 25 μm, it is similarly immersed in buffered hydrofluoric acid for 60 seconds. After this, silicon nitride film 0°02μm
/A pattern is obtained by reactive ion etching of a silicon oxide film of 0.15 μm. Over-etching amount is 10%
The following is fine. By creating a step-like taper, the wiring metal can be formed without creating a "hole".

The taper angle θ3 of the present invention is about 80 degrees, but if you want it to be 90 degrees, the amount of dry etching of BPSG should be 0.3 μm.
It's fine as long as it's moderate. That is, in the present invention, it is also possible to arbitrarily change the taper angle θ depending on the first dry etching amount and wet etching amount. Further, in the above description, a silicon nitride film having a thickness of 0.02F was used, but the thickness is not limited to this as long as it is sufficient to act as a stopper for wet etching. The silicon nitride film can be formed using known CVD methods, plasma CVD methods, and E
CR method, sputtering method, etc. may be used. On the other hand, although the connection hole between the substrate and the wiring is mainly used as an example, it is obvious that the present invention can also be applied to the connection hole between the wiring and the wiring. Further, although the above example mainly uses a three-layer film of glass/silicon nitride film/silicon oxide film, the same effect can be achieved with a two-layer film of glass or silicon oxide film/silicon nitride film. However, the dry etching rate ratio between the substrate (Si) and the silicon nitride film is
i)/Since the silicon oxide film cannot be made very large, the use of the above three-layer film can improve performance when forming connection holes between the substrate and wiring.

The pattern forming method according to the present invention will be described below using specific numerical examples and process examples.

Process step example I: S is deposited on a Si substrate by normal pressure CVD method.
+H < 0.4 liters/min, (min), silicon oxide film 0.0.2 liters/min at 400° C. under mixed conditions of N240 liters/min.
A film with a thickness of 1 μm is formed, and S is deposited on this film by plasma CVD.
! H4: N2=1:10, ITorr, 30
Deposition was performed for 2 minutes at 0° C. and high frequency of 300 W to form a silicon nitride film with a thickness of 400 A. Furthermore, S
iH.

600cc/min, /PH3600cc/min,
/B2Hs 300 cc/min, a 0.4 μm thick BPSG film was formed by atmospheric pressure CVD to serve as an insulating film. After forming a hole pattern with a width of 0.5 μm by the usual glue-sogelafy process of resist coating, exposure, and development, CH
F3: 0□-5/1, 50mTorr, 50
A 0.3 μm thick BPSG film was subjected to reactive ion etching under the condition of 0W, immersed in buffered hydrofluoric acid of HF:N84F=1:10 for 65 seconds, and finally a silicon nitride film of 400A (angstrom) was etched with CHF3.02=5=1. The silicon oxide film was subjected to reactive ion etching with CHF3:02=10:1. ashing
The resist was removed to form an opening with a width of 1 μm and a bottom width of 0.
A laminated wiring of titanium, titanium nitride, and copper-containing aluminum was formed in a step-like taper connection hole of 5 μm by sputtering, and a good connection pattern was obtained.

Enimaru Kodan■Uni ECR plasma CVD (microwave 400W) on a substrate with laminated aluminum wiring
Accordingly, a silicon oxide film was formed under the condition of SiH,:O,=1:2, a silicon nitride film was formed under the condition of SiH4:N,=1:1, and further 5iH1:O□=1=1.
Under the conditions of 0.2 μm and 10.0
The films were sequentially formed to have a thickness of 5 μm and a thickness of 10.5 μm. 0.8μm
After forming a resist pattern with a width of 0.3 μm, a silicon oxide film of 0.3 μm was reactive ion etched under the same conditions as process step example I, and immersed in buffered hydrofluoric acid for 70 seconds to form a silicon nitride film of 0.05 μm/silicon oxide film of 0. .2μm CHF
Reactive ion etching was performed at a ratio of 3:0□-5:1 to obtain a step-like tapered connection hole with an opening width of 1.4 μm and a bottom width of 0.8 μm. Copper-containing aluminum wiring was formed on this, and a good connection between the wirings could be achieved.

Note that the film thickness, formation conditions, etc. of the present invention are not limited to the above specific examples, and for example, a silicon nitride film or the like as a stopper insulating film can be used as a stopper for wet etching using an etching solution such as hydrofluoric acid when forming a contact hole. Any process that includes a process can be applied.

Note that in the present invention, the substrate is not limited to a semiconductor substrate made of Si, but may also be a substrate made of other semiconductor materials.
Of course, the substrate may also be made of ceramics, glass, amorphous, or other materials. Further, the wiring is, of course, a wiring made of an electrode material such as metal, doped polysilicon, silicide, etc. arranged on the above-mentioned substrate.

Furthermore, in the embodiments of the present invention, the process of forming connection holes in a planar shape has been mainly described, but the process is not limited to this. Of course, it can also be applied to the formation of contact holes and through holes.

〔Effect of the invention〕

In the connection hole forming process proposed in the past, (1) the metal film thickness of the large dust becomes thin because the taper connection hole shape is not sufficiently formed, and the subsequent migration makes it impossible to connect.
2) This will cause "stains" to form and then cause the film to peel off. (3)
) Considering the variation in the amount of wet etching, the amount of overetching increases, resulting in problems such as etching even the diffusion layer of the substrate. According to the present invention, since the shape of the connection hole is step-like, the wiring metal can easily enter the hole and can be formed without "snapping". Since a silicon nitride film, for example, is inserted between the oxide films as a stopper insulating film during wet etching using an etching solution such as hydrofluoric acid, the opening width can be determined using only the wet etching processing time without considering the amount of etching in the depth direction. It can be controlled.Furthermore,
Since the final film thickness to be dry etched remains constant regardless of the length of wet etching time, the amount of overetching can be minimized. Therefore, the present invention makes it possible to improve the yield of LSI.

[Brief explanation of the drawing]

Fig. 1 is a process diagram of wiring metal deposition in a stepped connection hole according to the present invention, Fig. 2 is an example of a process for forming a stepped taper connection hole according to the present invention, and Fig. 3 is a diagram showing the results of forming wiring metal in each connection hole. FIG. Fig. 4 shows a conventional example (b) in which a vertical contact hole (a) and wiring metal are formed therein, Fig. 5 shows an example of a process for forming a tapered contact hole using a wet etching process and a dry etching process, and Fig. 6 This is an example of a process for forming a tapered connection hole by a process method including a dry etching process, a wet etching process, and a dry etching process. FIG. 7 is a diagram showing a process of depositing wiring metal in a tapered contact hole according to the prior art. Number 1 in the figure is the substrate or wiring, 2.2' is the insulating film,
3 is a connection hole, 4 is a wiring metal, 5 is a resist pattern, 6
．． 6' is a tapered connection hole, 7 is a "," 8 is a first insulating film or silicon oxide film, 9 is a silicon nitride film (insulating film for a stopper), 10 is a glass film, and 11 is a stepped tapered connection hole. be.

Claims (7)

[Claims] (1) In the step of forming an insulating film on a substrate or wiring, and forming pores in the insulating film using microfabrication technology, the insulating film has at least a silicon oxide film and a pore diameter smaller than the top diameter of the pore. A pattern forming method characterized in that the film includes a silicon nitride film. (2) A first step of forming a stopper insulating film of a predetermined thickness directly on the substrate or wiring or via a first insulating film of a predetermined thickness; and a first step of forming a stopper insulating film of a predetermined thickness on the stopper insulating film. a second step of forming a thin glass film; a third step of forming a resist pattern with a predetermined pattern width on the glass film; and a fourth step of etching the glass film to the middle of its thickness by dry etching. a fifth wet etching step of etching the remaining glass film to expose the stopper insulating film and laterally etching the glass film to form a predetermined step-like taper; a sixth step of dry etching the film or the stopper insulating film and the first insulating film to form a predetermined stepped tapered connection hole; and a seventh step of forming a predetermined metal wiring after removing the resist pattern. A pattern forming method for connecting between a substrate and wiring or between wirings, including a process. (3) The pattern forming method according to claim 2, wherein the insulating films sequentially formed on the substrate or the wiring are a silicon oxide film/silicon nitride film/glass film having a predetermined thickness. (4) The pattern forming method according to claim 2, wherein the insulating films sequentially formed on the substrate or the wiring are silicon nitride films/glass films having a predetermined thickness. (5) The taper angle θ is arbitrarily defined by the amount of dry etching in the fourth step and the amount of wet etching in the fifth wet etching step, and the opening width of the connection hole is defined only by the wet etching time. The pattern forming method according to claim 2, characterized in that: (6) The pattern forming method according to claim 5, wherein the taper angle θ of the tapered connection hole is 80° or more. (7) In the sixth step, the amount of overetching is reduced to 1
3. The pattern forming method according to claim 2, wherein the amount is 0% or less.