JPS60227440A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the current capacitance of a wire without deteriorating it in quality or integrity, by interposing a conductive layer having a selectivity in etching between Al layers and patterning the wiring in separate two steps for forming an upper Al pattern so as to have a width smaller than that of a lower Al pattern. CONSTITUTION:Apertures 5 and 6 are formed in an insulation film 4 on diffusion layers 2 and 3 of an Si substrate 1. Thin films of Al 7, TiW 8 and Al 9 are subsequently deposited thereon. A negative resist mask 10 having a width smaller than that of the wire required for high current by about 1mum, so that the Al layer 9 is etched with phosphoric acid to form an Al pattern 9p. Positive resist masks 11a and 11b are provided to have the same widths as the wires for high current and ordinary current, respectively, and the TiW pattern 8 and the Al patterns 7p and 7n each having a predetermined width are formed by RIE. The resists 11a, 11b and 10 are plasma ashed so that a wire Lp having a two-layer structure and a wire Ln having an ordinary structure are formed. According to this method, an Al wire with a two-layer structure for high current can be readily formed without affecting dimensions of an Al wire with an ordinary width. Further, the difference in level as defined in the side faces of the thick wiring layer for high current is reduced, whereby the covering property of a protective film can be improved.

Description

Detailed Description of the Invention +8) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming two types of aluminum interconnects with different current capacities on a negative insulating film.

Note that the aluminum referred to here includes pure aluminum and aluminum alloys.

(b) Background of the Technology Recently, semiconductor integrated circuit devices are often used in which a circuit through which a large current flows is provided in the final output stage, such as a power amplifier or a control circuit for an external device.

In such a semiconductor integrated circuit device, if the current capacity of the output wiring is small, problems such as a decrease in output gain and disconnection occur.

tC) Prior Art and Problems Conventionally, one method of avoiding the above problem was to form the wiring width of the output section sufficiently wide.
When using this method, the degree of integration had to be sacrificed to some extent.

Another method is to increase the thickness of the wiring, but in this case, not only the above output wiring but also other wirings are formed thickly, so (1) Wet etching is used to pattern the wiring. If you try to pattern the wiring by dry etching, the pattern width will be significantly reduced by side etching, and the wiring width will need to be widened for the molecule, which will reduce the degree of integration. (2) If you try to pattern the wiring by dry etching Therefore, in terms of etching resistance, it is necessary to use a resist mask that is sufficiently thick to correspond to the thickness of the wiring, and it is difficult to provide a thick resist mask with a uniform thickness and the resolution during exposure is low. (3) Poor step coverage of the surface protection insulating film formed on the wiring at the edge of the wiring pattern. This caused problems such as lower reliability.

+d) Purpose of the Invention The present invention has been made in view of the problems of the conventional method described above, and is capable of increasing the current capacity of the output wiring without degrading the quality and degree of integration of the ordinary wiring formed on the same substrate. It is an object of the present invention to provide a method for forming aluminum interconnections that can be made evenly and without reducing the coverage of an insulating film for surface protection.

te1 Structure of the Invention The object of the present invention is to - form a first layer on an insulating film; When forming the second aluminum wiring, a first aluminum layer is formed on the insulating film, a conductive layer having etching selectivity with respect to the aluminum layer is formed on the first aluminum layer, and forming a second aluminum layer on the conductor layer; forming a resist pattern having a width narrower than a predetermined width of the wiring in a region on the second aluminum layer where the first aluminum wiring is to be formed; The second aluminum layer is patterned using the resist pattern as a mask, and then a predetermined first aluminum layer is formed on the main surface. A second resist pattern corresponding to the pattern width of the second wiring is formed, and the conductor layer and the first aluminum layer are patterned using the second resist pattern as a mask. A first aluminum wiring formed by laminating the second aluminum layer having a width narrower than that of the first aluminum layer on the first aluminum layer via the conductor layer; This is achieved by the method of manufacturing a semiconductor device according to the present invention, which includes the step of forming a second aluminum wiring formed by laminating conductor layers.

That is, in the present invention, the high current wiring is formed with a two-layer structure of aluminum, and the normal wiring disposed on the same insulating layer is formed with a single-layer structure of aluminum. an aluminum layer, a conductor layer having etching selectivity with respect to the aluminum layer;
After sequentially laminating the second aluminum layer, the second aluminum layer is patterned in the first etching step to form an upper layer aluminum pattern in the high current wiring, and in the second etching step, the second aluminum layer is patterned. The conductor layer and the first aluminum layer are patterned to form a lower aluminum pattern for large current wiring and a normal wiring pattern disposed on the same insulating film.

In this way, by interposing a conductive layer with etching selectivity between the aluminum layers and patterning thick high current wiring in two layers,
The problems of side etching and mask resistance shown in the conventional method are solved, and as shown in the summary above, the upper layer aluminum pattern in the high current wiring is formed narrower than the lower layer aluminum pattern. Since the side surface of the thick high-current wiring is formed in two steps and the step difference is alleviated, the coverage of the surface protective film is improved.

In this way, large current wiring and normal wiring can be easily installed together without degrading the quality and degree of integration of the wiring and without impairing the coverage of the surface protective film.

(f) Embodiment of the Invention The gist of the present invention will be specifically explained by way of an embodiment with reference to the process cross-sectional views shown in FIGS. 1 to 4 and the schematic top view shown in FIG. 5. The same symbols represent the same objects throughout the figures.

See Figure 1. For example, a functional region 2 consisting of a diffusion region on one surface of a semiconductor substrate.
and 3 are formed, and an insulating film 4 made of silicon dioxide, phosphosilicate glass, etc. is formed on the semiconductor substrate 1, and the insulating film 4
On the main surface of the substrate to be processed, on which the contact windows 5 and 6 that expose the functional regions 2 and 3 are formed, first, using a normal continuous sputtering method, a film is deposited to a thickness of about 1.5 to 2 [μm]. first aluminum layer 7. Thickness 0.1-0.2 [μm
] titanium-tungsten alloy (TiW) layer8. A second aluminum layer 9 having a thickness of about 1.5 to 2 [μm] is formed.

Here, the TiW layer 8 is a conductive layer having etching selectivity with respect to the aluminum layer 7.9.

Note that the conductor layer may be formed of silicon nitride, molybdenum, tungsten, molybdenum silicide, tungsten silicide, polycrystalline silicon, or the like.

Refer to FIG. 2. Next, a negative resist film, for example, is applied and formed on the substrate, and patterned by a normal photo process to form a region on the second aluminum layer 9 where a high current wiring is to be formed. , for example, from 0.5 to the width of the large current wiring.
Negative resist pattern 10 with a width as narrow as l (μm)
is formed, and wet etching is performed using, for example, phosphoric acid using the resist pattern 10 as a mask to form a second aluminum layer pattern 9p having a width narrower than the width of the large current wiring.
form.

Refer to Figure 3. Next, a positive resist film is applied and formed on the substrate, and patterned by a normal photo process to form a predetermined width on the main surface corresponding to large current wiring and normal wiring. The first positive resist pattern lla and the second
A positive resist pattern llb is formed, and the TiW layer 8 and the first aluminum layer 7 are patterned by dry etching means such as reactive ion etching using the positive resist patterns 11a and llb as a mask. Here, an aluminum pattern 7p as a lower layer of the large current wiring made of the first aluminum layer 7 and a normal wiring patterning 7n having a predetermined width are formed.

Here, the positive resist film may be formed after the negative resist pattern 10 is removed.

The gas used for the dry etching is czpsct for TtW and CCI* for aluminum.
+BC1s is suitable.

Refer to FIG. 4. Next, by removing the positive resist patterns lla, llb and the negative resist pattern 10 by a normal plasma ashing method etc., a first aluminum pattern 7p having a predetermined width is formed on the insulating film 4. niTi
A narrow second aluminum pattern 9 is formed through the W layer 8.
A two-layer high-current aluminum wiring t and p having a laminated structure and a normal aluminum wiring n having a single-layer structure consisting of an aluminum pattern 7n in which TiW 8 is disposed in the upper layer are formed.

FIG. 5 is a top view schematically showing the substrate surface when the wiring is completed.

(g) Effects of the Invention As shown in the above embodiments, according to the method of the present invention, a large current can be generated in a two-layer structure without affecting the dimensions of forming an aluminum wiring having a normal width on one insulating film. Since the aluminum wiring can be easily formed, the density of aluminum wiring having a normal width can be improved.

Further, the side surface portion of the thick aluminum wiring for high current is formed in two stages, and the difference in level between the two stages is reduced, so that the coverage of the surface protection insulating film formed on the wiring formation surface is improved.

Therefore, the present invention is effective for improving the degree of integration and reliability of semiconductor integrated circuit devices including large current circuits.

Furthermore, the present invention is extremely effective in increasing the current capacity of the power supply wiring of an ordinary semiconductor integrated circuit device.

[Brief explanation of drawings]

1 to 4 are process sectional views showing one embodiment of the present invention, and FIG. 5 is a schematic top view showing a state in which wiring formation is completed. In the figure, l is a semiconductor substrate, 2 and 3 are functional areas, and 4
1 is an insulating film, 5 and 6 are contact windows, 7 is a first aluminum layer, 7p and 7n are the same pattern, 8 is a titanium-tungsten alloy layer, 9 is a second aluminum layer, 9p is the same pattern, 10. lla. 11b is a resist pattern, Lp is a large current aluminum wiring, and Ln is a normal aluminum wiring. Agent Patent Attorney Hiroshi Matsuoka Department 11- Figure 1

Claims (1)

[Claims] A first insulating film. When forming the second aluminum wiring, a first aluminum layer is formed on the insulating film, a conductive layer having etching selectivity with respect to the aluminum layer is formed on the first aluminum layer, and forming a second aluminum layer on the conductor layer; forming a resist pattern having a width narrower than a predetermined width of the wiring in a region on the second aluminum layer where the first aluminum wiring is to be formed; Using the resist pattern as a mask, the second
The aluminum layer is patterned, and then a predetermined first pattern is formed on the main surface. A second resist pattern corresponding to the pattern width of the second wiring is formed, and the conductor layer and the first aluminum layer are patterned using the second resist pattern as a mask. A first aluminum wiring formed by laminating the second aluminum layer having a width narrower than that of the first aluminum layer on the first aluminum layer via the conductor layer; A method for manufacturing a semiconductor device, comprising the step of forming a second aluminum wiring formed by laminating conductor layers.