JPS62128150A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive improvement in reliability of the title semiconductor device by a method wherein, after a lower wiring has been formed by etching using a mask, the mask is removed, an isotropic etching is performed on the wiring until the desired film thickness is obtained, and the inclination of the end part of the wiring is made small, thereby preventing the short circuit generating from the etching residue on the upper layer wiring. CONSTITUTION:The lower layer wiring film 3 of polycrystalline silicon is grown on the insulating film 2 of a substrate 1 in the thickness which is a little thicker than normally required. Then, the mask 4 of the photoresist formed into the desired wiring pattern is formed on said wiring film 3, and a lower layer wiring 3a is formed. Subsequently, when a plasma isotropic etching is performed until the wiring 3a has a needed thickness under the condition wherein the mask 4 is removed and the wiring 3b is exposed, the end part of the wiring 3a is rounded off, and a wiring 3b having a gentle inclination is formed. Then, an interlayer insulating film 5 is formed by oxidizing the surface of the wiring 3b, and after an upper layer wiring film 6 of tungsten and the like has been coated thereon, a photoresist mask 7 is formed in the required pattern form. Then, an upper layer wiring 6a is formed by performing an anisotropic etching on the upper layer wiring film 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a multilayer wiring structure.

[Conventional technology]

2. Description of the Related Art As semiconductor devices have become highly integrated in recent years, semiconductor devices have been proposed in which a wiring structure formed on a substrate has a multilayer structure of two or more layers. For example, FIGS. 2(a) to 2(d) show a semiconductor device having a two-layer wiring structure in the order of its manufacturing process.

First, as shown in FIG. 2(a), a lower wiring film 13 made of polycrystalline silicon or the like is grown on the insulating film 12 on the surface of the semiconductor substrate 11.
Using a mask 14 on which a photoresist is formed in the shape of a wiring pattern, the lower wiring film 13 is isotropically etched to form a lower wiring 13a.

Next, after removing the mask 14 as shown in FIG. 2B, an interlayer insulating film 15 is formed on the lower wiring 13a as shown in FIG.
6 is applied. Then, a photoresist mask 17 formed in the desired wiring pattern shape is formed on this,
By anisotropically etching the upper layer wiring film 16 using this, the upper layer wiring 16a is formed as shown in FIG.
It has a two-layer wiring structure.

[Problem that the invention seeks to solve]

In the conventional manufacturing method described above, the lower layer wiring 1 formed first
The edge of the upper layer wiring 16a has a steep slope due to etching from the side of the mask 4.
During anisotropic etching, this end becomes a shadow in the etching direction, and as shown in FIG.
A may remain unetched at this edge. The remaining 16A of etching is the upper layer wiring 16a.
This causes short-circuiting of the semiconductor device and reduces the reliability of the semiconductor device.

For this reason, a method has been proposed in which after the upper layer wiring 16a is formed by etching, isotropic etching is added to remove the remaining etching 16A, but this method causes undercuts at the ends of the upper layer wiring 16a, and There is a possibility that the upper layer wiring 16a may be disconnected.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device having a highly reliable multilayer wiring structure by reliably preventing short circuits and disconnections particularly in upper layer wiring.

The method of manufacturing a semiconductor device of the present invention includes the steps of etching the lower layer wiring using a mask, and then isotropically etching the lower layer wiring to a desired thickness with the mask removed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(a) are cross-sectional views showing an embodiment of the present invention in the order of its steps.

First, as shown in FIG. 5A, a lower wiring film 3 made of polycrystalline silicon is deposited on an insulating film 2 on the surface of a semiconductor substrate 1 made of silicon or the like.
grow. In this case, the lower wiring film 3 is grown to be slightly thicker than originally required. Then, a photoresist mask 4 having a desired wiring pattern is formed on the lower wiring film 3, and using this, the lower wiring film 3 is isotropically etched to form the lower wiring 3a.

Next, the mask 4 is peeled off and removed to expose the lower layer wiring 3a as shown in FIG.
Plasma etching is performed using a mixed gas of a and 02, and the lower wiring 3a is isotropically etched to a desired thickness. As a result, the lower layer wiring 3a is reduced to its original thickness as shown in FIG. 3(c), and at the same time, the lower layer wiring 3b is formed with rounded shoulders and gentle slopes at the ends.

Thereafter, as shown in IiJ (d), the surface of the lower layer wiring 3b is oxidized to form a glabellar insulating film 5, and an upper layer wiring film 6 made of tungsten or the like is deposited thereon. Furthermore, a photoresist mask 7 is formed on this in a desired pattern shape. Then, by anisotropically etching the upper layer wiring film 6 using this mask 7, the upper layer wiring 6a is etched as shown in FIG.
form.

A reactive ion etching method or the like can be used for this anisotropic etching.

Hereinafter, although not shown, the mask 7 is removed and a surface protective film is formed thereon to complete the two-layer wiring structure.

In the two-layer wiring structure constructed in this way, after the lower layer wiring 3a is etched into a desired pattern shape,
Since the lower layer wiring 3b is formed by further isotropic etching with the mask 4 removed, the lower layer wiring 3 to be formed is
The slope of the end of b is relaxed and the corner of the shoulder is rounded. Therefore, when anisotropically etching the upper layer wiring film 6 in a later step, the lower layer wiring 3
There is no etching shadow at the edge of b.
Therefore, generation of etching residue on the upper wiring film 6 can be reliably prevented. Thereby, it is possible to prevent a short-circuit accident of the upper layer wiring 6a caused by etching residue on the upper layer wiring film. Further, since no etching residue is left on the upper layer wiring film 6, there is no need to add another isotropic etching after the pattern etching of the upper layer wiring film, and the occurrence of disconnection in the upper layer wiring 6a can be reliably prevented. can.

In the above embodiment, the lower layer wiring 3b is made of polycrystalline silicon, and the upper layer 1% 6a is made of tungsten, but aluminum or other high melting point metals can also be used as the material for these wirings. The same can be applied to this case as well.

Furthermore, it is also possible to use other anisotropic or isotropic etching methods other than those described above.

Furthermore, the same applies not only to the above-mentioned two-layer wiring structure but also to three or more layer wiring structures.

〔Effect of the invention〕

As explained above, the present invention includes the step of forming the lower layer wiring by etching using a mask, and then isotropically etching the lower layer wiring to the required thickness with the mask removed. By isotropic etching, it is possible to reduce the slope at the end of the lower layer wiring and prevent etching residue from forming on the upper layer wiring, and to prevent short circuits in the upper layer wiring caused by this, and to remove this etching residue. It is also possible to eliminate the need for additional etching, thereby preventing the occurrence of disconnections in the upper layer wiring caused by this, thereby improving the multilayer wiring structure and improving the reliability of the semiconductor device.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIGS. 2(a) to (d) are cross-sectional views showing the conventional method in the order of steps. ■, 11... Semiconductor substrate, 2.12... Insulating film, 3
゜13... Lower wiring film, 3a, 3b, 13a... Lower wiring, 4.14... Mask, 5, 15... Interlayer insulating film, 6.16... Upper wiring film, 6a, 16a...
Upper layer wiring, 7.17...mask. Agent Patent Attorney Akio Suzuki Figure 1

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device in which a lower layer wiring is formed, an interlayer insulating film is formed thereon, and an upper layer wiring is further formed on this to constitute a multilayer wiring structure, wherein the lower layer wiring A method for manufacturing a semiconductor device, comprising the step of isotropically etching the lower wiring to a desired thickness with the mask removed, after the step of etching into a desired pattern shape using a mask. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the lower layer wiring is formed in advance to be thicker than a desired value, and the film thickness of the lower layer wiring is reduced to the desired value by isotropic etching.