JPH0344929A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a capacity between interconnections and to improve rapidity of a semiconductor device by reactive ion etching an insulating film between base layers with second layer interconnection as a mask, and forming an isolating groove of an insulator between layers between second layer interconnections. CONSTITUTION:A first layer interconnection 2 is formed on a semiconductor substrate 1, an interlayer insulating film 3 of a silicon nitride film is deposited thereon, a coupling hole 3a is then formed. Then, second layer interconnections 4 made of Ti/Au are formed, with the interconnections 4 as masks the film 3 is etched by a reactive ion etching method to form an isolating groove 3b. Accordingly, since the film 3 except a lower part of the interconnections 4 is reduced in thickness by etching, interconnection capacity between the interconnections 2 and 4 can be reduced. Since the thickness of the film 3 between the interconnections 2 and 4 is not varied, the capacity between the layers does not increase. Thus, the capacity between the interconnections is reduced to enhance rapidity.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device mainly involving the formation of wiring.

(Prior Art) In recent years, semiconductor devices have progressed more and more, and LSIs with high integration and high speed operation have been developed.

In LSIs that require high-speed operation, in addition to the high speed of basic elements, delays due to wiring resistance and interlayer capacitance of multilayer wiring become problems, making it impossible to increase the thickness of wiring and interlayer films. ing.

Particularly, in GaAs ICs capable of high-speed operation, delays in the wiring process are a major problem.

FIGS. 3(a) to 3(d) are enlarged cross-sectional views of main parts showing the conventional manufacturing method for forming two-layer wiring of GaAs IC in the order of steps.

First, on the surface of the semiconductor substrate 1 on which elements are formed, for example,
T i / A u and each thickness is 50015000
A large first layer wiring 2 is formed (FIG. 3(a)). Next, for example, after depositing an interlayer insulating film 3 of 7,000 thick using a silicon nitride film, a connecting hole 3a is formed (FIG. 3(b)).
). Then 1, for example, Ti/Au, each with a thickness of 5
00/2nd tier placement of 8000 people! 4 (Fig. 3(C)). Finally, for example, use a silicon nitride film with a thickness of 400 mm.
A protective film 5 of size 0 is formed on the entire surface (Fig. 3(d)).
.

(Problem to be Solved by the Invention) However, in the above manufacturing method, an interlayer insulating film 3 such as a thick silicon nitride film is formed between each of the first layer and second layer wirings 2 and 4 formed in parallel. Therefore, the line capacitance becomes large, and as shown in the maximum frequency division frequency/current characteristic diagram in FIG. 2, there is a problem that the maximum frequency division frequency is low and the high speed characteristics are not sufficient.

The present invention solves the above problems and provides a method for manufacturing a semiconductor device that exhibits small line capacitance and excellent high-speed characteristics.

(Means for Solving the Problems) In order to solve the above problems, one aspect of the present invention is to etch the interlayer insulating film 3 other than the lower part of the second layer wiring 4 to form isolation trenches.

(Function) With the above structure, the interlayer insulating film formed between each of the first layer and second layer interconnects is thinned by etching, thus reducing the capacitance between the interconnects and increasing high speed.

(Example) An example of the present invention will be described with reference to enlarged cross-sectional schematic diagrams of main parts in the order of steps shown in FIGS. 1(a) to 1(e).

The difference between this embodiment and the conventional example shown in FIG. 3 is that after the first layer wiring 2 is formed (FIG. 1(c)), the second layer wiring 4 is
The interlayer insulating film 3 was etched by reactive ion etching (RIE) using the mask as a mask to form the isolation trench 3b.

Since the rest is the same as the conventional example, the same components are given the same reference numerals and the explanation will be omitted.

The semiconductor device manufactured in this way has a first layer wiring 2
Since the interlayer insulating film 3 other than the lower part of the interlayer insulating film 3 becomes a thin interlayer insulating film 3 by etching, the inter-wiring capacitance of each of the first and second layer wirings 2 and 4 can be reduced.

Since the thickness of the interlayer insulating film 3 between the first layer wiring 2 and the second layer wiring 4 does not change, the interlayer capacitance does not increase.

Figure 2 shows the manufacturing method of this embodiment and the conventional example.
This is a characteristic diagram comparing the current dependence of the maximum dividing frequency of a prototype A s frequency divider, showing that even with the protective film 5 formed on the entire surface, the characteristics are better than the conventional example without the protective film 5. I understand.

The present invention reduces inter-wiring capacitance and makes it possible to take advantage of high speed performance.

In this embodiment, the reactive ion etching (RIE) method was used to etch the interlayer insulating film 3 in order to prevent side etching from occurring in the interlayer insulating film 3 below the second layer wiring 4. It is. If isotropic etching is used, there is a risk that the interlayer insulating film 3 below the second layer wiring 4, which has become a fine wiring, will be removed, leading to a short circuit between the first layer wiring 2 and the second layer wiring 4. Furthermore, when side etching is performed under the second layer wiring 24, the interlayer capacitance is reduced at the same time as the interwiring capacitance. Usually, with the protective film 5 formed last,
Although the reduction in capacitance due to side etching is reduced, the protective film 5 is not sufficiently formed in the side etched portion.
Reliability decreases.

In this embodiment, the process for forming two-layer wiring has been described, but it is also effective for multi-layer wiring processes such as -layer wiring process and three-layer wiring process.

Also, in this example, Ti/Au was used for the wiring metal, but
This can also be other metals. Further, although a silicon nitride film is used for the one-layer insulating film 3 and the protective film 5, the present invention is not limited to this, and other insulating films such as a silicon oxide film or a polyimide film may be used. Furthermore, the interlayer insulating film 3 and the protective film 5 may be different types of films.

(Effects of the Invention) As explained above, according to the present invention, the underlying interlayer insulating film is etched using the second layer wiring as a mask, and isolation grooves of the interlayer insulating film are provided between the second layer wiring, thereby forming the wiring. This makes it possible to reduce the interlayer capacitance and increase the speed of the semiconductor device.

[Brief explanation of drawings]

1(a) to e) are enlarged cross-sectional views of main parts showing the manufacturing method of a semiconductor device according to the present invention in order of steps, and FIG. 2 is a G
Characteristic diagram of a A s frequency divider, Figure 3 (a) to d)
1A and 1B are enlarged cross-sectional views of main parts showing a conventional method for manufacturing a semiconductor device in order of steps. 1... Semiconductor substrate, 2... First layer wiring, 3...
- Interlayer insulating film, 3a... Connection hole, 3b... Isolation groove, 4... Second layer wiring, 5... Protective film. Fig. Fig. Protective film Fig. 6 (mA) Fig.

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device including a step of forming wiring on an insulating film, characterized by comprising a step of etching the insulating film using the wiring as a mask to form an isolation groove in the insulating film. A method for manufacturing a semiconductor device. (2) The method of manufacturing a semiconductor device according to claim (1), wherein the isolation trench of the insulating film is etched by reactive ion etching using the wiring as a mask.