JPS61271880A - Forming method for superconductive wire - Google Patents

Abstract

PURPOSE:To make the circuit compact, by arranging a superconductive wiring between two insulators, and etching a contact hole, whose size covers the superconductive wiring, in one insulator, under the conditions that the etching speed of one insulator is faster than the etching speed of the other insulator and the superconductive wiring. CONSTITUTION:On an Al2O3 film of a first insulator layer 5, an Nb film is deposited, and first and second superconductive wires 1 and 2 are formed. An SiO film or an SiO2 film of a second insulator layer 4 is deposited so as to cover the superconductive wires. a mask having an opening whose one part covers the wire 2, is formed. The insulator layer 4 is etched, and a contact hole 6 is formed. At this time, the etching condition is provided so that the etching speed of the insulator 4 is faster than the etching speed of the superconductive wires and the insulator. After the mask is removed, an Nb film is deposited to a thickness larger than the depth of the hole 6 on the upper part of the insulator 4 and the hole 6. Thus a third superconductive wire 3 is formed. The wire 3 and the wire 2 are electrically connected through the hole 6. Thus, the width of the superconductive wires and the interval between the wires can be made minimum, and the circuit can be made compact.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates more particularly to a method for forming a contact hole portion than a method for forming a superconducting line.

Superconducting integrated circuits containing Josephson junctions are capable of high-speed signal transmission due to the high-speed switching characteristics and low power consumption characteristics of Josephson junctions, and the lossless nature of superconducting lines, and are characterized by extremely low power consumption. Motsu. The superconducting integrated circuit has a multilayer structure consisting of Josephson junctions and multilayer superconducting lines. As a manufacturing method for realizing this circuit, Nb
Dry etching processes such as reactive ion etching using high melting point metals are often used.

According to this manufacturing method, it is necessary to make contact holes in the interlayer insulating layer in order to establish electrical connections between the multilayer interconnections of the superconducting integrated circuit. As a circuit becomes more highly integrated, the number of contact holes increases, and the area occupied by the contact portion in the circuit increases. Therefore, reducing the size of the contact portion is very effective in reducing the size of the entire circuit.

(Prior art and its problems) FIG. 3 (aXb) is a diagram for explaining a conventional example of a contact forming method. FIG. 3(a) is a plan view showing an example of a superconducting line, and FIG. 3(b) is a sectional view of a CC'' portion in FIG. 3(a). A pattern is formed on the top of the SiO insulating layer 35 of No. 1 by, for example, reactive ion etching.The line width at this time is t337, and the width between the lines is t3'38, or t.
It is 4'39. Next is the first one. Then, a second SiO insulator layer 34 is formed to cover the second superconducting line 31 and 32, and then a contact hole 36 is formed in the second SiO insulator layer 34 on the second superconducting line 32 by, for example, reaction. It is formed by a chemical ion etching method. contact hole 36
The width is W341. A third superconducting line 33 is patterned above the contact hole 36 by, for example, reactive ion etching. Said 1st. Second. For example, Nb can be chosen for the third superconducting line 31, 32, 33. The etching conditions for forming the contact hole 36 are set so that the etching rate of SiO is higher than the etching rate of Nb.

According to the forming method of this conventional example, it is necessary to make the size of the second superconducting line 32 below the contact hole 36 larger than the contact hole 36 by the alignment dimension n.

This is because if the contact hole 36 extends beyond the second superconducting line, even the first SiO insulator layer 35 will be etched, and if there is a superconducting wiring layer under the first SiO insulator layer 35, This is because an interlayer short circuit may occur in the contact hole portion. Now, the minimum dimension is t. The first superconducting line 31
The line width between the line and the second superconducting line 32 is t at the contact part.
4139, otherwise ζ'38, it is desirable to set t3=t4'=W=to in order to minimize the circuit size. However, in order to eliminate the above-mentioned interlayer short circuit at the contact portion, the line width ζ' is set to the minimum dimension by the alignment dimension n. It needed to be bigger. In an integrated circuit, a large number of such contact portions must be used, and it has been difficult to make the line spacing close to the minimum size.

For these reasons, conventional methods for forming superconducting lines have limitations in circuit miniaturization.

(Objective of the Invention) An object of the present invention is to solve the problems of the conventional method and to propose a method for forming a superconducting line that enables miniaturization of the circuit.

(Structure of the Invention) According to the present invention, at least first and second insulators;
In a method for forming a superconducting line, which includes a step of forming a pattern of superconducting wiring by etching, the superconducting wiring is arranged between the first and second insulators, and the etching rate of the second insulator is equal to the etching rate of the first insulator. etching a contact hole of an appropriate size so that at least a portion thereof covers the superconducting wire in the second insulator under conditions that are higher than the etching speed of the insulator and the superconducting wire. A method for forming a superconducting line characterized by the following is obtained.

(Function of the Invention) In a dry etching process such as reactive ion etching, a certain degree of overetching is required due to non-uniformity of etching on a wafer, variation in film thickness during film formation, and the like. Therefore, it is important that the etching speed ratio between the object to be etched and the underlying material is high.

In the present invention, if a contact hole is etched in the second insulator under conditions such that the etching rate of the second insulator is higher than that of the superconducting wiring and the first insulator, the contact hole can be etched. Even if the wire is larger than the superconducting wiring, the first insulator can stop the error. Therefore, interlayer short circuits at the contact portion can be prevented. In addition, the maximum depth of the contact hole can be determined accurately, and the thickness of the upper wiring can be determined with certainty.

Embodiments of the present invention will be described below with reference to the drawings.

(Example 1) FIGS. 1(a) and 1(b) are diagrams for explaining a first example of the present invention. FIG. 1(a) shows a plan view of the first embodiment, and FIG. 1(b) is a cross-sectional view of the crystal in FIG. 1(a). A superconducting layer, e.g. A Nb film is deposited by sputter deposition, and the first layer is etched by, for example, reactive ion etching. Second superconducting lines 1 and 2 are formed. A second insulating layer 4 covering the superconducting line, such as a SiO film formed by resistance heating vapor deposition, a silica film formed by spin coating and baking, or a SiO□ film formed by bias sputtering, etc. Deposit. On the second insulator layer 4, an etching mask having an opening such that at least a portion thereof overlaps the second superconducting line 2 is formed using photoresist, and the second insulator layer 4 is etched through the etching mask. The contact hole 6 is formed by etching the insulating layer using, for example, reactive ion etching. The etching conditions at this time are set so that the etching rate of the second insulator is higher than the etching rate of the superconducting line and the first insulator. Subsequently, after removing the etching mask, the second insulating layer 4 and the contact hole 6 are removed.
A superconducting layer, such as a Nb film, is deposited on top of the contact hole 6 by sputter deposition to a thickness equal to or greater than the depth of the contact hole 6, and a third superconducting line 3 is formed by, for example, reactive ion etching. The third superconducting line 3 and the second superconducting line 2 are electrically connected via the aforementioned contact hole 6.

According to the formation method of the present invention, even if over-etching is performed when etching the contact hole portion due to non-uniform etching or variation in film thickness when forming the contact hole 6, the etching will not occur in the first insulating layer. 5
It will be stopped at. Therefore, even if a superconducting layer exists under the first insulator layer 5, errors such as interlayer short circuits at the contact hole 6 portion will not occur. Therefore, the line width of the first and second superconducting lines 1.2 is 11? The line width t1'8 can be selected as the minimum dimension regardless of the presence or absence of a contact hole, and the circuit can be miniaturized.

At this time, it is appropriate that the width of the contact hole is the line width of the second superconducting line plus the alignment dimension 2n. Further, since the depth of the contact hole 6 is up to the first insulating layer 5 at its deepest, it is easy to set the film thickness of the third superconducting line 3. Furthermore, the thickness of the first insulating layer 5 can be selected to be thin. The inductance of the second superconducting lines 1 and 2 can be lowered. This also leads to faster circuits.

(Example 2) FIG. 2 (aXb) is a diagram for explaining a second example of the present invention. FIG. 2(a) shows a plan view of the second embodiment, and FIG. 2(b) is a sectional view taken along BB' in FIG. 2(a). A superconducting layer, such as Nb The first film is deposited by sputter deposition and etched by reactive ion etching, for example. A second superconducting line 11.12 is formed. A second insulating layer 14 covering the superconducting line, such as a SiO film formed by resistance heating vapor deposition, a silica film formed by spin coating and baking, or a 5102 film formed by bias sputtering, etc. Deposit. At least a portion of the second insulator layer 14 is covered with the second insulator layer 14.
A third insulator 16 having an opening extending over the superconducting line 12, for example, Al2 formed by anodic oxidation method.
0371! Alternatively, an Al2O3 film formed by a U plasma oxidation method, an Al2O3 film formed by a sputter deposition method, or the like is deposited. The opening is formed by, for example, a lift-off method. That is, the third insulator 16
The opening is formed by patterning and leaving a photoresist in the opening before depositing the third insulator 16, and removing the photoresist together with the third insulator 16 after the deposition. Using the third insulating layer 16 as an etching mask, the second insulating layer 1
4 is etched using, for example, a reactive ion etching method to form a contact hole 17. The etching conditions at this time are that the etching rate of the second insulator is the superconducting line, the etching rate of the first insulator is the same as that of the superconducting line, and the etching rate of the second insulator is the same as that of the first insulator. and the etching rate of the third insulator. Subsequently, a superconducting layer such as a Nb film is deposited on the second insulating layer 14 and the contact hole 16 to a thickness equal to or greater than the depth of the contact hole 17 by sputter deposition, and a third layer is deposited by, for example, reactive ion etching. A superconducting line 13 is formed. The third superconducting line 1
3 and the second superconducting line 12 are electrically connected through the contact hole 16.

According to the formation method of the present invention, even if over-etching is performed at the time of etching the contact hole portion due to non-uniform etching or variation in film thickness when forming the contact hole 17, the etching will not occur on the first insulator. It is stopped at layer 15.

Therefore, even if a superconducting layer exists under the first insulator layer, there is no possibility of errors such as interlayer short circuits occurring at the contact hole portion. Therefore, the line width t118 and line width ζ'19 of the first and second superconducting lines 11, 12 can be selected based on the minimum dimensions regardless of the presence or absence of a contact hole, and the circuit can be miniaturized. At this time, it is appropriate that the width of the contact hole is the line width of the second superconducting line plus the alignment dimension 2n. Further, since the contact hole 17 has a depth up to the first insulating layer 15 even when it is at its deepest, it is easy to set the thickness of the third superconducting line 13. Furthermore, since the first insulating layer 15 is hardly etched, its film thickness can be selected to be thin. Therefore, the first. Second superconducting line 11.
12 inductance can be lowered. This also leads to faster circuits. Further, by using the formation method of this embodiment, the present invention can be continuously applied to the case where contact is made between the third superconducting line and its upper layer.

(Effects of the Invention) According to the method for forming a superconducting line of the present invention, the line width and line spacing of the superconducting line can be minimized regardless of the presence or absence of contact holes, and the circuit can be significantly miniaturized. It is possible. Furthermore, the maximum depth of the contact hole is determined, and it is easy to set the film thickness of the upper line. Furthermore, the inductance can be reduced by thinning the insulator under the superconducting line.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are diagrams for explaining the present invention in detail,
FIG. 1(a) is a plan view of the first embodiment, and FIG. 1(b) is a sectional view of the first embodiment. FIG. 2(a) is a plan view of the second embodiment, and FIG. 2(b) is a sectional view of the second embodiment. FIG. 3 is a diagram for explaining the present invention in detail, and FIG. 3(a) is a plan view of a conventional example, and FIG. 3(b) is a sectional view of the conventional example. In each figure, 1.11.31...first superconducting line, 2.12.32...second superconducting line, 3
．． 13.33...Third superconducting line, 5.15.35
...First insulator layer, 4.14.34...Second insulator layer, 16...Third insulator layer, 6.17.36.
...Contact hole, 7.18.38... Line width of superconducting line, 8°19, 38.39... Width between superconducting lines, 9.20.40... Alignment dimension, 41... - Indicates the width of the contact hole. Figure 1 (b) Figure 7 (b) Figure 3 (mun)

Claims (1)

[Claims] A method for forming a superconducting line including at least a step of forming a pattern of first and second insulators and superconducting wiring by etching, wherein the superconducting wiring is arranged between the first and second insulators, and the superconducting wiring is arranged between the first and second insulators, Under the condition that the etching rate of the insulator is higher than the etching rate of the first insulator and the superconducting wiring, the second insulator is etched at least partially on the superconducting wiring. A method for forming a superconducting line, the method comprising the step of etching a contact hole of a certain size.