Summary of the invention
The purpose of this invention is to provide a kind of TFT-LCD array base palte and manufacture method thereof, under the prerequisite that guarantees TFT channel region performance, reduce the size of thin-film transistor, improve aperture opening ratio.
To achieve these goals, the invention provides a kind of TFT-LCD manufacturing method of array base plate, comprising:
Step 1, at substrate deposition grid metallic film, form the figure that comprises grid line and gate electrode by composition technique;
Step 2, deposit gate insulation layer, semiconductive thin film, doped semiconductor films and source at the substrate of completing steps 1 and leak metallic film, employing forms the figure that comprises active layer, data wire, source electrode, drain electrode and TFT channel region with halftoning or the gray mask plate of pellicle by composition technique, and the source electrode of described formation and the width of drain electrode are 2.8 μ m~3.0 μ m;
Step 3, on the substrate of completing steps 2 deposit passivation layer, form the figure comprise passivation layer via hole by composition technique, described passivation layer via hole is positioned at the top of drain electrode;
Step 4, on the substrate of completing steps 3 the deposit transparent conductive film, form the figure comprise pixel electrode by composition technique, described pixel electrode is connected with drain electrode by passivation layer via hole;
Wherein, the described first semi-transparent film is identical with the thickness of described the second semi-transparent film, but transmitance is different; Or described first semi-transparent film identical with the material of described the second semi-transparent film, but thickness is different.
Described step 2 comprises:
Step 21, using plasma strengthen chemical gaseous phase depositing process, deposit successively gate insulation layer, semiconductive thin film and doped semiconductor films;
The method of step 22, employing magnetron sputtering or thermal evaporation, sedimentary origin leaks metallic film;
Step 23, leak metallic film in described source and apply one deck positive photoresist;
Step 24, employing expose with halftoning or the gray mask plate of pellicle, make photoresist form unexposed area, half exposure area, compound exposure area and complete exposure area, wherein, unexposed area is corresponding to data wire, source electrode and drain electrode figure region, and half exposure area is corresponding to TFT channel region figure region between source electrode and the drain electrode; Compound exposure area is corresponding to the source electrode outside and region, the drain electrode outside; Complete exposure area corresponding to above-mentioned figure with exterior domain;
After step 25, the development treatment, the photoresist thickness of unexposed area does not change, and forms the complete reserve area of photoresist; The photoresist thickness attenuation of half exposure area forms photoresist half reserve area; The photoresist of compound exposure area and complete exposure area is completely removed, and forms photoresist and removes the zone fully;
Step 26, by the first time etching technics etch away photoresist fully and remove the source in zone fully and leak metallic film, doped semiconductor films and semiconductive thin film, form data wire and active layer figure;
Step 27, remove the photoresist of photoresist half reserve area by cineration technics, expose this regional source and leak metallic film;
Step 28, leak metallic film and doped semiconductor films by the source that the second time, etching technics etched away photoresist half reserve area fully, and etch away the semiconductive thin film of segment thickness, expose semiconductive thin film, formation source electrode, drain electrode and TFT channel region figure, the source electrode of described formation and the width of drain electrode are 2.8 μ m~3.0 μ m;
Step 29, peel off remaining photoresist.
Described halftoning or gray mask plate with pellicle comprises mask substrate; be formed with light tight film, the first semi-transparent film and the second semi-transparent film on the mask substrate; light tight film is used to form light tight zone; make the photoresist of its correspondence position form unexposed area; the first semi-transparent film is used to form the first semi-transparent zone; make the photoresist of its correspondence position form half exposure area; the second semi-transparent film is used to form the second semi-transparent zone, makes the photoresist of its correspondence position form compound exposure area.
Described compound exposure area forms by seeing through with vertical direction that the second semi-transparent film enters the ultraviolet in the second semi-transparent zone and exposing together with incline direction enters the second semi-transparent zone from the second semi-transparent film outside ultraviolet.The exposure effect of compound exposure area is equal to the exposure effect of complete exposure area.
The first semi-transparent film is identical with the second semi-transparent film thickness, the first semi-transparent film adopt light transmittance be 35%~45% half see through material, the second semi-transparent film adopt light transmittance be 55%~65% half see through material.
The described first semi-transparent film adopts half of identical transmitance to see through material with the second semi-transparent film, and the second semi-transparent film thickness is 60%~70% of the first semi-transparent film thickness.
To achieve these goals, the present invention also provides a kind of TFT-LCD array base palte, comprises grid line and data wire, forms pixel electrode and thin-film transistor in the pixel region that described grid line and data wire limit, and described thin-film transistor comprises:
Gate electrode is formed on the substrate, and is connected with grid line;
Gate insulation layer is formed on gate electrode and the grid line, and covers whole substrate;
Semiconductor layer is formed on the gate insulation layer, and is positioned at the top of gate electrode;
Doping semiconductor layer is formed on the semiconductor layer;
The source electrode is formed on the doping semiconductor layer, and an end is positioned at the top of gate electrode, and the other end is connected with data wire, and the width of described source electrode is 2.8 μ m~3.0 μ m;
Drain electrode is formed on the doping semiconductor layer, and an end is positioned at the top of gate electrode, is oppositely arranged with the source electrode, and the width of described drain electrode is 2.8 μ m~3.0 μ m;
The TFT channel region is formed between source electrode and the drain electrode, and the doping semiconductor layer of TFT channel region is etched away fully, and etches away the semiconductor layer of segment thickness, and the semiconductor layer of TFT channel region is come out;
Passivation layer is formed on source electrode, drain electrode and the TFT channel region, and covers whole substrate, offers the passivation layer via hole that drain electrode is connected with pixel electrode in the drain electrode position.
The invention provides a kind of TFT-LCD array base palte and manufacture method thereof, by adopting halftoning or the gray mask plate with pellicle, under the prerequisite that guarantees TFT channel region performance, the width of source of the present invention electrode and drain electrode is reduced greatly, with respect to the source electrode of prior art and the width of drain electrode, the width of source of the present invention electrode and drain electrode has reduced 50%, therefore reduced to greatest extent the size of thin-film transistor, improved aperture opening ratio, not only can increase brightness, and can reduce the brightness of backlight, thereby save energy consumption and manufacturing cost.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is the flow chart of TFT-LCD manufacturing method of array base plate of the present invention, comprising:
Step 1, at substrate deposition grid metallic film, form the figure that comprises grid line and gate electrode by composition technique;
Step 2, deposit gate insulation layer, semiconductive thin film, doped semiconductor films and source at the substrate of completing steps 1 and leak metallic film, employing forms the figure that comprises active layer, data wire, source electrode, drain electrode and TFT channel region with halftoning or the gray mask plate of pellicle by composition technique, and the source electrode of described formation and the width of drain electrode are 2.8 μ m~3.0 μ m;
Step 3, on the substrate of completing steps 2 deposit passivation layer, form the figure comprise passivation layer via hole by composition technique, described passivation layer via hole is positioned at the top of drain electrode;
Step 4, on the substrate of completing steps 3 the deposit transparent conductive film, form the figure comprise pixel electrode by composition technique, described pixel electrode is connected with drain electrode by passivation layer via hole.
The invention provides a kind of TFT-LCD manufacturing method of array base plate, by adopting halftoning or the gray mask plate with pellicle, the width of source of the present invention electrode and drain electrode is reduced greatly.Wherein, adopting with the halftoning of pellicle or the composition technique of gray mask plate is a kind of composition technique that adopts the multistep lithographic method, forms active layer, data wire, source electrode and drain electrode by a composition technique.
Fig. 2 is the flow chart that forms active layer, data wire, source electrode and drain electrode in the TFT-LCD manufacturing method of array base plate of the present invention, and in technical scheme shown in Figure 1, described step 2 comprises:
Step 21, using plasma strengthen chemical gaseous phase depositing process, deposit successively gate insulation layer, semiconductive thin film and doped semiconductor films;
The method of step 22, employing magnetron sputtering or thermal evaporation, sedimentary origin leaks metallic film;
Step 23, leak metallic film in described source and apply one deck positive photoresist;
Step 24, employing expose with halftoning or the gray mask plate of pellicle, make photoresist form unexposed area, half exposure area, compound exposure area and complete exposure area, wherein, unexposed area is corresponding to data wire, source electrode and drain electrode figure region, and half exposure area is corresponding to TFT channel region figure region between source electrode and the drain electrode; Compound exposure area is corresponding to the source electrode outside and region, the drain electrode outside; Complete exposure area corresponding to above-mentioned figure with exterior domain;
After step 25, the development treatment, the photoresist thickness of unexposed area does not change, and forms the complete reserve area of photoresist; The photoresist thickness attenuation of half exposure area forms photoresist half reserve area; The photoresist of compound exposure area and complete exposure area is completely removed, and forms photoresist and removes the zone fully;
Step 26, by the first time etching technics etch away photoresist fully and remove the source in zone fully and leak metallic film, doped semiconductor films and semiconductive thin film, form data wire and active layer figure;
Step 27, remove the photoresist of photoresist half reserve area by cineration technics, expose this regional source and leak metallic film;
Step 28, leak metallic film and doped semiconductor films by the source that the second time, etching technics etched away photoresist half reserve area fully, and etch away the semiconductive thin film of segment thickness, expose semiconductive thin film, formation source electrode, drain electrode and TFT channel region figure, the source electrode of described formation and the width of drain electrode are 2.8 μ m~3.0 μ m;
Step 29, peel off remaining photoresist.
Fig. 3~Figure 16 is the manufacture process schematic diagram of TFT-LCD manufacturing method of array base plate of the present invention, can further specify technical scheme of the present invention, in the following description, the alleged composition technique of the present invention comprises the techniques such as photoresist coating, mask, exposure, etching and photoresist lift off, and photoresist adopts positive photoresist.
Fig. 3 is for the first time plane graph after the composition technique of TFT-LCD array base palte of the present invention, and what reflect is the structure of a pixel cell, Fig. 4 be among Fig. 3 A1-A1 to profile.At first adopt the method for magnetron sputtering or thermal evaporation, at substrate 1 (such as glass substrate or quartz base plate) deposition one deck grid metallic film, the grid metallic film can adopt the single thin film of aluminium, chromium, tungsten, tantalum, titanium, molybdenum or aluminium nickel, also can adopt the multi-layer compound film that is made of above-mentioned single thin film.Adopt the normal masks plate that the grid metallic film is carried out composition, form the figure that comprises gate electrode 2 and grid line 11 at substrate 1, as shown in Figure 3 and Figure 4.In the practical application, the present invention for the first time also can form the public electrode line graph in the composition technique simultaneously, forms storage capacitance structure of (Cs on Common) on public electrode wire.
Fig. 5 is for the second time plane graph after the composition technique of TFT-LCD array base palte of the present invention, and what reflect is the structure of a pixel cell, Fig. 6 be among Fig. 5 A2-A2 to profile.On the substrate of finishing the said structure figure, at first deposit gate insulation layer, semiconductive thin film, doped semiconductor films and source and leak metallic film, then form active layer, data wire 12, source electrode 6, drain electrode 7 and TFT channel region figure by composition technique, as shown in Figure 5 and Figure 6.The present invention for the second time composition technique is a kind of composition technique that adopts the multistep lithographic method, and detailed process is described as follows.
Fig. 7 be TFT-LCD array base palte of the present invention for the second time in the composition technique behind each layer film of deposition A2-A2 to profile.At first using plasma strengthens chemical vapour deposition (CVD) (being called for short PECVD) method, deposit successively gate insulation layer 3, semiconductive thin film 23 and doped semiconductor films 24, then adopt the method for magnetron sputtering or thermal evaporation, metallic film 21 is leaked in deposition one deck source, as shown in Figure 7.Gate insulation layer 3 can adopt oxide, nitride or oxynitrides, and the single thin film that metallic film 21 can adopt aluminium, chromium, tungsten, tantalum, titanium, molybdenum or aluminium nickel is leaked in the source, also can adopt the multi-layer compound film that is made of above-mentioned single thin film.
Fig. 8 be TFT-LCD array base palte of the present invention for the second time in the composition technique during exposure A2-A2 to profile.At first leak metallic film 21 in the source and apply one deck positive photoresist 22, then adopt halftoning or 30 pairs of photoresists 22 of gray mask plate with pellicle to expose, make photoresist 22 form unexposed area A, half exposure area B, compound exposure area C and complete exposure area D, as shown in Figure 8.
It is a kind of mask plates with the semi-transparent zone of two classes that the present invention adopts halftoning or gray mask plate 30 with pellicle, and the semi-transparent zone of a class is used to form half exposure area B, and another kind of semi-transparent zone is used to form compound exposure area C.Particularly, the present invention adopts halftoning or the gray mask plate 30 with pellicle to comprise mask substrate 31, is formed with light tight film 32, the first semi-transparent film 33 and the second semi-transparent film 34 on the mask substrate 31.Two light tight films 32 are used to form light tight zone, and during exposure, ultraviolet 40 can't see through light tight zone, make the photoresist of its correspondence position form unexposed area A, and unexposed area A is corresponding to data wire, source electrode and drain electrode figure region; The first semi-transparent film 33 is between two light tight films 32, be used to form the first semi-transparent zone, during exposure, ultraviolet 40 can only partly see through the first semi-transparent zone, make the photoresist of its correspondence position form half exposure area B, half exposure area B is corresponding to TFT channel region figure region between source electrode and the drain electrode; The second semi-transparent film 34 is positioned at the outside of two light tight films 32, be used to form the second semi-transparent zone, during exposure, ultraviolet 40 parts of vertical direction see through the second semi-transparent zone, the ultraviolet 40 of incline direction also enters into the second semi-transparent zone from the outside of the second semi-transparent film 34 simultaneously, make the photoresist of its correspondence position form compound exposure area C, compound exposure area C is corresponding to the source electrode outside and region, the drain electrode outside; Other zone on the mask substrate 31 forms complete transmission region, and during exposure, ultraviolet 40 all passes complete transmission region, makes the photoresist of its correspondence position form complete exposure area D, complete exposure area D corresponding to above-mentioned figure with exterior domain.This shows, the ultraviolet 40 that enters the second semi-transparent zone comprises two parts: the ultraviolet 40 that sees through from the second semi-transparent film 34 and the ultraviolet 40 that enters from the second semi-transparent film 34 exterior lateral area, two parts ultraviolet 40 makes the photoresist exposure of this zone correspondence together, forms compound exposure area C.In actual the use, by designing the transmitance of the second semi-transparent film 34, can make the exposure effect of the compound exposure area C of the present invention be equal to complete exposure area D.
Fig. 9 be after TFT-LCD array base palte of the present invention develops in the composition technique for the second time A2-A2 to profile.After the development treatment, the photoresist thickness of unexposed area A does not change, and forms the complete reserve area of photoresist, corresponding to data wire, source electrode and drain electrode figure region; The photoresist thickness attenuation of half exposure area B forms photoresist half reserve area, corresponding to TFT channel region figure region between source electrode and the drain electrode; The photoresist of compound exposure area C and complete exposure area D is completely removed, and forms photoresist and removes the zone fully, corresponding to the zone beyond the above-mentioned figure, as shown in Figure 9.
Figure 10 be TFT-LCD array base palte of the present invention for the second time in the composition technique for the first time behind the etching technics A2-A2 to profile.Leak metallic film 21, doped semiconductor films 24 and semiconductive thin film 23 by the source that the first time, etching technics etched away compound exposure area C and complete exposure area D fully, as shown in figure 10.
Figure 11 be TFT-LCD array base palte of the present invention for the second time in the composition technique behind the cineration technics A2-A2 to profile.By cineration technics, remove the photoresist of half exposure area B, expose this regional source and leak metallic film 21, as shown in figure 11.
Figure 12 be TFT-LCD array base palte of the present invention for the second time in the composition technique for the second time behind the etching technics A2-A2 to profile.Leak metallic film 21 and doped semiconductor films 24 by the source that the second time, etching technics etched away half exposure area B fully, and etch away the semiconductive thin film 23 of segment thickness, expose semiconductive thin film 23, as shown in figure 12.
Peel off at last remaining photoresist, finish for the second time composition technique of TFT-LCD array base palte of the present invention.After this composition technique, grid line 11 and data wire 12 define pixel region, active layer is formed on (comprising semiconductor layer 4 and doping semiconductor layer 5) top of gate electrode 2, source electrode 6 and drain electrode 7 are formed on the doping semiconductor layer 5, one end of source electrode 6 is positioned at the top of gate electrode 2, the other end is connected with data wire 12, one end of drain electrode 7 is positioned at the top of gate electrode 2, be oppositely arranged with source electrode 6, form the TFT channel region between source electrode 6 and the drain electrode 7, the doping semiconductor layer 5 of TFT channel region is etched away fully, and etches away the semiconductor layer 4 of segment thickness, the semiconductor layer 4 of TFT channel region is come out, as shown in Figure 5 and Figure 6.Since adopt in this composition technique halftoning or the gray mask plate of the present invention with pellicle, by forming compound exposure area, the width of the present invention's formed source electrode and drain electrode is reduced greatly, be the prior art of 5.7 μ m~6.0 μ m with respect to source electrode and drain electrode width, the width of the present invention's formed source electrode and drain electrode only has 2.8 μ m~3.0 μ m, and width has reduced 50%.
Figure 13 is for the third time plane graph after the composition technique of TFT-LCD array base palte of the present invention, and what reflect is the structure of a pixel cell, Figure 14 be among Figure 13 A3-A3 to profile.On the substrate of finishing the said structure figure, adopt PECVD method deposition one deck passivation layer 8.Passivation layer 8 can adopt oxide, nitride or oxynitrides.Adopt the normal masks plate that passivation layer is carried out composition, form passivation layer via hole 9, passivation layer via hole 9 is positioned at the top of drain electrode 7, such as Figure 13 and shown in Figure 14.In this composition technique, also be formed with simultaneously the grid line interface via hole in grid line interface zone (grid line PAD) and the figures such as data line interface via hole in data line interface zone (data wire PAD), the technique that forms grid line interface via hole and data line interface via pattern by composition technique has been widely used in repeating no more here in the present composition technique.
Figure 15 is the plane graph after the 4th composition technique of TFT-LCD array base palte of the present invention, and what reflect is the structure of a pixel cell, Figure 16 be among Figure 15 A4-A4 to profile.On the substrate of finishing the said structure figure, adopt the method for magnetron sputtering or thermal evaporation, deposit transparent conductive film, transparent conductive film can adopt the materials such as tin indium oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide, also can adopt other metal and metal oxide.Adopt the normal masks plate to form pixel electrode 13 figures by composition technique in pixel region, pixel electrode 13 is connected with drain electrode 7 by passivation layer via hole 9, such as Figure 15 and shown in Figure 16.
In the technique scheme, the present invention can have multiple implementation structure with halftoning or the gray mask plate of pellicle, further specifies the present invention with the halftoning of pellicle or the technical scheme of gray mask plate below by two kinds of typical structures.
Figure 17 is that the present invention is with the halftoning of pellicle or the structural representation of gray mask plate the first embodiment.Present embodiment comprises mask substrate 31 with halftoning or the gray mask plate of pellicle; be formed with light tight film 32, the first semi-transparent film 33 and the second semi-transparent film 34 on the mask substrate 31; light tight film 32 is used to form data wire, source electrode and drain electrode figure; the first semi-transparent film 33 is between the light tight film 32 that forms source electrode and drain electrode figure; be used to form TFT channel region figure, the second semi-transparent film 34 is positioned at light tight film 32 outsides of formation source electrode and drain electrode figure.In the present embodiment, the first semi-transparent film 33 is identical with the thickness of the second semi-transparent film 34, but transmitance is different.Mask substrate 31 can adopt glass substrate or quartz base plate; light tight film 32 can adopt the strong metal material of light-proofness (such as chromium) or resin material (as add black particle in resin); the first semi-transparent film 33 can adopt half of light transmittance 35%~45% to see through material, and the second semi-transparent film 34 adopts half of light transmittance 55%~65% to see through material.Preferably, the first semi-transparent film 33 can adopt half of light transmittance 40% to see through material, and the second semi-transparent film 34 adopts half of light transmittance 60% to see through material.In the practical application, when the photoresist thickness that applies is
The time, behind the exposure imaging, the photoresist thickness that the unexposed area of light tight film 32 correspondences keeps is
The photoresist thickness that half exposure area of the first semi-transparent film 33 correspondences keeps is
In the compound exposure area of the second semi-transparent film 34 correspondences, if only have the ultraviolet exposure of vertical direction, the photoresist thickness of reservation is
And the ultraviolet by incline direction is further after the exposure, photoresist that should the zone all can be removed.
Figure 18 is that the present invention is with the halftoning of pellicle or the structural representation of gray mask plate the second embodiment.Present embodiment comprises mask substrate 31 with halftoning or the gray mask plate of pellicle; be formed with light tight film 32, the first semi-transparent film 33 and the second semi-transparent film 34 on the mask substrate 31, the position of light tight film 32, the first semi-transparent film 33 and the second semi-transparent film 34 is identical with aforementioned the first embodiment.The first semi-transparent film 33 is identical with the material of the second semi-transparent film 34 in the present embodiment, but thickness is different.Mask substrate 31 can adopt glass substrate or quartz base plate; light tight film 32 can adopt the strong metal material of light-proofness (such as chromium) or resin material (as add black particle in resin); the first semi-transparent film 33 and the second semi-transparent film 34 can adopt half of light transmittance 35%~45% to see through material, but the second semi-transparent film 34 thickness are 60%~70% of the first semi-transparent film 33 thickness.Preferably, the first semi-transparent film 33 and the second semi-transparent film 34 can adopt half of light transmittance 40% to see through material, but the second semi-transparent film 34 thickness are 2/3 of the first semi-transparent film 33 thickness.
In the technique scheme of the present invention, owing to be provided with the second semi-transparent film 34, the second semi-transparent film 34 can stop the ultraviolet of its outside incline direction, the photoresist that therefore can not cause the TFT channel region is crossed thin or distortion, can not cause incident ray to cause the unsteadiness of thin-film transistor TFT channel region, not have harmful effect for dot structure and effect.
The invention provides a kind of TFT-LCD manufacturing method of array base plate, by adopting halftoning or the gray mask plate with pellicle, under the prerequisite that guarantees TFT channel region performance, the width of source of the present invention electrode and drain electrode is reduced greatly, with respect to the source electrode of prior art and the width of drain electrode, the width of source of the present invention electrode and drain electrode has reduced 50%, has therefore reduced to greatest extent the size of thin-film transistor.Brightness is an important parameter of reflection TFT-LCD performance, and determine that the most important factor of brightness is aperture opening ratio, because the width of source of the present invention electrode and drain electrode has reduced 50%, the size of thin-film transistor is little, so technical solution of the present invention can realize high aperture, high aperture not only can increase brightness, and can reduce the brightness of backlight, thereby saves energy consumption and manufacturing cost.This shows that the present invention has broad application prospects.
The present invention also provides a kind of TFT-LCD array base palte, is prepared from by TFT-LCD manufacturing method of array base plate of the present invention.Such as Figure 15 and shown in Figure 16, the agent structure of TFT-LCD array base palte of the present invention comprises grid line 11, data wire 12, pixel electrode 13 and the thin-film transistor that is formed on the substrate 1, orthogonal grid line 11 and data wire 12 have defined pixel region, thin-film transistor and pixel electrode 13 are formed in the pixel region, grid line 11 is used for providing start signal to thin-film transistor, and data wire 12 is used for providing data-signal to pixel electrode 13.Particularly, thin-film transistor comprises gate electrode 2, gate insulation layer 3, semiconductor layer 4, doping semiconductor layer (ohmic contact layer) 5, source electrode 6, drain electrode 7 and passivation layer 8, and gate electrode 2 is formed on the substrate 1, and is connected with grid line 11; Gate insulation layer 3 is formed on gate electrode 2 and the grid line 11 and covers whole substrate 1, and active layer (semiconductor layer 4 and doping semiconductor layer 5) is formed on the gate insulation layer 3 and is positioned at the top of gate electrode 2; Source electrode 6 and drain electrode 7 are formed on the doping semiconductor layer 5, one end of source electrode 6 is positioned at the top of gate electrode 2, the other end is connected with data wire 12, the width of source electrode 6 is 2.8 μ m~3.0 μ m, one end of drain electrode 7 is positioned at the top of gate electrode 2, the other end is connected with pixel electrode 13 by the passivation layer via hole 9 of offering on the passivation layer 8, the width of drain electrode 7 is 2.8 μ m~3.0 μ m, form the TFT channel region between source electrode 6 and the drain electrode 7, the doping semiconductor layer 5 of TFT channel region is etched away fully, and etch away the semiconductor layer 4 of segment thickness, the semiconductor layer 4 of TFT channel region is come out; Passivation layer 8 is formed on data wire 12, source electrode 6 and the drain electrode 7 and covers whole substrate 1, offers the passivation layer via hole 9 that drain electrode 7 is connected with pixel electrode 13 in drain electrode 7 positions.Pixel electrode 13 is formed on the passivation layer 8, is connected with drain electrode 7 by passivation layer via hole 9.
It should be noted that at last: above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.