CN101799603B - TFT-LCD array substrate and manufacture method thereof - Google Patents
TFT-LCD array substrate and manufacture method thereof Download PDFInfo
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- CN101799603B CN101799603B CN200910077686.3A CN200910077686A CN101799603B CN 101799603 B CN101799603 B CN 101799603B CN 200910077686 A CN200910077686 A CN 200910077686A CN 101799603 B CN101799603 B CN 101799603B
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- 238000000034 method Methods 0.000 title claims abstract description 118
- 239000000758 substrate Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010408 film Substances 0.000 claims abstract description 107
- 238000003860 storage Methods 0.000 claims abstract description 64
- 239000010409 thin film Substances 0.000 claims abstract description 36
- 238000009413 insulation Methods 0.000 claims abstract description 24
- 238000000059 patterning Methods 0.000 claims description 76
- 229920002120 photoresistant polymer Polymers 0.000 claims description 74
- 239000004065 semiconductor Substances 0.000 claims description 54
- 238000002161 passivation Methods 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 9
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 8
- 238000002207 thermal evaporation Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 4
- 239000007792 gaseous phase Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 15
- 238000010276 construction Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a kind of TFT-LCD array substrate and manufacture method thereof.Array base palte comprises and is formed in grid line on substrate and data line, and form pixel electrode and thin film transistor (TFT) in the pixel region that described grid line and data line limit, the top of described grid line is formed with the storage electrode forming memory capacitance together with described pixel electrode.Further, described storage electrode and described data line are arranged with layer, and described storage electrode is connected with described grid line by the grid insulating layer through hole that gate insulation layer film is offered.Described storage electrode subsection setup is above the grid line of described data line both sides.The present invention, by being arranged on above grid line by storage electrode, improves unit area memory capacitance, simultaneously can not occluded pixels region, therefore effectively improves aperture opening ratio and display brightness, improves display quality on the whole.
Description
Technical field
The present invention relates to a kind of LCD Structure of thin film transistor and manufacture method thereof, especially a kind of TFT-LCD array substrate and manufacture method thereof.
Background technology
Thin Film Transistor-LCD (ThinFilmTransistorLiquidCrystalDisplay is called for short TFT-LCD) has the features such as volume is little, low in energy consumption, radiationless, in current flat panel display market, occupy leading position.
TFT-LCD is formed primarily of to the array base palte of box and color membrane substrates, and wherein array base palte is formed with thin film transistor (TFT) and the pixel electrode of matrix arrangement, each pixel electrode is controlled by thin film transistor (TFT).When thin film transistor (TFT) is opened, pixel electrode charges in opening time, after charging terminates, again charges when pixel electrode voltage will be maintained to scanning next time.In general, liquid crystal capacitance is little, and only can not maintain the voltage of pixel electrode by liquid crystal capacitance, therefore existing design all arranges a memory capacitance to keep the voltage of pixel electrode.Usually, the main Types of memory capacitance is: memory capacitance is (CsonGate), memory capacitance (CsonCommon) and unitized construction on public electrode wire on grid line, unitized construction refers to that a memory capacitance part is on controlling grid scan line, and another part is on public electrode wire.But no matter be which kind of type, prior art is all adopt grid metal layer thin film as memory capacitance battery lead plate, and is folded with gate insulation layer film and passivation layer film between the pixel electrode as another battery lead plate of memory capacitance.From the computing formula of memory capacitance, distance between the size of unit area memory capacitance and two battery lead plates is inversely proportional to, due to sandwiched gate insulation layer film and passivation layer film between memory capacitance two battery lead plate in existing TFT-LCD array substrate, distance between two battery lead plates is comparatively large, therefore causes unit area memory capacitance relatively little.
Summary of the invention
The object of this invention is to provide a kind of TFT-LCD array substrate and manufacture method thereof, not only can effectively improve unit area memory capacitance, also there is the advantage such as high aperture and high display brightness.
To achieve these goals, the invention provides a kind of TFT-LCD array substrate, comprise and be formed in grid line on substrate and data line, pixel electrode and thin film transistor (TFT) is formed in the pixel region that described grid line and data line limit, the top of described grid line is formed with the storage electrode forming memory capacitance together with described pixel electrode, and described pixel electrode is connected with drain electrode by described passivation layer via hole.
Described storage electrode and described data line are arranged with layer.
Described storage electrode is connected with described grid line by the grid insulating layer through hole that gate insulation layer film is offered.
Described storage electrode subsection setup is above the grid line of described data line both sides.
Also be formed in described pixel region and block bar, described in block bar and described storage electrode is arranged with layer, and to be connected with described storage electrode.
To achieve these goals, present invention also offers a kind of TFT-LCD array substrate manufacture method, comprising:
Step 1, on substrate, deposit grid metal layer thin film, formed the figure comprising grid line and gate electrode by patterning processes;
Step 2, on the substrate of completing steps 1, deposit gate insulation layer film, semiconductor layer film and doped semiconductor layer film, formed the figure including active layer and grid insulating layer through hole by patterning processes, described grid insulating layer through hole is positioned at the top of described grid line;
Step 3, on the substrate of completing steps 2, deposit source and drain metal layer thin film, the figure comprising data line, source electrode, drain electrode, TFT channel region and storage electrode is formed by patterning processes, described storage electrode is positioned on the grid line of described data line both sides, and is connected with described grid line by described grid insulating layer through hole;
Step 4, on the substrate of completing steps 3 deposit passivation layer film, formed by patterning processes and comprise the figure of passivation layer via hole, described passivation layer via hole is positioned at the top of described drain electrode;
Step 5, on the substrate of completing steps 4 deposit transparent conductive film, formed by patterning processes and comprise the figure of pixel electrode, described pixel electrode is connected with drain electrode by described passivation layer via hole.
Described step 2 comprises:
Using plasma strengthens chemical gaseous phase depositing process and deposits gate insulation layer film, semiconductor layer film and doped semiconductor layer film successively;
Adopt shadow tone or gray mask plate to be formed the figure including active layer and grid insulating layer through hole by patterning processes, described grid insulating layer through hole is positioned at the top of described grid line.
Described employing shadow tone or gray mask plate form by patterning processes the figure including active layer and grid insulating layer through hole and comprise:
Described doped semiconductor layer film applies one deck photoresist;
Adopt shadow tone or the exposure of gray mask plate, make photoresist form photoresist and remove region, the complete reserve area of photoresist and photoresist half reserve area completely; The complete reserve area of photoresist corresponds to active layer pattern region, and photoresist is removed region completely and corresponded to grid insulating layer through hole figure region, and photoresist half reserve area corresponds to the region beyond above-mentioned figure; After development treatment, the photoresist thickness of the complete reserve area of photoresist does not change, and the photoresist that region removed completely by photoresist is completely removed, and the photoresist thickness of photoresist half reserve area reduces;
Etch away photoresist completely by first time etching technics and remove the doped semiconductor layer film in region, semiconductor layer film and gate insulation layer film completely, form grid insulating layer through hole figure;
Removed the photoresist of photoresist half reserve area by cineration technics, expose the doped semiconductor layer film in this region;
Etched away doped semiconductor layer film and the semiconductor layer film of photoresist half reserve area by second time etching technics completely, form active layer pattern;
Peel off remaining photoresist.
Described step 3 comprises: the method deposition source and drain metal layer thin film adopting magnetron sputtering or thermal evaporation, normal masks plate is adopted to carry out composition by patterning processes to source and drain metal layer thin film, form data line, source electrode, drain electrode, TFT channel region and storage electrode figure, wherein storage electrode is positioned at above the grid line of data line both sides, and is connected with grid line by grid insulating layer through hole.
Described step 3 is also formed simultaneously blocks bar figure, described in block bar and be connected with storage electrode.
The invention provides a kind of TFT-LCD array substrate and manufacture method thereof, storage electrode is arranged on above grid line, storage electrode and data line, source electrode and drain electrode are arranged with layer, being formed with in a patterning processes, are formed two battery lead plates of memory capacitance by storage electrode and pixel electrode.Compare with the existing storage capacitor construction of passivation layer film with sandwiched gate insulation layer film between two battery lead plates, the distance between memory capacitance of the present invention two battery lead plates only has the thickness of passivation layer, therefore improves unit area memory capacitance.Because storage electrode is arranged on above grid line, can not occluded pixels region, therefore the present invention effectively improves aperture opening ratio and display brightness, improves display quality on the whole.Further, because storage electrode of the present invention is arranged on above grid line, therefore can design suitable memory capacitance by the area changing storage electrode according to actual needs, this ensures that there sufficient memory capacitance surplus, effectively can reduce leaping voltage Δ V
p, improve display quality.
Accompanying drawing explanation
Fig. 1 is the planimetric map of a TFT-LCD array substrate of the present invention pixel cell;
Fig. 2 be in Fig. 1 A1-A1 to sectional view;
Fig. 3 be in Fig. 1 B1-B1 to sectional view;
Fig. 4 is the planimetric map of a pixel cell after TFT-LCD array substrate of the present invention first time patterning processes;
Fig. 5 be in Fig. 4 A2-A2 to sectional view;
Fig. 6 be in Fig. 4 B2-B2 to sectional view;
Fig. 7 is the planimetric map of a pixel cell after TFT-LCD array substrate of the present invention second time patterning processes;
Fig. 8 be in TFT-LCD array substrate of the present invention second time patterning processes after exposure imaging A3-A3 to sectional view;
Fig. 9 be in TFT-LCD array substrate of the present invention second time patterning processes after exposure imaging B3-B3 to sectional view;
Figure 10 be TFT-LCD array substrate of the present invention second time patterning processes in first time etching technics after B3-B3 to sectional view;
Figure 11 be in TFT-LCD array substrate of the present invention second time patterning processes after cineration technics A3-A3 to sectional view;
Figure 12 be in TFT-LCD array substrate of the present invention second time patterning processes after cineration technics B3-B3 to sectional view;
Figure 13 be TFT-LCD array substrate of the present invention second time patterning processes in second time etching technics after A3-A3 to sectional view;
Figure 14 be TFT-LCD array substrate of the present invention second time patterning processes in second time etching technics after B3-B3 to sectional view;
Figure 15 be TFT-LCD array substrate of the present invention second time patterning processes after A3-A3 to sectional view;
Figure 16 is the planimetric map of a pixel cell after TFT-LCD array substrate of the present invention third time patterning processes;
Figure 17 be in Figure 16 A4-A4 to sectional view;
Figure 18 be in Figure 16 B4-B4 to sectional view;
Figure 19 is the planimetric map of a pixel cell after TFT-LCD array substrate of the present invention 4th patterning processes;
Figure 20 be in Figure 19 A5-A5 to sectional view;
Figure 21 be in Figure 19 B5-B5 to sectional view;
Figure 22 is the process flow diagram of TFT-LCD array substrate manufacture method of the present invention;
Figure 23 is the process flow diagram of TFT-LCD array substrate manufacture method specific embodiment of the present invention.
Description of reference numerals:
1-substrate; 2-gate electrode; 3-gate insulation layer film;
4-semiconductor layer film; 5-doped semiconductor layer film; 6-source electrode;
7-drain electrode; 8-passivation layer film; 9-pixel electrode;
10-grid line; 11-data line; 12-grid insulating layer through hole;
13-storage electrode; 14-passivation layer via hole; 30-photoresist.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is the planimetric map of a TFT-LCD array substrate of the present invention pixel cell, Fig. 2 be in Fig. 1 A1-A1 to sectional view, Fig. 3 be in Fig. 1 B1-B1 to sectional view.As shown in FIG. 1 to 3, the agent structure of TFT-LCD array substrate of the present invention comprises formation grid line 10 on substrate 1, data line 11, pixel electrode 9, thin film transistor (TFT) and storage electrode 13, orthogonal grid line 10 and data line 11 define pixel region, thin film transistor (TFT) and pixel electrode 9 are formed in pixel region, grid line 10 is for providing start signal to thin film transistor (TFT), data line 11 is for providing data-signal to pixel electrode 9, and storage electrode 13 for forming memory capacitance together with pixel electrode 9.Storage electrode 13 of the present invention is arranged on the top of grid line 10, layer same with data line 11.Particularly, TFT-LCD array substrate of the present invention comprises formation grid line 10 on substrate 1 and gate electrode 2, and gate electrode 2 is connected with grid line 10; Gate insulation layer film 3 to be formed on gate electrode 2 and grid line 10 and to cover whole substrate 1, gate insulation layer film 3 offers grid insulating layer through hole 12, at least one grid insulating layer through hole 12 is arranged on grid line 10 position, is connected by grid insulating layer through hole 12 for making storage electrode 13 with grid line 10; Active layer (semiconductor layer film 4 and doped semiconductor layer film 5) to be formed on gate insulation layer film 3 and to be positioned at the top of gate electrode 2; One end of source electrode 6 is formed on active layer, the other end is connected with data line 11, one end of drain electrode 7 is formed on active layer, the other end is connected with pixel electrode 9 by the passivation layer via hole 14 that passivation layer film 8 is offered, TFT channel region is formed between source electrode 6 and drain electrode 7, the doped semiconductor layer film (ohmic contact layer) 5 of TFT channel region is etched completely away, and exposes semiconductor layer film 4; Storage electrode 13 and data line 11, source electrode 6 and the same layer of drain electrode 7, and be positioned at above grid line 10, storage electrode 13 is connected with grid line 10 by the grid insulating layer through hole 12 that gate insulation layer film 3 is offered; Passivation layer film 8 to be formed on data line 11, source electrode 6, drain electrode 7 and storage electrode 13 and to cover whole substrate 1, offers the passivation layer via hole 14 that drain electrode 7 is connected with pixel electrode 9 in drain electrode 7 position; Pixel electrode 9 is formed on passivation layer film 8, and pixel electrode 9 is connected with drain electrode 7 by passivation layer via hole 14.
Fig. 4 ~ Figure 21 is the schematic diagram of TFT-LCD array substrate manufacture process of the present invention, technical scheme of the present invention can be further illustrated, in the following description, the patterning processes alleged by the present invention comprises the techniques such as photoresist coating, mask, exposure, etching, and photoresist is for positive photoresist.
Fig. 4 be TFT-LCD array substrate of the present invention first time patterning processes after a pixel cell planimetric map, Fig. 5 be in Fig. 4 A2-A2 to sectional view, Fig. 6 be in Fig. 4 B2-B2 to sectional view.First the method for magnetron sputtering or thermal evaporation is adopted, at substrate 1 (as glass substrate or quartz base plate) upper deposition grid metal layer thin film, grid metal layer thin film can adopt the metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, also can adopt the multiple layer film be made up of multiple metal layer thin film.Normal masks plate (also claiming dull mask plate) is adopted to be formed the figure comprising grid line 10 and gate electrode 2 by patterning processes, as shown in Fig. 4 ~ Fig. 6.
Fig. 7 is the planimetric map of a pixel cell after TFT-LCD array substrate of the present invention second time patterning processes, Fig. 8 be in TFT-LCD array substrate of the present invention second time patterning processes after exposure imaging A3-A3 to sectional view, Fig. 9 be in TFT-LCD array substrate of the present invention second time patterning processes after exposure imaging B3-B3 to sectional view.On the substrate completing Fig. 4 structure graph, using plasma strengthens chemical vapor deposition (being called for short PECVD) method, deposits gate insulation layer film 3, semiconductor layer film 4 and doped semiconductor layer film 5 (also claiming ohmic contact layer) successively.Gate insulation layer film 3 can select oxide, nitride or oxynitrides, and corresponding reacting gas can be SiH
4, NH
3, N
2mixed gas or SiH
2cl
2, NH
3, N
2mixed gas; The reacting gas of semiconductor layer film 4 correspondence can be SiH
4, H
2mixed gas or SiH
2cl
2, H
2mixed gas; The reacting gas of doped semiconductor layer film 5 correspondence can be SiH
4, PH
3, H
2mixed gas or SiH
2cl
2, PH
3, H
2mixed gas.Subsequently, doped semiconductor layer film 5 applies one deck photoresist 30, adopt shadow tone or the exposure of gray mask plate, make photoresist form complete exposure area A, unexposed area B and half exposure area C.Unexposed area B corresponds to active layer pattern region, and complete exposure area A corresponds to grid insulating layer through hole figure region, and half exposure area C corresponds to the region beyond above-mentioned figure.After development treatment, the photoresist thickness of unexposed area B does not change, form the complete reserve area of photoresist, the photoresist of complete exposure area A is completely removed, form photoresist and remove region completely, the photoresist thickness of half exposure area C reduces, and forms photoresist half reserve area, as shown in Figure 8, Figure 9.
Figure 10 be TFT-LCD array substrate of the present invention second time patterning processes in first time etching technics after B3-B3 to sectional view.Etch away the doped semiconductor layer film 5 of complete exposure area A, semiconductor layer film 4 and gate insulation layer film 3 completely by first time etching technics, form grid insulating layer through hole 12 figure, expose grid line 10 in grid insulating layer through hole 12, as shown in Figure 10.
Figure 11 be in TFT-LCD array substrate of the present invention second time patterning processes after cineration technics A3-A3 to sectional view, Figure 12 be in TFT-LCD array substrate of the present invention second time patterning processes after cineration technics B3-B3 to sectional view.By cineration technics, get rid of the photoresist of half exposure area C, expose the doped semiconductor layer film 5 in this region, as shown in Figure 11, Figure 12.Thickness due to unexposed area B photoresist is greater than the thickness of half exposure area C photoresist, and therefore after cineration technics, unexposed area B is still coated with certain thickness photoresist 30.
Figure 13 be TFT-LCD array substrate of the present invention second time patterning processes in second time etching technics after A3-A3 to sectional view, Figure 14 be TFT-LCD array substrate of the present invention second time patterning processes in second time etching technics after B3-B3 to sectional view.Etched away doped semiconductor layer film 5 and the semiconductor layer film 4 of half exposure area C completely by second time etching technics, form active layer pattern, active layer comprises semiconductor layer film 4 and doped semiconductor layer film 5, as shown in Figure 13, Figure 14.
Figure 15 be TFT-LCD array substrate of the present invention second time patterning processes after A3-A3 to sectional view.Finally peel off remaining photoresist, complete TFT-LCD array substrate of the present invention second time patterning processes, as shown in Fig. 7, Figure 14 and Figure 15.After the present invention's second time patterning processes, active layer is formed in above gate electrode 2, and grid insulating layer through hole 12 is formed in above grid line 10.The concrete shape of grid insulating layer through hole 12 also can be multiple, such as square, circular etc.In practical application, can arrange multiple grid insulating layer through hole structure above grid line 10, the present embodiment illustrate only the structure of employing two grid insulating layer through hole.
Figure 16 is the planimetric map of a pixel cell after TFT-LCD array substrate of the present invention third time patterning processes, Figure 17 be in Figure 16 A4-A4 to sectional view, Figure 18 be in Figure 16 B4-B4 to sectional view.On the substrate completing Fig. 7 structure graph, adopt the method for magnetron sputtering or thermal evaporation, deposition source and drain metal layer thin film, source and drain metal layer thin film can adopt the metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, also can adopt the multiple layer film be made up of multiple metal layer thin film.Normal masks plate is adopted to carry out composition by patterning processes to source and drain metal layer thin film, form data line 11, source electrode 6, drain electrode 7, TFT channel region and storage electrode 13 figure, wherein one end of source electrode 6 is positioned on active layer, the other end is connected with data line 11, one end of drain electrode 7 is positioned on active layer, be oppositely arranged with source electrode 6, TFT channel region is formed between source electrode 6 and drain electrode 7, doped semiconductor layer film 5 between TFT channel region is etched completely away, and the semiconductor layer film 4 of etch away sections thickness, expose semiconductor layer film 4, storage electrode 13 subsection setup in the both sides of data line 11, and is positioned at above grid line 10, is connected, as shown in Figure 16, Figure 17 and Figure 18 by grid insulating layer through hole 12 with grid line 10.In practical application, this patterning processes can also form screening rib construction simultaneously, blocks bar for blocking the light in light leak region further, further, blocks bar and can also connect into an entirety with storage electrode.The shape and size of storage electrode 13 can design according to actual needs.
Figure 19 is the planimetric map of a pixel cell after TFT-LCD array substrate of the present invention 4th patterning processes, Figure 20 be in Figure 19 A5-A5 to sectional view, Figure 21 be in Figure 19 B5-B5 to sectional view.On the substrate completing Figure 16 structure graph, adopt PECVD method deposit passivation layer film 8.Passivation layer film 8 can adopt oxide, nitride or oxynitrides, and corresponding reacting gas can be SiH
4, NH
3, N
2mixed gas or SiH
2cl
2, NH
3, N
2mixed gas.Adopt normal masks plate to carry out composition by patterning processes to passivation layer film 8, form passivation layer via hole 14, passivation layer via hole 14 is positioned at the top of drain electrode 7, as shown in Figure 19, Figure 20 and Figure 21.In this patterning processes, be also formed with the figure such as the grid line interface via hole in grid line interface region (grid line PAD) and the data line interface via hole of data line interface region (data line PAD) simultaneously.The technique forming grid line interface via hole and data line interface via pattern above by patterning processes has been widely used in, in current patterning processes, repeating no more here.
Finally, on the substrate completing said structure figure, adopt the method for magnetron sputtering or thermal evaporation, deposit transparent conductive film, transparent conductive film can adopt the materials such as tin indium oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide, also can adopt other metal and metal oxide.Adopt normal masks plate to form pixel electrode 9 by patterning processes, pixel electrode 9 is connected with drain electrode 7 by passivation layer via hole 14, as shown in FIG. 1 to 3.
Five patterning processes discussed above are only a kind of implementation methods of preparation TFT-LCD array substrate of the present invention, can also by increasing or reduce patterning processes number of times, selecting different materials or combination of materials to realize the present invention in actual use.Such as, TFT-LCD array substrate second time patterning processes of the present invention can adopt the patterning processes of normal masks plate to complete by secondary, namely by once adopting the patterning processes of normal masks plate to form active layer pattern, by once adopting the patterning processes of normal masks plate to form grid insulating layer through hole, repeat no more here.
The invention provides a kind of TFT-LCD array substrate, storage electrode is arranged on above grid line, storage electrode and data line, source electrode and drain electrode are arranged with layer, being formed with in a patterning processes, are formed two battery lead plates of memory capacitance by storage electrode and pixel electrode.Compare with the existing storage capacitor construction of passivation layer film with sandwiched gate insulation layer film between two battery lead plates, the distance between memory capacitance of the present invention two battery lead plates only has the thickness of passivation layer film, therefore improves unit area memory capacitance.Because storage electrode is arranged on above grid line, can not occluded pixels region, therefore the present invention effectively improves aperture opening ratio and display brightness, improves display quality on the whole.
When TFT-LCD works, owing to there is stray capacitance between source electrode and gate electrode, between drain electrode and gate electrode, the moment therefore terminated in pixel electrode charging can produce a leaping voltage Δ V
p, the expression formula of leaping voltage is:
Wherein V
ghfor the cut-in voltage of gate electrode, V
glthe shutoff voltage of gate electrode, C
lcfor liquid crystal capacitance, C
gsfor stray capacitance, C
sfor memory capacitance.Research shows, leaping voltage Δ V
pexistence the polarity of pixel electrode can be made to change, and then cause the voltage difference of positive-negative polarity inconsistent, cause display frame to produce flicker (flicker) phenomenon, seriously have impact on display quality, therefore the upper leaping voltage Δ V requiring to produce of design
pthe smaller the better.Because storage electrode of the present invention is arranged on above grid line, therefore suitable memory capacitance C can be designed by the area changing storage electrode according to actual needs
s, this ensures that there sufficient memory capacitance surplus, effectively can reduce leaping voltage Δ V
p, improve display quality.
Figure 22 is the process flow diagram of TFT-LCD array substrate manufacture method of the present invention, comprising:
Step 1, on substrate, deposit grid metal layer thin film, formed the figure comprising grid line and gate electrode by patterning processes;
Step 2, on the substrate of completing steps 1, deposit gate insulation layer film, semiconductor layer film and doped semiconductor layer film, formed the figure including active layer and grid insulating layer through hole by patterning processes, described grid insulating layer through hole is positioned at the top of described grid line;
Step 3, on the substrate of completing steps 2, deposit source and drain metal layer thin film, the figure comprising data line, source electrode, drain electrode, TFT channel region and storage electrode is formed by patterning processes, described storage electrode is positioned on the grid line of described data line both sides, and is connected with described grid line by described grid insulating layer through hole;
Step 4, on the substrate of completing steps 3 deposit passivation layer film, formed by patterning processes and comprise the figure of passivation layer via hole, described passivation layer via hole is positioned at the top of described drain electrode;
Step 5, on the substrate of completing steps 4 deposit transparent conductive film, formed by patterning processes and comprise the figure of pixel electrode, described pixel electrode is connected with drain electrode by described passivation layer via hole.
In technique scheme of the present invention, because storage electrode is arranged on above grid line, storage electrode and drain electrode, source electrode and data line are arranged with layer, therefore improve unit area memory capacitance.Because storage electrode is arranged on above grid line, can not occluded pixels region, therefore the present invention effectively improves aperture opening ratio and display brightness, improves display quality on the whole.
Figure 23 is the process flow diagram of TFT-LCD array substrate manufacture method specific embodiment of the present invention, and in technical scheme shown in Figure 22, described step 2 comprises:
Step 11, using plasma strengthen chemical gaseous phase depositing process, and the substrate of completing steps 1 deposits gate insulation layer film, semiconductor layer film and doped semiconductor layer film successively;
Step 12, on described doped semiconductor layer film, apply one deck photoresist;
Step 13, employing shadow tone or the exposure of gray mask plate, make photoresist form photoresist and remove region, the complete reserve area of photoresist and photoresist half reserve area completely; The complete reserve area of photoresist corresponds to active layer pattern region, and photoresist is removed region completely and corresponded to grid insulating layer through hole figure region, and photoresist half reserve area corresponds to the region beyond above-mentioned figure; After development treatment, the photoresist thickness of the complete reserve area of photoresist does not change, and the photoresist that region removed completely by photoresist is completely removed, and the photoresist thickness of photoresist half reserve area reduces;
Step 14, etch away photoresist completely by first time etching technics and remove the doped semiconductor layer film in region, semiconductor layer film and gate insulation layer film completely, form grid insulating layer through hole figure;
Step 15, removed the photoresist of photoresist half reserve area by cineration technics, expose the doped semiconductor layer film in this region;
Step 16, etch away doped semiconductor layer film and the semiconductor layer film of photoresist half reserve area completely by second time etching technics, form active layer pattern;
Step 17, peel off remaining photoresist.
The present embodiment is that a kind of multistep etching technics that adopts is formed with the technical scheme of active layer and grid insulating layer through hole figure by patterning processes simultaneously, and its preparation process is introduced in detail in technical scheme shown in earlier figures 7 ~ Figure 15, repeats no more here.
In actual use, the step 2 of TFT-LCD array substrate manufacture method of the present invention can adopt the patterning processes of normal masks plate to complete by secondary, namely by once adopting the patterning processes of normal masks plate to form active layer pattern, grid insulating layer through hole is formed by once adopting the patterning processes of normal masks plate.
In step 1 of the present invention, first the method for magnetron sputtering or thermal evaporation is adopted, at substrate (as glass substrate or quartz base plate) upper deposition grid metal layer thin film, grid metal layer thin film can adopt the metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, also can adopt the multiple layer film be made up of multiple metal layer thin film.Normal masks plate is adopted to be formed the figure comprising grid line and gate electrode by patterning processes.
In step 3 of the present invention, adopt the method for magnetron sputtering or thermal evaporation, deposition source and drain metal layer thin film, source and drain metal layer thin film can adopt the metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, also can adopt the multiple layer film be made up of multiple metal layer thin film.Normal masks plate is adopted to carry out composition by patterning processes to source and drain metal layer thin film, form data line, source electrode, drain electrode, TFT channel region and storage electrode figure, wherein one end of source electrode is positioned on active layer, the other end is connected with data line, one end of drain electrode is positioned on active layer, be oppositely arranged with source electrode, TFT channel region is formed between source electrode and drain electrode, doped semiconductor layer film between TFT channel region is etched completely away, and the semiconductor layer film of etch away sections thickness, expose semiconductor layer film; Storage electrode is positioned at above the grid line of data line both sides, and is connected with grid line by grid insulating layer through hole.In practical application, this patterning processes can also be formed simultaneously block bar figure, blocks bar for blocking the light in light leak region further, further, blocks bar and can also connect into an entirety with storage electrode.The shape and size of storage electrode can design according to actual needs.
In step 4 of the present invention, adopt PECVD method deposit passivation layer film.Passivation layer film can adopt oxide, nitride or oxynitrides, and corresponding reacting gas can be SiH
4, NH
3, N
2mixed gas or SiH
2cl
2, NH
3, N
2mixed gas.Adopt normal masks plate to carry out composition by patterning processes to passivation layer film, form passivation layer via hole, wherein passivation layer via hole is positioned at the top of drain electrode.In this patterning processes, be also formed with the figure such as the grid line interface via hole in grid line interface region and the data line interface via hole in data line interface region simultaneously.The technique forming grid line interface via hole and data line interface via pattern above by patterning processes has been widely used in current patterning processes.
In step 5 of the present invention, adopt the method for magnetron sputtering or thermal evaporation, deposit transparent conductive film, transparent conductive film can adopt the materials such as tin indium oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide, also can adopt other metal and metal oxide.Adopt normal masks plate to form pixel electrode by patterning processes, pixel electrode is connected with drain electrode by passivation layer via hole.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (9)
1. a TFT-LCD array substrate, comprise and be formed in grid line on substrate and data line, pixel electrode and thin film transistor (TFT) is formed in the pixel region that described grid line and data line limit, it is characterized in that, the top of described grid line is formed with the storage electrode forming memory capacitance together with described pixel electrode; Described pixel electrode is connected with drain electrode by passivation layer via hole; Described storage electrode is connected with described grid line by the grid insulating layer through hole that gate insulation layer film is offered, described storage electrode and described pixel electrode above described grid line to be projected to small part overlapping.
2. TFT-LCD array substrate according to claim 1, is characterized in that, described storage electrode and described data line are arranged with layer.
3. TFT-LCD array substrate according to claim 1, is characterized in that, is also formed and blocks bar in described pixel region, described in block bar and described storage electrode is arranged with layer, and to be connected with described storage electrode.
4. TFT-LCD array substrate according to claim 1, is characterized in that, described storage electrode subsection setup is above the grid line of described data line both sides.
5. a TFT-LCD array substrate manufacture method, is characterized in that, comprising:
Step 1, on substrate, deposit grid metal layer thin film, formed the figure comprising grid line and gate electrode by patterning processes;
Step 2, on the substrate of completing steps 1, deposit gate insulation layer film, semiconductor layer film and doped semiconductor layer film, formed the figure including active layer and grid insulating layer through hole by patterning processes, described grid insulating layer through hole is positioned at the top of described grid line;
Step 3, on the substrate of completing steps 2, deposit source and drain metal layer thin film, the figure comprising data line, source electrode, drain electrode, TFT channel region and storage electrode is formed by patterning processes, described storage electrode is positioned on the grid line of described data line both sides, and be connected with described grid line by described grid insulating layer through hole, described storage electrode and described pixel electrode above described grid line to be projected to small part overlapping;
Step 4, on the substrate of completing steps 3 deposit passivation layer film, formed by patterning processes and comprise the figure of passivation layer via hole, described passivation layer via hole is positioned at the top of described drain electrode;
Step 5, on the substrate of completing steps 4 deposit transparent conductive film, formed by patterning processes and comprise the figure of pixel electrode, described pixel electrode is connected with drain electrode by described passivation layer via hole.
6. TFT-LCD array substrate manufacture method according to claim 5, is characterized in that, described step 2 comprises:
Using plasma strengthens chemical gaseous phase depositing process and deposits gate insulation layer film, semiconductor layer film and doped semiconductor layer film successively;
Adopt shadow tone or gray mask plate to be formed the figure including active layer and grid insulating layer through hole by patterning processes, described grid insulating layer through hole is positioned at the top of described grid line.
7. TFT-LCD array substrate manufacture method according to claim 6, is characterized in that, described employing shadow tone or gray mask plate form by patterning processes the figure including active layer and grid insulating layer through hole and comprise:
Described doped semiconductor layer film applies one deck photoresist;
Adopt shadow tone or the exposure of gray mask plate, make photoresist form photoresist and remove region, the complete reserve area of photoresist and photoresist half reserve area completely; The complete reserve area of photoresist corresponds to active layer pattern region, and photoresist is removed region completely and corresponded to grid insulating layer through hole figure region, and photoresist half reserve area corresponds to the region beyond above-mentioned figure; After development treatment, the photoresist thickness of the complete reserve area of photoresist does not change, and the photoresist that region removed completely by photoresist is completely removed, and the photoresist thickness of photoresist half reserve area reduces;
Etch away photoresist completely by first time etching technics and remove the doped semiconductor layer film in region, semiconductor layer film and gate insulation layer film completely, form grid insulating layer through hole figure;
Removed the photoresist of photoresist half reserve area by cineration technics, expose the doped semiconductor layer film in this region;
Etched away doped semiconductor layer film and the semiconductor layer film of photoresist half reserve area by second time etching technics completely, form active layer pattern;
Peel off remaining photoresist.
8. TFT-LCD array substrate manufacture method according to claim 5, it is characterized in that, described step 3 comprises: the method deposition source and drain metal layer thin film adopting magnetron sputtering or thermal evaporation, normal masks plate is adopted to carry out composition by patterning processes to source and drain metal layer thin film, form data line, source electrode, drain electrode, TFT channel region and storage electrode figure, wherein storage electrode is positioned at above the grid line of data line both sides, and is connected with grid line by grid insulating layer through hole.
9. TFT-LCD array substrate manufacture method according to claim 5, is characterized in that, described step 3 is also formed simultaneously blocks bar figure, described in block bar and be connected with storage electrode.
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| CN103915431B (en) * | 2013-06-17 | 2017-10-20 | 上海天马微电子有限公司 | A kind of tft array substrate, display device and array substrate manufacturing method |
| CN103824864A (en) * | 2014-02-12 | 2014-05-28 | 北京京东方显示技术有限公司 | Array substrate and preparation method thereof, and display apparatus |
| CN105093756B (en) * | 2015-08-31 | 2019-01-22 | 深圳市华星光电技术有限公司 | Liquid crystal display pixel structure and preparation method thereof |
| CN106206603A (en) * | 2016-07-19 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of array base palte, its manufacture method, display floater and display device |
| WO2018094595A1 (en) * | 2016-11-23 | 2018-05-31 | 深圳市柔宇科技有限公司 | Manufacturing method of array substrate |
| CN108493216B (en) * | 2018-03-21 | 2021-04-27 | 福建华佳彩有限公司 | TFT array substrate, display device and preparation method of TFT array substrate |
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| CN101017294A (en) * | 2006-02-06 | 2007-08-15 | 三星电子株式会社 | Liquid crystal display device |
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