CN102023424B - TFT-LCD array substrate and manufacture method thereof - Google Patents
TFT-LCD array substrate and manufacture method thereof Download PDFInfo
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- CN102023424B CN102023424B CN 200910092842 CN200910092842A CN102023424B CN 102023424 B CN102023424 B CN 102023424B CN 200910092842 CN200910092842 CN 200910092842 CN 200910092842 A CN200910092842 A CN 200910092842A CN 102023424 B CN102023424 B CN 102023424B
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Abstract
The invention relates to a TFT-LCD array substrate and a manufacture method thereof. The TFT-LCD array substrate includes gate lines and data lines, pixel electrodes and thin film transistors are formed in the pixel areas defined by the gate lines and data lines, the gate lines and data lines are positioned on the same layer, the pixel electrodes are formed on the insulating layer which is covering on the gate lines and data lines. Source electrode and drain electrode of the thin film transistor are positioned on the same layer where the gate lines are located; a doped semiconductor layer is formed on the source electrode and drain electrode, the semiconductor layer is formed on the doped semiconductor layer and covers channels between the source electrode and drain electrode, the gate electrode of the thin film transistor is formed on the insulating layer, the gate electrode is connected with the gate lines by a third through hole provided in the insulating layer. The invention is characterized in that only an insulating layer exists between the two plate electrodes of a storage capacitor, which allows the capacitance stored in unit area to be improved; simultaneously, the invention adopts the technical proposal which comprises firstly forming the channel and secondly forming the semiconductor layer, defects due to over etching or incomplete etching will not exist in TFT channel area, so that the yield rate is increased.
Description
Technical field
The present invention relates to a kind of Thin Film Transistor-LCD and manufacture method thereof, especially a kind of TFT-LCD array base palte and manufacture method thereof.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Displ ay is called for short TFT-LCD) has the characteristics such as volume is little, low in energy consumption, radiationless, has occupied leading position in current flat panel display market.
TFT-LCD mainly is made of array base palte and color membrane substrates to box, wherein is formed with thin film transistor (TFT) and pixel electrode that matrix form is arranged on the array base palte, and each pixel electrode is controlled by thin film transistor (TFT).When the thin film transistor (TFT) conducting, pixel electrode charges in ON time, and after charging finishes, pixel electrode voltage will be maintained to when scanning next time and again charge.In general, liquid crystal capacitance is little, only depends on liquid crystal capacitance can not keep the voltage of pixel electrode, and therefore existing design all arranges the voltage that a memory capacitance keeps pixel electrode.
At present prior art usually adopt grid line or with grid line with the public electrode wire of layer as battery lead plate of memory capacitance, and be folded with insulation course and passivation layer between the pixel electrode as another battery lead plate of memory capacitance.By the computing formula of memory capacitance as can be known, distance between the size of unit area memory capacitance and two battery lead plates is inversely proportional to, because sandwiched insulation course and passivation layer between memory capacitance two battery lead plates in the existing TFT-LCD array base palte, distance between two battery lead plates is larger, so the unit area memory capacitance is less.
In addition, in the prior art TFT-LCD array base palte, because the TFT channel region is to be completed by the composition technique that adopts shadow tone or gray mask plate, exists quarter or etching incomplete etc. bad, reduced to a certain extent yield rate.
Summary of the invention
The purpose of this invention is to provide a kind of TFT-LCD array base palte and manufacture method thereof, not only can Effective Raise unit area memory capacitance, and can overcome existing TFT channel region and had quarter or the incomplete defective of etching.
To achieve these goals, the invention provides a kind of TFT-LCD array base palte, comprise grid line and data line, be formed with pixel electrode and thin film transistor (TFT) in the pixel region that described grid line and data line limit, described grid line and data line arrange with layer, and described pixel electrode is formed on the insulation course that covers described grid line and data line; The source electrode of described thin film transistor (TFT) and drain electrode and grid line arrange with layer, doping semiconductor layer is formed on described source electrode and the drain electrode, semiconductor layer is formed on the described doping semiconductor layer and covers raceway groove between source electrode and the drain electrode, the gate electrode of described thin film transistor (TFT) is formed on the insulation course, and described gate electrode is connected with grid line by the 3rd via hole of offering on the insulation course.
Described grid line is horizontally disposed one-piece construction, and described data line is the intermittent configuration that vertically arranges, and between two adjacent grid lines, described data line connects into integral body by the data connecting line that forms on the second via hole of offering on the insulation course and the insulation course.Further, described pixel electrode, data connecting line and gate electrode arrange with layer, and are forming with in a composition technique.
Described data line is the one-piece construction that vertically arranges, and described grid line is horizontally disposed intermittent configuration, and between two adjacent data lines, described grid line connects into integral body by the grid connecting line that forms on the second via hole of offering on the insulation course and the insulation course.Further, the gate electrode of described pixel electrode, grid connecting line and thin film transistor (TFT) arranges with layer, and is forming with in a composition technique.
On the technique scheme basis, described pixel electrode is set up on described grid line.
On the technique scheme basis, also comprise the public electrode wire that arranges with layer with grid line, described public electrode wire is horizontally disposed intermittent configuration, between two adjacent data lines, described public electrode wire connects into integral body by the bus that forms on the 4th via hole offered on the insulation course and the insulation course.Further, the gate electrode of described pixel electrode, bus and thin film transistor (TFT) arranges with layer, and is forming with in a composition technique.
On the technique scheme basis, also comprise barrier bed, described barrier bed is positioned at the below of the TFT channel region of thin film transistor (TFT).
To achieve these goals, the present invention also provides a kind of TFT-LCD manufacturing method of array base plate,
Comprise:
Form the figure that comprises grid line, data line, source electrode, drain electrode and doping semiconductor layer at substrate by composition technique, described grid line is horizontally disposed one-piece construction, described data line is the intermittent configuration that vertically arranges, or described grid line is horizontally disposed intermittent configuration, and described data line is the one-piece construction that vertically arranges;
Form the figure that comprises semiconductor layer by composition technique;
Form the insulation course that comprises the first via hole, the second via hole and the 3rd via hole by composition technique, described the first via hole is positioned at the top of described drain electrode, described the second via hole is positioned at two ends of grid line or the data line of intermittent configuration, and described the 3rd via hole is positioned at the top of described grid line;
Form the figure that comprises pixel electrode, connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described gate electrode is connected with grid line by the 3rd via hole, and described connecting line makes the grid line of intermittent configuration or data line connect into integral body by the second via hole.
Described formation at substrate by composition technique comprises that the figure of grid line, data line, source electrode, drain electrode and doping semiconductor layer comprises:
Depositing metal films;
The dopant deposition semiconductive thin film;
Apply one deck photoresist at doped semiconductor films;
Adopt shadow tone or gray mask plate that photoresist is exposed, make photoresist form the complete reserve area of photoresist after the development, photoresist is removed zone and photoresist part reserve area fully, the complete reserve area of described photoresist and photoresist part reserve area are corresponding to grid line, data line, source electrode and drain electrode figure region, described photoresist is removed the zone fully corresponding to grid line, data line, zone beyond source electrode and the drain electrode figure, described photoresist part reserve area is corresponding to the zone beyond the doped semiconductor layer pattern on source electrode and the drain electrode;
By the first time etching technics etch away fully photoresist remove fully the zone doped semiconductor films and metallic film, formation comprises the figure of grid line, data line, source electrode and drain electrode, described grid line is horizontally disposed one-piece construction, described data line is the intermittent configuration that vertically arranges, or described grid line is horizontally disposed intermittent configuration, and described data line is the one-piece construction that vertically arranges;
Photoresist by cineration technics removal photoresist half reserve area exposes this regional doped semiconductor films;
By the second time etching technics etch away the doped semiconductor films of photoresist half reserve area fully, form the doped semiconductor layer pattern;
Peel off remaining photoresist.
Described formation by composition technique comprises that the figure of pixel electrode, connecting line and gate electrode comprises: form the figure that comprises pixel electrode, data connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described gate electrode is connected with grid line by the 3rd via hole, and described data connecting line makes the data line of intermittent configuration connect into integral body by the second via hole.
Described formation by composition technique comprises that the figure of pixel electrode, connecting line and gate electrode comprises: form the figure that comprises pixel electrode, grid connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described gate electrode is connected with grid line by the 3rd via hole, and described grid connecting line makes the grid line of intermittent configuration connect into integral body by the second via hole.
Described formation at substrate by composition technique comprises grid line, data line, the source electrode, also be formed with public electrode wire in the figure of drain electrode and doping semiconductor layer, described public electrode wire is horizontally disposed intermittent configuration, between two adjacent data lines, described formation by composition technique comprises the first via hole, also be formed with the 4th via hole in the insulation course of the second via hole and the 3rd via hole, described the 4th via hole lays respectively at two ends of described public electrode wire, described formation by composition technique comprises pixel electrode, also be formed with bus in the figure of connecting line and gate electrode, described bus makes the public electrode wire of intermittent configuration connect into integral body by described the 4th via hole.
On the technique scheme basis, also comprise the step that forms the barrier bed figure.
The invention provides a kind of TFT-LCD array base palte and manufacture method thereof, the figure that comprises grid line, data line, source electrode, drain electrode and doping semiconductor layer by the composition technique formation first time, the figure that comprises semiconductor layer by the composition technique formation second time, form the figure that comprises insulation course and via hole by composition technique for the third time, form the figure that comprises gate electrode, pixel electrode and connecting line by the 4th composition technique.Compare with the existing structure of sandwiched gate insulation layer and passivation layer between two battery lead plates, the present invention is by adopting data line and grid line with layer structure, distance between two battery lead plates of memory capacitance only has the thickness of insulation course, has therefore improved the unit area memory capacitance, has improved product quality.Simultaneously, existed four composition techniques of prior art of quarter or the incomplete defective of etching to compare with the TFT channel region, the present invention adopts and forms first the technical scheme that raceway groove forms semiconductor layer again, therefore the TFT channel region did not exist quarter or the incomplete defective of etching, guarantee product quality, improved yield rate.
Description of drawings
Fig. 1 is the planimetric map of TFT-LCD array base palte the first embodiment of the present invention;
Fig. 2 be among Fig. 1 A1-A1 to sectional view;
Fig. 3 be among Fig. 1 B1-B1 to sectional view;
Fig. 4 is the planimetric map after TFT-LCD array base palte the first embodiment composition technique first time of the present invention;
Fig. 5 be among Fig. 4 A2-A2 to sectional view;
Fig. 6 be among Fig. 4 B2-B2 to sectional view;
Fig. 7 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique behind each layer film of deposition A2-A2 to sectional view;
Fig. 8 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique behind the exposure imaging A2-A2 to sectional view;
Fig. 9 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique for the first time behind the etching technics A2-A2 to sectional view;
Figure 10 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique behind the cineration technics A2-A2 to sectional view;
Figure 11 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique for the second time behind the etching technics A2-A2 to sectional view;
Figure 12 is the planimetric map after TFT-LCD array base palte the first embodiment composition technique second time of the present invention;
Figure 13 be among Figure 12 A3-A3 to sectional view;
Figure 14 be among Figure 12 B3-B3 to sectional view;
Figure 15 is for the third time planimetric map after the composition technique of TFT-LCD array base palte the first embodiment of the present invention;
Figure 16 be among Figure 15 A4-A4 to sectional view;
Figure 17 be among Figure 15 B4-B4 to sectional view;
Figure 18 is the planimetric map of TFT-LCD array base palte the second embodiment of the present invention;
Figure 19 is the planimetric map of TFT-LCD array base palte the 3rd embodiment of the present invention;
Figure 20 is the planimetric map of TFT-LCD array base palte the 4th embodiment of the present invention;
Figure 21 be among Figure 20 C1-C1 to sectional view;
Figure 22 is the process flow diagram of TFT-LCD manufacturing method of array base plate of the present invention;
Figure 23 is the process flow diagram of TFT-LCD manufacturing method of array base plate the first embodiment of the present invention;
Figure 24 is the process flow diagram of TFT-LCD manufacturing method of array base plate the second embodiment of the present invention.
Description of reference numerals:
The 1-substrate; The 2-gate electrode; The 3-insulation course;
The 4-semiconductor layer; The 5-doping semiconductor layer; 6-source electrode;
The 7-drain electrode; The 9-barrier bed; The 11-grid line;
The 12-data line; The 13-pixel electrode; The 14-data connecting line;
The 15-public electrode wire; The 16-bus; 17-grid connecting line;
21-the first via hole; 22-the second via hole; 23-the 3rd via hole;
24-the 4th via hole; The 30-photoresist; The 31-metallic film;
The 32-doped semiconductor films.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is the planimetric map of TFT-LCD array base palte the first embodiment of the present invention, and what reflect is the structure of a pixel cell, Fig. 2 be among Fig. 1 A1-A1 to sectional view, Fig. 3 be among Fig. 1 B1-B1 to sectional view.Such as Fig. 1～shown in Figure 3, the agent structure of present embodiment TFT-LCD array base palte comprises grid line 11, data line 12, pixel electrode 13 and thin film transistor (TFT), orthogonal grid line 11 and data line 12 have defined pixel region, thin film transistor (TFT) and pixel electrode 13 are formed in the pixel region, grid line 11 is used for providing unlatching or cut-off signals to thin film transistor (TFT), data line 12 is used for providing data-signal to pixel electrode 13, and grid line 11 and data line 12 arrange with layer, make between the pixel electrode 13 that consists of memory capacitance and the grid line 11 and only be folded with insulation course, Effective Raise the unit area memory capacitance.Particularly, present embodiment TFT-LCD array base palte comprises grid line 11, data line 12, source electrode 6 and the drain electrode 7 that is formed on the substrate 1, grid line 11 is horizontally disposed one-piece construction, data line 12 is the intermittent configuration that vertically arranges, data line 12 is between two adjacent grid lines 11, one end of source electrode 6 is connected with data line 12, and the other end and drain electrode 7 are oppositely arranged, and makes between source electrode 6 and the drain electrode 7 and forms raceway groove; Be formed with doping semiconductor layer 5 on source electrode 6 and the drain electrode 7; Semiconductor layer 4 be formed on the doping semiconductor layer 5 and cover source electrode 6 and drain electrode 7 between raceway groove; Insulation course 3 is formed on the above-mentioned composition and covers whole substrate 1, offer the first via hole 21, the second via hole 22 and the 3rd via hole 23 on the insulation course 3, be formed with gate electrode 2, pixel electrode 13 and data connecting line 14 on the insulation course 3, pixel electrode 13 is connected with drain electrode 7 by the first via hole 21, data connecting line 14 makes the data line 12 of intermittent configuration connect into integral body by the second via hole 22, and gate electrode 2 is connected with grid line 11 by the 3rd via hole 23.Partial pixel electrode 13 is set up on part grid line 11, makes pixel electrode 13 and the overlapping region of grid line 11 consist of memory capacitance, only has insulation course 3 between pixel electrode 13 and the grid line 11.
Fig. 4～Figure 17 is the synoptic diagram of TFT-LCD array base palte the first embodiment manufacture process of the present invention, can further specify technical scheme of the present invention, in the following description, the alleged composition technique of the present invention comprises the techniques such as photoresist coating, mask, exposure, etching, and photoresist is take positive photoresist as example.
Fig. 4 is for the first time planimetric map after the composition technique of TFT-LCD array base palte the first embodiment of the present invention, and what reflect is the structure of a pixel cell, Fig. 5 be among Fig. 4 A2-A2 to sectional view, Fig. 6 be among Fig. 4 B2-B2 to sectional view.At first at substrate 1 deposition layer of metal film, then deposit one deck doped semiconductor films, adopt shadow tone or gray mask plate to form the figure that comprises grid line 11, data line 12, source electrode 6 and drain electrode 7 and doping semiconductor layer 5 by composition technique, such as Fig. 4～shown in Figure 6.The present invention for the first time composition technique is a kind of composition technique that adopts the multistep lithographic method, and detailed process is described as follows.
Fig. 7 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique behind each layer film of deposition A2-A2 to sectional view.At first adopt the method for magnetron sputtering or thermal evaporation, in substrate 1 (such as glass substrate or quartz base plate) deposition a layer thickness be
Metallic film 31, then using plasma strengthens chemical vapor deposition (being called for short PECVD) method, deposition one deck doped semiconductor films 32, as shown in Figure 7.Metallic film 31 can adopt the metal or alloy such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper, also can adopt the multi-layer compound film that is made of above-mentioned single thin film.
Fig. 8 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique behind the exposure imaging A2-A2 to sectional view.At first apply one deck photoresist 30 at doped semiconductor films 32, then adopt shadow tone or gray mask plate that photoresist 30 is exposed, make photoresist 30 form unexposed area A (the complete reserve area of photoresist), complete exposure area B (photoresist is removed the zone fully) and partial exposure area C (photoresist part reserve area) after the development, as shown in Figure 8.Wherein the thickness of unexposed area A photoresist is the thickest, the thinner thickness of partial exposure area C photoresist, the photoresist of complete exposure area B is completely removed, unexposed area A and partial exposure area C are corresponding to grid line, data line, source electrode and drain electrode figure region, complete exposure area B is corresponding to the zone beyond grid line, data line, source electrode and the drain electrode figure, and partial exposure area C is corresponding to the zone beyond the doped semiconductor layer pattern on source electrode and the drain electrode.
Fig. 9 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique for the first time behind the etching technics A2-A2 to sectional view.By the first time etching technics etch away doped semiconductor films 32 and the metallic film 31 of complete exposure area B fully, form the figure that comprises grid line 11, data line 12, source electrode 6 and drain electrode 7, as shown in Figure 9.
Figure 10 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique behind the cineration technics A2-A2 to sectional view.By cineration technics, remove the photoresist of partial exposure area C, expose this regional doped semiconductor films 32, as shown in figure 10.Since cineration technics, corresponding the reducing of thickness of unexposed area A photoresist.
Figure 11 be TFT-LCD array base palte the first embodiment of the present invention for the first time in the composition technique for the second time behind the etching technics A2-A2 to sectional view.By the second time etching technics etch away the doped semiconductor films of partial exposure area C fully, form doping semiconductor layer 5 figures, as shown in figure 11.
Peel off at last remaining photoresist, finish for the first time composition technique of TFT-LCD array base palte the first embodiment of the present invention.After this composition technique, grid line 11 is horizontally disposed one-piece construction, data line 12 is the intermittent configuration that vertically arranges, data line 12 is between two adjacent grid lines 11, and source electrode 6 and drain electrode 7 are formed on the substrate 1, and an end of source electrode 6 is connected with data line 12, the other end and drain electrode 7 are oppositely arranged, form raceway groove between source electrode 6 and the drain electrode 7, doping semiconductor layer 5 is positioned on source electrode 6 and the drain electrode 7, such as Fig. 4～shown in Figure 6.
Figure 12 is for the second time planimetric map after the composition technique of TFT-LCD array base palte the first embodiment of the present invention, and what reflect is the structure of a pixel cell, Figure 13 be among Figure 12 A3-A3 to sectional view, Figure 14 be among Figure 12 B3-B3 to sectional view.On the substrate of finishing Fig. 4 composition, adopt PECVD method deposition layer of semiconductor film, adopt the normal masks plate to form the figure that comprises semiconductor layer 4 by composition technique, semiconductor layer 4 is positioned on the doping semiconductor layer 5, and the covering raceway groove, such as Figure 12～shown in Figure 14.
Figure 15 is for the third time planimetric map after the composition technique of TFT-LCD array base palte the first embodiment of the present invention, and what reflect is the structure of a pixel cell, Figure 16 be among Figure 15 A4-A4 to sectional view, Figure 17 be among Figure 15 B4-B4 to sectional view.On the substrate of finishing Figure 12 composition, adopt PECVD method deposition a layer thickness to be
Insulation course 3, insulation course 3 is selected oxide, silicon dioxide, nitride or oxynitrides.Adopt the normal masks plate to form the figure that comprises the first via hole 21, the second via hole 22 and the 3rd via hole 23 by composition technique, wherein, the first via hole 21 is positioned at the top of drain electrode, the second via hole 22 lays respectively at two ends of the data line 12 of intermittent configuration, the 3rd via hole 23 is positioned at the top of grid line 11, such as Figure 15～shown in Figure 17.In this composition technique, also be formed with simultaneously the grid line interface via hole in grid line interface zone (grid line PAD) and the figures such as data line interface via hole in data line interface zone (data line PAD).Above-mentioned technique by composition technique formation grid line interface via hole and data line interface via pattern has been widely used in repeating no more here in the present composition technique.
At last, finish on the substrate of above-mentioned composition, adopt the method for magnetron sputtering or thermal evaporation, deposit thickness is
Transparent conductive film, transparent conductive film can adopt the materials such as tin indium oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide, also can adopt other metal and metal oxide.Adopt the normal masks plate to form gate electrode 2 by composition technique, the figure of pixel electrode 13 and data connecting line 14, pixel electrode 13 is connected with drain electrode 7 by the first via hole 21, the second via hole 22 that data connecting line 14 is offered by data line 12 ends makes the data line 12 of grid line 11 both sides connect into integral body, gate electrode 2 is positioned at the top of raceway groove, be connected with grid line 11 by the 3rd via hole 23, pixel electrode 13 is set up on grid line 11, make pixel electrode 13 and grid line 11 consist of memory capacitance, form memory capacitance storage capacitor construction of (Cs on Gate) on grid line, such as Fig. 1～shown in Figure 3.
Present embodiment provides a kind of TFT-LCD array base palte, the figure that comprises grid line, data line, source electrode, drain electrode and doping semiconductor layer by the composition technique formation first time, the figure that comprises semiconductor layer by the composition technique formation second time, form the figure that comprises insulation course and via hole by composition technique for the third time, form the figure that comprises gate electrode, pixel electrode and data connecting line by the 4th composition technique.Present embodiment is by adopting data line and grid line with layer structure, consisted of two battery lead plates of memory capacitance by grid line and pixel electrode, compare with the existing structure of sandwiched gate insulation layer and passivation layer between two battery lead plates, distance between two battery lead plates of present embodiment memory capacitance only has the thickness of insulation course, therefore improve the unit area memory capacitance, improved product quality.Simultaneously, existed four composition techniques of prior art of quarter or the incomplete defective of etching to compare with the TFT channel region, present embodiment adopts and forms first the technical scheme that raceway groove forms semiconductor layer again, therefore the TFT channel region did not exist quarter or the incomplete defective of etching, guarantee product quality, improved yield rate.
Need to prove that preparation process and the formed structure of the TFT-LCD array base palte of above-mentioned explanation only are a kind of implementations, in the practical application, those skilled in the art can form close structure by changing technological process.For example, present embodiment for the first time composition technique can be divided into two composition techniques, namely form the figure that comprises grid line, data line, source electrode and drain electrode by the composition technique that once adopts the normal masks plate, adopt the composition technique of normal masks plate to form the figure that comprises doping semiconductor layer by another time.
Figure 18 is the planimetric map of TFT-LCD array base palte the second embodiment of the present invention.As shown in figure 18, present embodiment is the structure extension of aforementioned the first embodiment, on aforementioned the first embodiment technical scheme basis, present embodiment TFT-LCD array base palte also comprises the public electrode wire 15 that consists of memory capacitance with pixel electrode 13, form memory capacitance storage capacitor construction of (Cs on Common) on public electrode wire, public electrode wire 15 arranges with layer with grid line and is forming with in a composition technique, make between the pixel electrode 13 that consists of memory capacitance and the public electrode wire 15 and only be folded with insulation course, Effective Raise the unit area memory capacitance.Particularly, public electrode wire 15 is horizontally disposed intermittent configuration, between two adjacent data lines 12.Also offer the 4th via hole 24 on the insulation course 3 simultaneously, the 4th via hole 24 lays respectively at two ends of public electrode wire 15, also be formed with bus 16 on the insulation course 3, the 4th via hole 24 that bus 16 is offered by public electrode wire 15 ends makes the bus 16 of data line 12 both sides connect into integral body.The preparation process of present embodiment TFT-LCD array base palte is close with aforementioned the first embodiment, difference is, form simultaneously the public electrode wire of intermittent configuration in the composition technique in the first time, forming simultaneously the 4th via hole in the composition technique for the third time, form simultaneously bus in the 4th composition technique, bus makes the public electrode wire of intermittent configuration connect into integral body by the 4th via hole.
In the practical application, aforementioned the first embodiment and the second embodiment combination can also be formed the unitized construction of memory capacitance, unitized construction refers to a memory capacitance part on grid line, and another part is on public electrode wire.
Figure 19 is the planimetric map of TFT-LCD array base palte the 3rd embodiment of the present invention.As shown in figure 19, present embodiment is the malformation of aforementioned the first embodiment, present embodiment agent structure and aforementioned the first embodiment are basic identical, difference is, present embodiment grid line 11 is horizontally disposed intermittent configuration, data line 12 is the one-piece construction that vertically arranges, the grid line 11 of intermittent configuration is between two adjacent data lines 12, therefore the second via hole 22 of offering on the insulation course 3 lays respectively at two ends of the grid line 11 of intermittent configuration, correspondingly also be formed with grid connecting line 17 on the insulation course 3, the second via hole 22 that grid connecting line 17 is offered by grid line 11 ends makes the grid line 11 of data line 12 both sides connect into integral body.The present embodiment preparation flow can referring to the manufacture process of aforementioned the first embodiment, repeat no more.
Figure 20 is the planimetric map of TFT-LCD array base palte the 4th embodiment of the present invention, and what reflect is the structure of a pixel cell, Figure 21 be among Figure 20 C1-C1 to sectional view.Such as Figure 20 and shown in Figure 21, present embodiment is the structure extension of aforementioned the first embodiment, on aforementioned the first embodiment technical scheme basis, present embodiment TFT-LCD array base palte also comprises barrier bed 9 figures, barrier bed 9 is positioned at the below of TFT channel region, is used for avoiding light direct irradiation semiconductor layer.In the practical application, barrier bed 9 can adopt preferably metallic film of light-proofness, such as Metal Cr, also can adopt preferably nonmetal film of light-proofness, as adding the resin material of black particle.The preparation flow of present embodiment TFT-LCD array base palte comprises: at first form the barrier bed figure at substrate, and then formation grid line, data line, source electrode, drain electrode and doped semiconductor layer pattern, and the figures such as active layer, insulation course, gate electrode, pixel electrode and data connecting line, it is identical with aforementioned the first embodiment to form the later flow process of barrier bed figure, repeats no more.Forming the barrier bed figure at substrate then comprises film forming step and adopts the normal masks plate to form the step of barrier bed figure by composition technique, when barrier bed is metallic film, adopt magnetron sputtering or thermal evaporation method deposition, when barrier bed is nonmetal film, adopt the methods such as PECVD method deposition or spin coating to apply.Obviously, the barrier bed of present embodiment can also be applied among aforementioned the second embodiment and the 3rd embodiment.
Figure 22 is the process flow diagram of TFT-LCD manufacturing method of array base plate of the present invention, comprising:
In the technique scheme of the present invention, because the distance that data line and grid line with a layer structure, consist of between two battery lead plates of memory capacitance only has the thickness of insulation course, so has improved the unit area memory capacitance, improved product quality.Simultaneously, form first the technical scheme that raceway groove forms semiconductor layer again owing to adopt, so the TFT channel region do not exist quarter or the incomplete defective of etching, guaranteed product quality, improved yield rate.
Figure 23 is the process flow diagram of TFT-LCD manufacturing method of array base plate the first embodiment of the present invention, comprising:
The method of step 11, employing magnetron sputtering or thermal evaporation, depositing metal films on substrate;
The method of step 19, employing magnetron sputtering or thermal evaporation, the deposit transparent conductive film, adopt the normal masks plate to form the figure that comprises pixel electrode, connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described connecting line makes the grid line of intermittent configuration or data line connect into integral body by the second via hole, described gate electrode is connected with grid line by the 3rd via hole, and described pixel electrode is set up on grid line.
The present embodiment preparation process is introduced in earlier figures 4～technical scheme shown in Figure 17 in detail, repeats no more here.Wherein, the connecting line in the step 19 is data connecting line or grid connecting line.When connecting line is data connecting line, step 19 is specially: form the figure that comprises pixel electrode, data connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described gate electrode is connected with grid line by the 3rd via hole, and described data connecting line makes the data line of intermittent configuration connect into integral body by the second via hole.When connecting line is the grid connecting line, step 19 is specially: form the figure that comprises pixel electrode, grid connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described gate electrode is connected with grid line by the 3rd via hole, and described grid connecting line makes the grid line of intermittent configuration connect into integral body by the second via hole.The step 11 of present embodiment～step 16 is for adopting shadow tone or gray mask plate to form simultaneously grid line by a composition technique, data line, the source electrode, the technique of drain electrode and doped semiconductor layer pattern, in the practical application, this composition technique can be divided into two composition techniques, namely form by the composition technique that once adopts the normal masks plate and comprise grid line, data line, the figure of source electrode and drain electrode, adopt the composition technique of normal masks plate to form the figure that comprises doping semiconductor layer by another time, be specially: adopt the method depositing metal films of magnetron sputtering or thermal evaporation, comprise grid line by the composition technique formation of adopting the normal masks plate, data line, the figure of source electrode and drain electrode; Using plasma strengthens chemical gaseous phase depositing process dopant deposition semiconductive thin film, forms the figure that comprises doping semiconductor layer by the composition technique that adopts the normal masks plate.
Figure 24 is the process flow diagram of TFT-LCD manufacturing method of array base plate the second embodiment of the present invention, comprising:
The method of step 21, employing magnetron sputtering or thermal evaporation, depositing metal films on substrate;
The method of step 29, employing magnetron sputtering or thermal evaporation, the deposit transparent conductive film, adopt the normal masks plate to form the figure that comprises pixel electrode, connecting line, gate electrode and bus by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described connecting line makes the grid line of intermittent configuration or data line connect into integral body by the second via hole, described gate electrode is connected with grid line by the 3rd via hole, and described bus makes the public electrode wire of intermittent configuration connect into integral body by the 4th via hole.
The flow process of present embodiment and aforementioned the first embodiment is basic identical, and difference is that present embodiment also is formed with public electrode wire, public electrode wire and pixel electrode formation memory capacitance.
In technical scheme shown in Figure 22, TFT-LCD manufacturing method of array base plate of the present invention can also comprise the step that forms the barrier bed figure, and barrier bed is used for avoiding light direct irradiation semiconductor layer below the TFT channel region between source electrode and the drain electrode.Particularly, before step 1, at first form the barrier bed figure, then form the figure of step 1～step 4.Barrier bed can adopt preferably metallic film of light-proofness, such as Metal Cr, also can adopt preferably nonmetal film of light-proofness, as adding the resin material of black particle.Forming the barrier bed figure at substrate then comprises film forming step and adopts the normal masks plate to form the step of barrier bed figure by composition technique, when barrier bed is metallic film, adopt magnetron sputtering or thermal evaporation method deposition, when barrier bed is nonmetal film, adopt the methods such as PECVD method deposition or spin coating to apply.Obviously, the barrier bed of present embodiment can also be applied among aforementioned the first embodiment and the second embodiment.
It should be noted that at last: above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.
Claims (15)
1. TFT-LCD array base palte, comprise grid line and data line, be formed with pixel electrode and thin film transistor (TFT) in the pixel region that described grid line and data line limit, described grid line and data line arrange with layer, described pixel electrode is formed on the insulation course that covers described grid line and data line, it is characterized in that
The source electrode of described thin film transistor (TFT) and drain electrode and grid line arrange with layer, doping semiconductor layer is formed on described source electrode and the drain electrode, semiconductor layer is formed on the described doping semiconductor layer and covers raceway groove between source electrode and the drain electrode, the gate electrode of described thin film transistor (TFT) is formed on the insulation course, and described gate electrode is connected with grid line by the 3rd via hole of offering on the insulation course.
2. TFT-LCD array base palte according to claim 1, it is characterized in that, described grid line is horizontally disposed one-piece construction, described data line is the intermittent configuration that vertically arranges, between two adjacent grid lines, described data line connects into integral body by the data connecting line that forms on the second via hole of offering on the insulation course and the insulation course.
3. TFT-LCD array base palte according to claim 2 is characterized in that, described pixel electrode, data connecting line and gate electrode arrange with layer, and is forming with in a composition technique.
4. TFT-LCD array base palte according to claim 1, it is characterized in that, described data line is the one-piece construction that vertically arranges, described grid line is horizontally disposed intermittent configuration, between two adjacent data lines, described grid line connects into integral body by the grid connecting line that forms on the second via hole of offering on the insulation course and the insulation course.
5. TFT-LCD array base palte according to claim 4 is characterized in that, the gate electrode of described pixel electrode, grid connecting line and thin film transistor (TFT) arranges with layer, and is forming with in a composition technique.
6. the described TFT-LCD array base palte of arbitrary claim is characterized in that described pixel electrode is set up on described grid line according to claim 1～5.
7. the described TFT-LCD array base palte of arbitrary claim according to claim 1～5, it is characterized in that, also comprise the public electrode wire that arranges with layer with grid line, described public electrode wire is horizontally disposed intermittent configuration, between two adjacent data lines, described public electrode wire connects into integral body by the bus that forms on the 4th via hole offered on the insulation course and the insulation course.
8. TFT-LCD array base palte according to claim 7 is characterized in that, the gate electrode of described pixel electrode, bus and thin film transistor (TFT) arranges with layer, and is forming with in a composition technique.
9. the described TFT-LCD array base palte of arbitrary claim is characterized in that according to claim 1～5, also comprises barrier bed, and described barrier bed is positioned at the below of the TFT channel region of thin film transistor (TFT).
10. a TFT-LCD manufacturing method of array base plate is characterized in that, comprising:
Form the figure that comprises grid line, data line, source electrode, drain electrode and doping semiconductor layer at substrate by composition technique, described grid line is horizontally disposed one-piece construction, described data line is the intermittent configuration that vertically arranges, or described grid line is horizontally disposed intermittent configuration, and described data line is the one-piece construction that vertically arranges;
Form the figure that comprises semiconductor layer by composition technique;
Form the insulation course that comprises the first via hole, the second via hole and the 3rd via hole by composition technique, described the first via hole is positioned at the top of described drain electrode, described the second via hole is positioned at two ends of grid line or the data line of intermittent configuration, and described the 3rd via hole is positioned at the top of described grid line;
Form the figure that comprises pixel electrode, connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described gate electrode is connected with grid line by the 3rd via hole, and described connecting line makes the grid line of intermittent configuration or data line connect into integral body by the second via hole.
11. TFT-LCD manufacturing method of array base plate according to claim 10 is characterized in that, described formation at substrate by composition technique comprises that the figure of grid line, data line, source electrode, drain electrode and doping semiconductor layer comprises:
Depositing metal films;
The dopant deposition semiconductive thin film;
Apply one deck photoresist at doped semiconductor films;
Adopt shadow tone or gray mask plate that photoresist is exposed, make photoresist form the complete reserve area of photoresist after the development, photoresist is removed zone and photoresist part reserve area fully, the complete reserve area of described photoresist and photoresist part reserve area are corresponding to grid line, data line, source electrode and drain electrode figure region, described photoresist is removed the zone fully corresponding to grid line, data line, zone beyond source electrode and the drain electrode figure, described photoresist part reserve area is corresponding to the zone beyond the doped semiconductor layer pattern on source electrode and the drain electrode;
By the first time etching technics etch away fully photoresist remove fully the zone doped semiconductor films and metallic film, formation comprises the figure of grid line, data line, source electrode and drain electrode, described grid line is horizontally disposed one-piece construction, described data line is the intermittent configuration that vertically arranges, or described grid line is horizontally disposed intermittent configuration, and described data line is the one-piece construction that vertically arranges;
Photoresist by cineration technics removal photoresist half reserve area exposes this regional doped semiconductor films;
By the second time etching technics etch away the doped semiconductor films of photoresist half reserve area fully, form the doped semiconductor layer pattern;
Peel off remaining photoresist.
12. TFT-LCD manufacturing method of array base plate according to claim 10, it is characterized in that, described formation by composition technique comprises that the figure of pixel electrode, connecting line and gate electrode comprises: form the figure that comprises pixel electrode, data connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described gate electrode is connected with grid line by the 3rd via hole, and described data connecting line makes the data line of intermittent configuration connect into integral body by the second via hole.
13. TFT-LCD manufacturing method of array base plate according to claim 10, it is characterized in that, described formation by composition technique comprises that the figure of pixel electrode, connecting line and gate electrode comprises: form the figure that comprises pixel electrode, grid connecting line and gate electrode by composition technique, described pixel electrode is connected with drain electrode by the first via hole, described gate electrode is connected with grid line by the 3rd via hole, and described grid connecting line makes the grid line of intermittent configuration connect into integral body by the second via hole.
14. TFT-LCD manufacturing method of array base plate according to claim 10, it is characterized in that, described formation at substrate by composition technique comprises grid line, data line, the source electrode, also be formed with public electrode wire in the figure of drain electrode and doping semiconductor layer, described public electrode wire is horizontally disposed intermittent configuration, between two adjacent data lines, described formation by composition technique comprises the first via hole, also be formed with the 4th via hole in the insulation course of the second via hole and the 3rd via hole, described the 4th via hole lays respectively at two ends of described public electrode wire, described formation by composition technique comprises pixel electrode, also be formed with bus in the figure of connecting line and gate electrode, described bus makes the public electrode wire of intermittent configuration connect into integral body by described the 4th via hole.
15. the described TFT-LCD manufacturing method of array base plate of arbitrary claim is characterized in that according to claim 10～14, also comprises the step that forms the barrier bed figure.
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| CN103915443B (en) * | 2013-04-02 | 2018-04-27 | 上海天马微电子有限公司 | A kind of array base palte and preparation method thereof, liquid crystal display device |
| CN103941499B (en) * | 2013-11-19 | 2016-12-07 | 上海天马微电子有限公司 | A kind of array base palte and display floater, display device |
| CN103676385B (en) | 2013-12-27 | 2016-08-17 | 深圳市华星光电技术有限公司 | Dot structure |
| CN103941509A (en) * | 2014-04-16 | 2014-07-23 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal panel |
| CN104218092B (en) * | 2014-08-13 | 2017-08-25 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device |
| CN104217994B (en) * | 2014-08-29 | 2017-10-03 | 京东方科技集团股份有限公司 | A kind of thin-film transistor array base-plate and preparation method thereof, display device |
| CN108511457B (en) * | 2017-02-28 | 2020-09-01 | 昆山国显光电有限公司 | TFT pixel structure, array substrate, manufacturing method of array substrate and display device |
| CN107910351B (en) * | 2017-11-14 | 2020-06-05 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT substrate |
| CN113741102A (en) * | 2020-05-28 | 2021-12-03 | 合肥鑫晟光电科技有限公司 | Array substrate, display panel and preparation method |
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