CN103915443B - A kind of array base palte and preparation method thereof, liquid crystal display device - Google Patents
A kind of array base palte and preparation method thereof, liquid crystal display device Download PDFInfo
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- CN103915443B CN103915443B CN201310113604.2A CN201310113604A CN103915443B CN 103915443 B CN103915443 B CN 103915443B CN 201310113604 A CN201310113604 A CN 201310113604A CN 103915443 B CN103915443 B CN 103915443B
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Abstract
The embodiment of the present invention provides a kind of array base palte and preparation method thereof; data cable on array base palte is manufactured with gate line with layer; some independent data line segments are arranged to as space segmentation using the gate line continuously set; gate insulation layer and etch-protecting layer are covered on the data line; the etch-protecting layer of covering on the data line is used with the etch-protecting layer being formed on thin film transistor active layer and manufactured with layer, does not increase extra processing step.Moreover, the thickness of etch-protecting layer is very thick, so that the distance between data cable and public electrode increase, reduce the parasitic capacitance between data cable and public electrode.Simultaneously as covered with etch-protecting layer on data cable, and etch-protecting layer can use organic film material, therefore the dielectric constant between data cable and public electrode is also reduced, so as to further reduce the parasitic capacitance between data cable and public electrode.
Description
Technical field
The present invention relates to technical field of flat panel display, more particularly to a kind of array base palte and preparation method thereof, liquid crystal display
Device.
Background technology
At present, in the sull field-effect transistor of array base palte（Thin Film Transistor, TFT）Design
In, it is to utilize organic film to have a kind of design method（Organic Film）As island etch-protecting layer（Etch-stop
Layer, ESL layers）, to realize low temperature process.
Structure diagram by the use of organic film as the array base palte of ESL layers of island can be with as shown in Figure 1, Fig. 1 be shown
The structure of a pixel unit in array base palte, in array base palte as shown in Figure 1, cross-sectional view such as Fig. 2 of AA ' positions
It is shown.
In array base palte as depicted in figs. 1 and 2, including thin film transistor (TFT), data cable 01 and gate line 02.It is described thin
Film transistor is included in the grid 05 formed on transparent substrate 00（Since the grid 05 and the gate line 02 are manufactured with layer,
Therefore, the gate line 02 and the grid 05 are represented using identical pattern）, the covering gate insulation layer 08 of grid 05, position
Active layer 07 on gate insulation layer 08, the etch-protecting layer 06 on active layer 07, and the source electrode being separated
04 and drain electrode 03（Source electrode 04 and drain electrode 03 are same material, and are located at same layer, therefore, are represented using identical pattern）.
Meanwhile array base palte still further comprises pixel electrode 09 and passivation layer 10.Since pixel electrode 09 is transparent electricity
Pole, so in Fig. 1, it is visible in pixel electrode 09 and the lap of drain electrode 03, drain electrode 03.Passivation layer 10 is to be located at pixel electrode
One layer on 09, since passivation layer 10 is transparent, and passivation layer 10 covers most areas on the transparent substrate 00
Domain, therefore, passivation layer 10 is not shown in Fig. 1.In fig. 2, passivation layer 10 can be understood as covering transparent substrate 00 and dotted line
Surround the white space in part.
On passivation layer 10, array base palte can also include public（common）Electrode 11.Specifically, in fig. 2, it is blunt
Change that layer 10 can be understood as covering transparent substrate 00, public electrode 11 and dotted line surround white space in part.Public electrode
11 transparencies are preferable, and public electrode 11 can be understood as covering whole pixel electrode 09, but not where cover film transistor
Region.It is in Fig. 1, public in order to clearly illustrate that the position of source electrode 04, and the position relationship of drain electrode 03 and pixel electrode 09
Common electrode 11 is it is to be understood that covering dotted line is surrounded in part, except other regions of thin film transistor (TFT) region.
In the array base palte shown in Fig. 1 and Fig. 2, data cable 01 and source electrode 04, drain electrode 03 are in same layer, on the one hand, are
Reduce the parasitic capacitance that data cable 01, gate line 02 produce between pixel electrode 09 respectively, generally can by pixel electrode 09 with
Data cable 01, gate line 02 are spaced a distance, and this reduces the aperture opening ratio of liquid crystal display panel；On the other hand, due to
Data cable 01 and 11 part of public electrode overlap, therefore, the parasitism produced between data cable 01, gate line 02 and public electrode 11
Capacitance is larger.On the make, large scale and high screen resolution（Pixels Per inch, PPI）Array base palte when, face
Plate loads（Panel Loading）And signal delay（Delay）All bigger, the performance of array base palte is difficult to be guaranteed.
The content of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, liquid crystal display device, for reducing array base
Parasitic capacitance in plate.
A kind of array base palte, the array base palte includes thin film transistor (TFT) and transverse and longitudinal intersection encloses and sets to form multiple pixels
The data cable and gate line of unit, the gate line and the data line bit are in same layer, and the data cable is continuously to set
The gate line be arranged to some independent data line segments for space segmentation；Gate insulation layer is formed in the data cable and gate line
On；Thin film transistor (TFT), including source electrode and drain electrode, the source electrode is by penetrating the logical of the gate insulation layer above the data cable
Hole, the adjacent independent data line segment is electrically connected.
A kind of liquid crystal display device, including：Above-mentioned array base palte, the color film base being oppositely arranged with the array base palte
Plate, the liquid crystal layer being arranged between the array base palte and the color membrane substrates.
A kind of preparation method of array base palte, the described method includes：On the transparent substrate, the first metal layer is deposited, at this
Make gate line and data cable on the first metal layer by lithography, and the data cable is using the gate line continuously set as space segmentation
It is arranged to some independent data line segments；On the gate line and data cable, deposition forms gate insulation layer, and the gate insulation layer covers
Cover the gate line and the data cable；Side etches through hole on the data line；On the gate insulation layer, deposition second
Metal layer, pattern is made by lithography in the second metal layer, forms the source electrode being separated and drain electrode, and the source electrode pass through it is described
Through hole above data cable, the adjacent independent data line segment is electrically connected.
The scheme provided according to embodiments of the present invention, the data cable on array base palte is used to be manufactured with gate line with layer, with
The gate line continuously set is arranged to some independent data line segments for space segmentation, covers gate insulation layer and etching on the data line
Protective layer, so that the distance between data cable and public electrode increase, reduces the parasitism between data cable and public electrode
Capacitance.
In addition, etch-protecting layer penetrates the gate insulation layer and institute with thin film transistor (TFT) source electrode by data cable top
The through hole of the first etch-protecting layer is stated, the adjacent independent data line segment is electrically connected, does not increase other techniques
Step, processing procedure are simple.
Brief description of the drawings
Fig. 1 is the structure diagram for the array base palte that the prior art provides；
Fig. 2 is the cross-sectional view of AA ' positions in Fig. 1 that the prior art provides；
Fig. 3 is the structure diagram for the array base palte that the embodiment of the present invention one provides；
Fig. 4 is the cross-sectional view of AA ' positions in Fig. 3 that the embodiment of the present invention one provides；
Fig. 5 is the step flow chart of preparation method provided by Embodiment 2 of the present invention.
Embodiment
The preferred embodiment of the present invention is illustrated below in conjunction with Figure of description, it will be appreciated that described herein
Preferred embodiment is merely to illustrate and explain the present invention, and is not intended to limit the present invention.And in the case where there is no conflict, this Shen
Please in embodiment and embodiment in feature can be mutually combined.
Embodiment one,
The embodiment of the present invention one provides a kind of array base palte, and the structure of the array base palte can be with as shown in figure 3, and such as Fig. 3
The cross-sectional view of AA ' positions can be with as shown in figure 4, with reference to Fig. 3 and Fig. 4 to of the invention real in shown array base palte
The array base palte for applying the offer of example one illustrates, and the array base palte includes thin film transistor (TFT) and transverse and longitudinal intersection encloses and sets to be formed
The data cable 01 and gate line 02 of multiple pixel units, wherein：
The gate line 02 and the data cable 01 are located at same layer, in Fig. 4, due to the gate line 02 and the number
Manufactured according to line 01 with layer, therefore, the gate line 02 and the data cable 01, and the data are represented using identical pattern
Line 01 is arranged to some independent data line segments with the gate line 02 continuously set for space segmentation；
The thin film transistor (TFT), including the grid 05 being formed on transparent substrate 00（Due to the grid 05 and the grid
Polar curve 02 is manufactured with layer, therefore, the gate line 02 and the grid 05 is represented using identical pattern）, gate insulation layer 08,
Active layer 07, etch-protecting layer 06, source electrode 04 and drain electrode 03, the etch-protecting layer 06 includes the first etch-protecting layer and second
Etch-protecting layer, wherein：
The grid 05 is electrically connected with the gate line 02；
The gate insulation layer 08 covers the grid 05 and the data cable 01；
The active layer 07, is formed on the gate insulation layer 08, and is overlapped with 05 region of grid；
First etch-protecting layer, is formed on the data cable 01, wherein the width of first etch-protecting layer
More than the width of data cable 01, in figure 3, in order to clearly show that the position of the data cable 01 and first etch-protecting layer
Relation, in the data cable 01 and the first etch-protecting layer overlapping part, shows the data cable 01；
Second etch-protecting layer, is formed in the source-drain electrode region；
The source electrode 04 and the drain electrode 03, are separated and are formed in second etch-protecting layer, active layer 07 and grid
On insulating layer 08, and the source electrode 04 is protected by penetrating the gate insulation layer 08 and first etching above the data cable
The through hole of layer, the adjacent independent data line segment is electrically connected.
Further, pixel electrode 09, the drain electrode 03 and the pixel electrode 09 are additionally provided with above the drain electrode
It is electrically connected.Since 09 transparency of pixel electrode is preferable, in figure 3, in pixel electrode 09 and the lap of drain electrode 03, drain electrode 03
It can be seen that.
Preferably, as shown in figure 3, in the present embodiment, the pixel electrode 09 can with 01 region of data cable
To partly overlap.So as to expand the area of pixel electrode 09, increase effective vent rate.
Further, the array base palte further includes the covering pixel electrode 09, the thin film transistor (TFT), the data
The passivation layer 10 of line 01 and the gate line 02.Since passivation layer 10 is transparent, and passivation layer 10 covers the transparent substrate
Most areas on 00, therefore, in figure 3, passivation layer 10 is not shown.In Fig. 4, passivation layer 10 can be understood as covering
Transparent substrate 00 surrounds the white space in part with dotted line.
Further, the array base palte further includes the public electrode 11 being formed on the pixel electrode 09.Specifically,
In Fig. 4, passivation layer 10 can be understood as covering transparent substrate 00, public electrode 11 and dotted line surround clear area in part
Domain.The public electrode 11 is overlapped with the 01 region part of data cable, and with the 02 region part of gate line
It is overlapping.11 transparency of public electrode is preferable, and public electrode 11 can be understood as covering whole pixel electrode 09, but does not cover thin
Film transistor region.In order to clearly illustrate that the position of source electrode 04, and the position of drain electrode 03 and pixel electrode 09 are closed
System, in figure 3, public electrode 11 is it is to be understood that covering dotted line is surrounded in part, except other of thin film transistor (TFT) region
Region.
Preferably, second etch-protecting layer is located at same layer with first etch-protecting layer.I.e. described second quarter
Erosion protective layer can be manufactured with first etch-protecting layer with layer, so as to reduce the preparation process of array person's substrate, simplify system
Standby technique, saves manufacturing cost.
Preferably, second etch-protecting layer also covers the gate line 02, in figure 3, described in order to clearly show that
The position relationship of gate line 02 and second etch-protecting layer, overlaps in the gate line 02 and second etch-protecting layer
Part, shows the gate line 02.So that array base palte provided in this embodiment is except that can reduce data cable and common electrical
Outside parasitic capacitance between pole, the parasitic capacitance between data cable and gate line, gate line and public electrode can also be reduced,
So as to further reduce the parasitic capacitance of array base palte.
Preferably, in the present embodiment, the active layer is oxide semiconductor material, such as indium gallium zinc oxide.
In the present embodiment, etch-protecting layer can be the organic film that organic material is formed, and can have relatively low Jie
Electric constant, can be generally 2 or 3, be under normal conditions the dielectric constant less than 4, such as：Etch-protecting layer material is sub- for polyamides
Amine（polymide）Deng so as to further reduce parasitic capacitance.Meanwhile the thickness of the etch-protecting layer can be more than 2 μm
（Including 2 μm）, for example, being 2~3 μm of thickness.But on the dielectric constant and thickness of etch-protecting layer, the present invention is not
This is only limitted to, specific dielectric constant can make choice in the range of above-mentioned provide according to demand with thickness.
Preferably, relative to the prior art, the present embodiment can provide the etch-protecting layer of thickness increase.It is for example, described
The thickness of first etch-protecting layer and the second etch-protecting layer can be 0.5 micron~3 microns.Specifically, coating can be passed through
Technique realizes the increase of etch-protecting layer thickness.In the present embodiment, can be with due to providing the etch-protecting layer of thickness increase
So that the distance between data cable and public electrode increase, further reduce the parasitic capacitance between data cable and public electrode.
Simultaneously as etch-protecting layer thickness increases, relative to the prior art, array base palte provided in an embodiment of the present invention can also have
Effect reduces the parasitic capacitance between gate line and public electrode, and can further reduce the parasitism between data cable and gate line
Capacitance.
Using the array base palte of above structure, the data cable on array base palte is manufactured with gate line with layer, continuously to set
Gate line be arranged to some independent data line segments for space segmentation, cover gate insulation layer and etch-protecting layer on the data line,
The etch-protecting layer of covering on the data line is used with the etch-protecting layer being formed on thin film transistor active layer and manufactured with layer,
Extra processing step is not increased.Moreover, the thickness of etch-protecting layer is very thick, so that between data cable and public electrode
Distance increases, and reduces the parasitic capacitance between data cable and public electrode.Simultaneously as protected on data cable covered with etching
Layer, and etch-protecting layer can use organic film material, therefore the dielectric constant between data cable and public electrode is also reduced,
So as to further reduce the parasitic capacitance between data cable and public electrode.In addition, source electrode passes through above the data cable
The through hole of the gate insulation layer and first etch-protecting layer is penetrated, the adjacent independent data line segment is connected electrically in one
Rise, do not increase other processing steps, processing procedure is simple.
Further, the embodiment of the present invention two provides a kind of preparation method of array base palte.
Embodiment two,
The embodiment of the present invention two provides a kind of preparation method of array base palte, is used for realization the offer of the embodiment of the present invention one
The preparation of array base palte, the step flow of the preparation method can with as shown in figure 5, including：
Step 101, form grid, gate line and data cable.
In this step, it can deposit the first metal layer on the transparent substrate, grid made by lithography on the first metal layer
Pole, gate line and data cable, and the data cable is arranged to some independences using the gate line continuously set as space segmentation
Data line segment.
Step 102, form gate insulation layer.
In this step, it can deposit on the grid, gate line and data cable and form gate insulation layer, the grid are exhausted
Edge layer covers grid, gate line and the data cable.The gate insulation layer can be inorganic material, such as silica, nitridation
Silicon etc., or organic material.
Step 103, form active layer.
In this step, can be on the gate insulation layer, deposited semiconductor layer, figure is made by lithography on the semiconductor layer
Case, forms active layer, and the active layer is overlapped with the grid region.
Preferably, the semiconductor layer uses oxide semiconductor material.Such as, indium gallium zinc oxide.
Step 104, form etch-protecting layer.
In this step, it can coat etch-protecting layer on the active layer and the gate insulation layer, which protected
Sheath patterns, and forms the first etch-protecting layer and the second etch-protecting layer, wherein, described in the first etch-protecting layer covering
Data cable region, second etch-protecting layer are formed in the source-drain electrode region.Wherein described first etching is protected
The width of sheath is more than the width of data cable, and the width of second etch-protecting layer is more than the width of gate line.
The etch-protecting layer is the organic film that organic material is formed, and has relatively low dielectric constant, generally can be with
It is under normal conditions the dielectric constant less than 4 for 2 or 3, such as：Polyimides（polymide）.Meanwhile the etch-protecting layer
Thickness can be more than 2 μm（Including 2 μm）, for example, being 2~3 μm of thickness.But on the dielectric constant of etch-protecting layer
And thickness, the present invention is not limited to this, and specific dielectric constant can be according to demand in above-mentioned provided scope with thickness
Inside make choice.
Step 105, etching through hole.
In this step, through hole can be just etched on the data line.
Step 106, form source electrode and drain electrode.
In this step, the can be deposited on second etch-protecting layer, the active layer and the gate insulation layer
Two metal layers, pattern is made by lithography in the second metal layer, forms the source electrode being separated and drain electrode, and the source electrode passes through institute
The through hole above data cable is stated, the adjacent independent data line segment is electrically connected.
Further, the present embodiment can also comprise the following steps：
Step 107, form pixel electrode.
In this step, transparency conducting layer can be deposited, in the electrically conducting transparent in the drain electrode and the gate insulation layer
Make pattern on layer by lithography, form pixel electrode, wherein, the pixel electrode partly overlaps with the data cable region.
Step 108, form passivation layer.
In this step, can be on the pixel electrode, deposit passivation layer, the passivation layer covers the transparent base
Plate.The passivation layer can use silica or silicon nitride.
Step 109, form public electrode.
In this step, transparent conductive material, the photoetching on the transparent conductive material can be deposited on the passivation layer
Go out pattern, form public electrode, the common electrode layer covers the pixel electrode；And the public electrode and the data cable
Region part overlaps, and is overlapped with gate line region part.The transparent conductive material can be indium oxide
Tin.
The array base palte that above-mentioned manufacture method is formed, data cable is manufactured with gate line with layer, with the gate line continuously set
It is arranged to some independent data line segments for space segmentation, covers gate insulation layer and etch-protecting layer on the data line, be covered in number
Use according to the etch-protecting layer on line and the etch-protecting layer being formed on thin film transistor active layer and manufactured with layer, do not increase volume
Outer processing step.Moreover, the thickness of etch-protecting layer is very thick, so that the distance between data cable and public electrode add
Greatly, the parasitic capacitance between data cable and public electrode is reduced.Simultaneously as covered with etch-protecting layer on data cable, and carve
Erosion protective layer can use organic film material, therefore also reduce the dielectric constant between data cable and public electrode, so as to
Further to reduce the parasitic capacitance between data cable and public electrode.In addition, source electrode above the data cable by penetrating institute
The through hole of gate insulation layer and first etch-protecting layer is stated, the adjacent independent data line segment is electrically connected, no
The other processing steps of increase, processing procedure are simple.
Above example is to better illustrate technical solution of the present invention, it is known by a person skilled in the art that the present invention also wraps
Include the substantially equivalent or equivalent scheme of technical solution described in above example, not should using specific situation described in embodiment as pair
The limitation of the claims in the present invention.In addition, although have been described for the preferred embodiment of the application, but those skilled in the art
Once knowing basic creative concept, then other change and modification can be made to these embodiments.So appended right will
Ask and be intended to be construed to include preferred embodiment and fall into all change and modification of the application scope.
Obviously, those skilled in the art can carry out the application essence of the various modification and variations without departing from the application
God and scope.In this way, if these modifications and variations of the application belong to the scope of the application claim and its equivalent technologies
Within, then the application is also intended to comprising including these modification and variations.
Claims (20)
1. a kind of array base palte, the array base palte includes thin film transistor (TFT) and encloses the data for setting and forming multiple pixel units
Line and gate line, it is characterised in that
The gate line and the data line bit are in same layer, and the data cable is using the gate line continuously set as interval
Subsection setup is into some independent data line segments；
Gate insulation layer is formed on the data cable and gate line；
Thin film transistor (TFT), including source electrode and drain electrode, the source electrode is by penetrating the logical of the gate insulation layer above the data cable
Hole, is electrically connected with the adjacent independent data line segment；Pixel electrode, the drain electrode are also provided directly with above the drain electrode
It is electrically connected with the pixel electrode；The pixel electrode partly overlaps with the data cable region；
The thin film transistor (TFT) further includes the first etch-protecting layer being formed on the gate insulator, and first etching is protected
Sheath covers on the data line, and the width of first etch-protecting layer is more than the width of the data cable；Described first
Etch-protecting layer material is organic film.
2. array base palte as claimed in claim 1, it is characterised in that the thin film transistor (TFT), which further includes, is formed at the grid
The second etch-protecting layer on insulating layer, second etch-protecting layer are formed in the source-drain electrode region.
3. array base palte as claimed in claim 1, it is characterised in that the thin film transistor (TFT), which further includes, is formed at transparent substrate
On grid and active layer, wherein, the grid is electrically connected with the gate line, the active layer and the grid region
Overlap mutually.
4. array base palte as claimed in claim 3, it is characterised in that the array base palte further includes the covering pixel electricity
Pole, the thin film transistor (TFT), the passivation layer of the data cable and the gate line.
5. array base palte as claimed in claim 4, it is characterised in that the array base palte, which further includes, is formed in the pixel electricity
Public electrode on extremely；The public electrode is overlapped with data cable region part, and with the gate line location
Domain part overlaps.
6. array base palte as claimed in claim 2, it is characterised in that second etch-protecting layer is protected with the described first etching
Sheath is located at same layer.
7. array base palte as claimed in claim 2, it is characterised in that second etch-protecting layer also covers the grid
Line.
8. array base palte as claimed in claim 3, it is characterised in that the active layer is oxide semiconductor material.
9. array base palte as claimed in claim 2, it is characterised in that the second etch-protecting layer material is organic film.
10. array base palte as claimed in claim 2, it is characterised in that the thickness of second etch-protecting layer is 0.5 micron
~3 microns.
11. the array base palte as described in claim 1~10 is any, it is characterised in that the thickness of first etch-protecting layer
For 0.5 micron~3 microns.
A kind of 12. liquid crystal display device, it is characterised in that including：Array base palte as described in claim 1~11 is any, with
The color membrane substrates that the array base palte is oppositely arranged, the liquid crystal layer being arranged between the array base palte and the color membrane substrates.
A kind of 13. preparation method of array base palte, it is characterised in that the described method includes：
On the transparent substrate, the first metal layer is deposited, makes gate line and data cable, and the number by lithography on the first metal layer
Some independent data line segments are arranged to as space segmentation using the gate line continuously set according to line；
On the gate line and data cable, deposition forms gate insulation layer, and the gate insulation layer covers the gate line and described
Data cable；
Side etches through hole on the data line；
On the gate insulation layer, depositing second metal layer, makes pattern by lithography in the second metal layer, forms what is be separated
Source electrode and drain electrode, and the source electrode is electrically connected by the through hole above the data cable with the adjacent independent data line segment；
Also include after the source electrode being separated and drain electrode is formed in the drain electrode and the gate insulation layer, Direct precipitation is saturating
Bright conductive layer, makes pattern by lithography on the transparency conducting layer, forms pixel electrode, wherein, the pixel electrode and the data
Line region partly overlaps；
Formed after the gate insulator, in addition on the gate insulation layer, coat etch-protecting layer, which is protected
Pattern layers, the first etch-protecting layer of formation, the first etch-protecting layer covering data cable region, described first
The width of etch-protecting layer is more than the width of the data cable.
14. preparation method as claimed in claim 13, it is characterised in that after the patterning by the etch-protecting layer, also
Including：The second etch-protecting layer is formed, wherein, second etch-protecting layer is formed in the source-drain electrode region.
15. preparation method as claimed in claim 13, it is characterised in that also include the photoetching at the same time on the first metal layer
Go out grid, the grid is electrically connected with the gate line.
16. preparation method as claimed in claim 15, it is characterised in that formed after the gate insulator, be additionally included in
On the gate insulation layer, deposited semiconductor layer, makes pattern by lithography on the semiconductor layer, forms active layer, and the active layer
Overlap mutually with the grid region.
17. preparation method as claimed in claim 13, it is characterised in that further included after pixel electrode is formed：
Deposit passivation layer, covers the transparent substrate；
On the passivation layer, transparent conductive material is deposited, makes pattern by lithography on the transparent conductive material, forms common electrical
Pole, the common electrode layer cover the pixel electrode；And the public electrode is overlapped with data cable region part,
And overlapped with gate line region part.
18. preparation method as claimed in claim 16, it is characterised in that the semiconductor layer uses oxide semiconductor material
Material.
19. preparation method as claimed in claim 13, it is characterised in that the first etch-protecting layer material is organic film.
20. preparation method as claimed in claim 14, it is characterised in that the second etch-protecting layer material is organic film.
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| CN106935597B (en) | 2017-03-14 | 2020-02-18 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
| CN107765920B (en) * | 2017-10-26 | 2020-01-14 | 惠科股份有限公司 | Signal transmission device and display device |
| CN111863906A (en) | 2020-07-28 | 2020-10-30 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN114512495A (en) | 2020-10-23 | 2022-05-17 | 合肥鑫晟光电科技有限公司 | Array substrate and display device |
| CN114415408A (en) * | 2022-01-21 | 2022-04-29 | 合肥京东方显示技术有限公司 | Display substrate, preparation method thereof and display device |
| CN115032840B (en) * | 2022-06-07 | 2024-05-24 | 广州华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN115951515A (en) * | 2022-12-28 | 2023-04-11 | 长沙惠科光电有限公司 | Display panel, preparation method thereof and display device |
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| CN101393364A (en) * | 2007-09-21 | 2009-03-25 | 北京京东方光电科技有限公司 | TFT LCD pixel structure and method for manufacturing same |
| CN101893799A (en) * | 2009-05-22 | 2010-11-24 | 上海天马微电子有限公司 | Liquid crystal display panel and manufacturing method thereof |
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