CN104409510A - Thin film transistor and preparation method, array substrate and preparation method, and display apparatus - Google Patents
Thin film transistor and preparation method, array substrate and preparation method, and display apparatus Download PDFInfo
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- CN104409510A CN104409510A CN201410588974.6A CN201410588974A CN104409510A CN 104409510 A CN104409510 A CN 104409510A CN 201410588974 A CN201410588974 A CN 201410588974A CN 104409510 A CN104409510 A CN 104409510A
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- 239000010409 thin film Substances 0.000 title claims abstract description 73
- 238000002360 preparation method Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 87
- 239000011241 protective layer Substances 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000010292 electrical insulation Methods 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 30
- 229920002120 photoresistant polymer Polymers 0.000 description 25
- 230000008569 process Effects 0.000 description 23
- 238000000059 patterning Methods 0.000 description 19
- 239000010408 film Substances 0.000 description 16
- 230000008021 deposition Effects 0.000 description 14
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 238000002161 passivation Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910001257 Nb alloy Inorganic materials 0.000 description 1
- 229910000583 Nd alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- VVTQWTOTJWCYQT-UHFFFAOYSA-N alumane;neodymium Chemical compound [AlH3].[Nd] VVTQWTOTJWCYQT-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The invention provides a thin film transistor and a preparation method, an array substrate and a preparation method, and a display apparatus, and belongs to the field of a display technology, for solving the problems of reduced array substrate aperture ratio and low display panel resolution which are caused by quite large dimension of a conventional thin film transistor. The thin film transistor comprises a substrate, a projection structure which is arranged on the substrate, and a gate, a source, a drain and an active layer which are arranged above the substrate, wherein the gate and the active layer cover above the projection structure.
Description
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of thin-film transistor and preparation method thereof, array base palte and preparation method thereof, display unit.
Background technology
Along with the development of Display Technique, the demand of people to display image quality is growing, and the demand of the panel display apparatus of high image quality, high-resolution and high aperture is more and more general, also more and more obtains the attention of display floater producer.Wherein, the main method improving resolution and aperture opening ratio is exactly the size in the light tight region reduced on display floater.And thin-film transistor (Thin Film Transistor is called for short TFT) is the primary drive part of panel display board, be directly connected to the developing direction of high performance flat display unit.
Inventor finds that in prior art, at least there are the following problems: because the size of thin-film transistor is comparatively large, make the size in the light tight region of display floater comparatively large, thus have impact on the resolution of display unit and the raising of aperture opening ratio.
Summary of the invention
Technical problem to be solved by this invention comprises, for the above-mentioned problem that existing thin-film transistor exists, thin-film transistor that a kind of size is less and preparation method thereof is provided, and applies the array base palte of this thin-film transistor and the preparation method of array base palte and display unit.
The technical scheme that solution the technology of the present invention problem adopts is a kind of thin-film transistor, comprise substrate, be arranged on the grid above substrate, source electrode, drain electrode and active layer, it is characterized in that, and being arranged on suprabasil bulge-structure, described grid and active layer cover above described bulge-structure.
Preferably, described bulge-structure is coated with insulating protective layer, described grid is arranged on described insulating protective layer, described active layer to be arranged on above grid and with described grid electrical insulation.
Preferably, described bulge-structure is coated with insulating protective layer, described active layer is arranged on described insulating protective layer, described grid to be arranged on above described active layer and with described active layer electrical insulation.
Further preferably, the material of described insulating protective layer is silicon nitride, silica or both combinations.
Preferably, the thickness of described bulge-structure is between 2um to 3um.
Preferably, the material of described bulge-structure is resin.
The technical scheme that solution the technology of the present invention problem adopts is a kind of preparation method of thin-film transistor, be included in the step forming grid, source electrode, drain electrode and active layer above substrate, and in substrate, form the step of bulge-structure, wherein, described grid and active layer cover above described bulge-structure.
Preferably, described preparation method also comprises: the step forming insulating protective layer in the substrate forming described bulge-structure, wherein said insulating protective layer covers on described bulge-structure.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, and it comprises above-mentioned thin-film transistor.
The technical scheme that solution the technology of the present invention problem adopts is a kind of preparation method of array base palte, and it comprises the preparation method of above-mentioned thin-film transistor.
The technical scheme that solution the technology of the present invention problem adopts is a kind of display unit, and it comprises above-mentioned array base palte.
The grid of thin-film transistor of the present invention and active layer cover above bulge-structure, because bulge-structure exists certain thickness, therefore grid and active layer are less than the physical length size of grid and active layer in the size of suprabasil projection, thus make the size of thin-film transistor compared with the thin-film transistor of the grid and active layer that adopt same size in prior art, the size of thin-film transistor of the present invention reduces relatively, because thin-film transistor is light tight, the aperture opening ratio of array base palte is affected between its size, the size of thin-film transistor also directly affects the number of pixel in display floater simultaneously, the namely resolution of display floater, therefore when thin-film transistor of the present invention is applied in array base palte, because its size is less, therefore it effectively can improve the aperture opening ratio of array base palte, and the resolution of display floater.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the thin-film transistor of the embodiment of the present invention 1;
Fig. 2 is the schematic diagram of the array base palte of embodiments of the invention 1;
Wherein Reference numeral is: 1, substrate; 2, grid; 3, gate insulator; 4, active layer; 5-1, source electrode; 5-2, drain electrode; 6, bulge-structure; 7, insulating protective layer; 8, passivation layer; 9, pixel electrode.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
A kind of thin-film transistor, comprises substrate, is arranged on the grid above substrate, source electrode, drain electrode and active layer, and described thin-film transistor also comprises and is arranged on suprabasil bulge-structure, and described grid and active layer are arranged on above described bulge-structure.
A kind of array base palte, comprises above-mentioned thin-film transistor.
A kind of display unit, comprises above-mentioned array base palte.
A preparation method for thin-film transistor, be included in the step forming grid, source electrode, drain electrode and active layer above substrate, and in substrate, form the step of bulge-structure, wherein, described grid and active layer cover above described bulge-structure.
A preparation method for array base palte, comprises the above-mentioned step preparing thin-film transistor.
It should be noted that, in the following embodiments, so-and-so described layer is arranged on so-and-so layer " top ", now this double-layer structure can be contact also can be non-contacting just structure last layer last layer under; And so-and-so described layer be arranged on so-and-so layer " on ", now then represent that two-layer to be one deck contact with each other at lower and double-layer structure at last layer for this.
Described in the following embodiments " patterning processes ", can only include photoetching process, or, comprise photoetching process and etch step, other techniques for the formation of predetermined pattern such as printing, ink-jet can also be comprised simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. that comprise the technical processs such as film forming, exposure, development form the technique of figure.Can according to the structure choice formed in the present invention corresponding patterning processes.
Described " thickness " in the following embodiments refers to perpendicular to the height on substrate direction.
Embodiment 1:
A kind of thin-film transistor, comprises substrate, is arranged on the grid above substrate, source electrode, drain electrode and active layer, and described thin-film transistor also comprises and is arranged on suprabasil bulge-structure, and described grid and active layer are arranged on above described bulge-structure.
In the present embodiment, as shown in Figure 1, this thin-film transistor is top gate type thin film transistor, substrate 1 is provided with bulge-structure 6, bulge-structure 6 is coated with grid 2, grid 2 is provided with gate insulator 3, gate insulator 3 is provided with active layer 4, active layer 4 is provided with source electrode 5-1 and drain electrode 5-2.
The grid 2 of the thin-film transistor of the present embodiment and active layer 4 cover above bulge-structure 6, because bulge-structure 6 exists certain thickness, therefore the size of grid 2 and active layer 4 projection is on the base 1 less than the physical length size of grid 2 and active layer 4, thus make the size of thin-film transistor compared with the thin-film transistor of the grid 2 adopting same size in prior art and active layer 4, the size of the thin-film transistor of the present embodiment reduces relatively, because thin-film transistor is light tight, the aperture opening ratio of array base palte is affected between its size, the size of thin-film transistor also directly affects the number of pixel in display floater simultaneously, the namely resolution of display floater, therefore when the thin-film transistor of the present embodiment is applied in array base palte, because its size is less, therefore it effectively can improve the aperture opening ratio of array base palte, and the resolution of display floater.
In the present embodiment; at least one material in grid 2 usual molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium and copper is formed; in order to improve the caking property of metal material and bulge-structure 6; therefore preferably between bulge-structure 6 and grid 2, be also provided with insulating protective layer 7; make grid 2 can well cover above bulge-structure 6, to ensure the stability of thin-film transistor.The material of this insulating protective layer 7 is preferably silicon nitride, silica or both combinations.
In the present embodiment, the material of bulge-structure 6 is resin (such as polyimides).Rupture because the thickness of bulge-structure 6 produces section difference to prevent from covering grid 2 above bulge-structure 6 and active layer 4, therefore its thickness is preferably between 2um to 3um, can certainly can specifically set as the case may be.
The preparation method of above-mentioned thin-film transistor, comprise the step being formed in and forming grid 2, source electrode 5-1, drain electrode 5-2 and active layer 4 above substrate 1, and the step of bulge-structure 6 is formed in the below of grid 2, wherein, described grid 2 and active layer 4 cover above described bulge-structure 6.
Preferably, be also included in this preparation method form bulge-structure 6 substrate on form the step of insulating protective layer 7, described grid 2 is formed on insulating protective layer 7.
Shown in composition graphs 2, the present embodiment also provides a kind of array base palte, and this array base palte comprises above-mentioned thin-film transistor.
In this array base palte, also layer is provided with grid line with grid 2, grid line is electrically connected with grid 2, and grid line adopts identical material with grid 2 and formed in same patterning processes; Also layer is provided with data wire with source electrode 5-1, data wire is electrically connected with source electrode 5-1, and data wire adopts identical material with source electrode 5-1 and formed in same patterning processes.And, above source electrode 5-1 and drain electrode 5-2, be also provided with passivation layer 8, above passivation layer 8, be also provided with pixel electrode 9.
A preparation method for array base palte, comprises the preparation method of above-mentioned formation thin-film transistor.Specifically comprise the steps:
Step 1, employing patterning processes form the figure comprising bulge-structure 6 on the base 1.
In this step, the rete graph exposure of the rete deposition → bulge-structure 6 of initial wash → bulge-structure 6, development, rear baking → photoresist lift off.
Step 2, employing patterning processes form the figure comprising insulating protective layer 7 and grid 2, and wherein, insulating protective layer 7 is arranged on bulge-structure 6, and grid 2 is arranged on insulating protective layer 7.
In this step, the front cleaning → insulating protective layer 7 of film forming deposits → gate metal rete deposition → photoresist coating → grid metal film layer pattern exposure imaging, rear baking → etching → photoresist lift off.
Step 3, employing patterning processes form the figure comprising gate insulation layer, active layer 4.
In this step, film forming front cleaning → gate insulation layer deposition → semiconductor film → photoresist coating → semiconductor film graph exposure development, rear baking → semiconductor film dry etching → photoresist lift off.
Step 4, employing patterning processes form the figure comprising source electrode 5-1 and drain electrode 5-2.
In this step, source and drain metallic diaphragm deposition → photoresist coating → source-drain electrode rete graph exposure development, rear baking → source-drain electrode rete etching → photoresist lift off.
So far, namely thin-film transistor has been prepared, and has been pre-formed grid line and data wire, to facilitate the wiring of array base palte.
Step 5, employing patterning processes form the figure comprising passivation layer 8 and electrode contact via hole thereof.
In this step, passivation film deposition → photoresist coating → electrode contact via pattern exposure, development, rear baking → electrode contact via etch → photoresist lift off.
Step 6, employing patterning processes form the figure comprising pixel electrode 9.
In this step, the development of pixel electrode 9 rete deposition (ITO or IZO: tin indium oxide or indium zinc oxide) → photoresist coating → pixel electrode 9 rete graph exposure, the etching → photoresist lift off → annealing of rear baking → pixel electrode 9 rete.
The figure of the counter structure that the figure of the concrete structure of array base palte can be prepared with reference to array base palte in prior art in the present embodiment, concrete technology in array base palte preparation method with reference to the corresponding technique in array base palte preparation method in prior art, can repeat no more here.
Embodiment 2:
The present embodiment provides a kind of thin-film transistor, this thin-film transistor is top gate type thin film transistor, it specifically comprises: substrate, substrate is provided with bulge-structure, be provided with active layer above bulge-structure, active layer is provided with gate insulator, gate insulator is provided with grid, grid is provided with planarization layer, planarization layer is provided with source electrode and drain electrode.
The grid of the thin-film transistor of the present embodiment and active layer cover above bulge-structure, because bulge-structure exists certain thickness, therefore the size of grid and active layer projection is on the base 1 less than the physical length size of grid and active layer, thus make the size of thin-film transistor compared with the thin-film transistor of the grid and active layer that adopt same size in prior art, the size of the thin-film transistor of the present embodiment reduces relatively, because thin-film transistor is light tight, the aperture opening ratio of array base palte is affected between its size, the size of thin-film transistor also directly affects the number of pixel in display floater simultaneously, the namely resolution of display floater, therefore when the thin-film transistor of the present embodiment is applied in array base palte, because its size is less, therefore it effectively can improve the aperture opening ratio of array base palte, and the resolution of display floater.
In the present embodiment in order to ensure the adhesive property of active layer and bulge-structure, preferably between bulge-structure and active layer, be also provided with insulating protective layer, active layer can well be covered above bulge-structure, to ensure the stability of thin-film transistor.The material of this insulating protective layer is preferably silicon nitride, silica or both combinations.
In the present embodiment, the material of bulge-structure is resin or polyimides.Rupture because the thickness of bulge-structure produces section difference to prevent from covering grid above bulge-structure and active layer, thus its thickness preferably between 2um to 3um between, can certainly can specifically set as the case may be.
The preparation method of above-mentioned thin-film transistor, comprise the step being formed in and forming grid, source electrode, drain electrode and active layer above substrate, and form the step of bulge-structure in the below of grid, wherein, described grid and active layer cover above described bulge-structure.
Preferably, be also included in this preparation method form bulge-structure substrate on form the step of insulating protective layer, described active layer is formed on insulating protective layer.
The present embodiment also provides a kind of array base palte, and this array base palte comprises above-mentioned thin-film transistor.
In this array base palte, also layer is provided with grid line with grid, grid line is electrically connected with grid, and grid line and grid adopt identical material and formed in same patterning processes; Also layer is provided with data wire with source electrode, data wire is electrically connected with source electrode, and data wire and source electrode adopt identical material and formed in same patterning processes.And, above source electrode and drain electrode, be also provided with passivation layer, above passivation layer, be also provided with pixel electrode.
A preparation method for array base palte, comprises the preparation method of above-mentioned formation thin-film transistor.Specifically comprise the steps:
Step 1, formed the figure comprising bulge-structure on the base 1 by patterning processes.
In this step, the rete graph exposure of the rete deposition → bulge-structure of initial wash → bulge-structure, development, rear baking → photoresist lift off.
Step 2, formed the figure comprising insulating protective layer and active layer by patterning processes, wherein, insulating protective layer is arranged on bulge-structure, and active layer is arranged on insulating protective layer.
In this step, the front cleaning of film forming → insulating protective layer deposition → semiconductor film deposition → photoresist coating → semiconductor film graph exposure development, rear baking → etching → photoresist lift off.
Step 3, employing patterning processes form the figure comprising gate insulation layer, grid.
In this step, the front cleaning of film forming → gate insulation layer deposition → grid metal film rete → photoresist coating → grid metal film layer pattern exposure imaging, rear baking → gate metal rete dry etching → photoresist lift off.
Step 4, employing patterning processes are formed and comprise planarization layer and run through planarization layer with gate insulator for source electrode and the via hole be connected with active layer that drains.
In this step, planarization layer rete deposition → photoresist coating → planarization layer rete and gate insulator graph exposure development, rear baking → etching → photoresist lift off.
Step 5, employing patterning processes form the figure comprising source electrode and drain electrode.
In this step, source and drain metallic diaphragm deposition → photoresist coating → source-drain electrode rete graph exposure development, rear baking → source-drain electrode rete etching → photoresist lift off.
So far, namely thin-film transistor has been prepared, and has been pre-formed grid line and data wire, to facilitate the wiring of array base palte.
Step 6, employing patterning processes form the figure comprising passivation layer and electrode contact via hole thereof.
In this step, passivation film deposition → photoresist coating → electrode contact via pattern exposure, development, rear baking → electrode contact via etch → photoresist lift off.
Step 7, employing patterning processes form the figure comprising pixel electrode.
In this step, pixel electrode rete deposition (ITO or IZO: tin indium oxide or indium zinc oxide) → photoresist coating → pixel electrode film layer pattern exposure imaging, rear baking → pixel electrode rete etching → photoresist lift off → annealing.
The figure of the counter structure that the figure of the concrete structure of array base palte can be prepared with reference to array base palte in prior art in the present embodiment, concrete technology in array base palte preparation method with reference to the corresponding technique in array base palte preparation method in prior art, can repeat no more here.
Embodiment 3:
A kind of display unit, comprises the array base palte exemplified by embodiment 1 or 2.
This display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Because in the array base palte of employing, the size of thin-film transistor is less, therefore this display unit has good aperture opening ratio and resolution.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (11)
1. a thin-film transistor, comprise substrate, and be arranged on grid above substrate, source electrode, drain electrode and active layer, it is characterized in that, described thin-film transistor also comprises and is arranged on suprabasil bulge-structure, and described grid and active layer cover above described bulge-structure.
2. thin-film transistor according to claim 1, is characterized in that, described bulge-structure is coated with insulating protective layer, and described grid is arranged on described insulating protective layer, described active layer to be arranged on above grid and with described grid electrical insulation.
3. thin-film transistor according to claim 1; it is characterized in that; described bulge-structure is coated with insulating protective layer, and described active layer is arranged on described insulating protective layer, described grid to be arranged on above described active layer and with described active layer electrical insulation.
4. the thin-film transistor according to Claims 2 or 3, is characterized in that, the material of described insulating protective layer is silicon nitride, silica or both combinations.
5. thin-film transistor according to claim 1, is characterized in that, the thickness of described bulge-structure is between 2um to 3um.
6. thin-film transistor according to claim 1, is characterized in that, the material of described bulge-structure is resin.
7. a preparation method for thin-film transistor, be included in the step forming grid, source electrode, drain electrode and active layer above substrate, it is characterized in that, described preparation method also comprises:
Substrate is formed the step of bulge-structure, and wherein, described grid and active layer cover above described bulge-structure.
8. the preparation method of thin-film transistor according to claim 7; it is characterized in that; described preparation method also comprises: the step forming insulating protective layer in the substrate forming described bulge-structure, wherein said insulating protective layer covers on described bulge-structure.
9. an array base palte, is characterized in that, comprises the thin-film transistor in claim 1 to 6 described in any one.
10. a preparation method for array base palte, comprises the step forming thin-film transistor, it is characterized in that, described thin-film transistor adopts the preparation method described in claim 7 or 8 to prepare.
11. 1 kinds of display unit, is characterized in that, comprise array base palte according to claim 9.
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