CN110854205A - Thin film transistor, manufacturing method, display panel and display device - Google Patents
Thin film transistor, manufacturing method, display panel and display device Download PDFInfo
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- CN110854205A CN110854205A CN201911190006.9A CN201911190006A CN110854205A CN 110854205 A CN110854205 A CN 110854205A CN 201911190006 A CN201911190006 A CN 201911190006A CN 110854205 A CN110854205 A CN 110854205A
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- 239000010409 thin film Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims description 167
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 13
- 230000008569 process Effects 0.000 description 20
- 238000010586 diagram Methods 0.000 description 9
- 239000002184 metal Substances 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
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Abstract
The invention provides a thin film transistor, a manufacturing method, a display panel and a display device, wherein the thin film transistor comprises: the grid electrode comprises an active layer, a grid electrode and a grid electrode insulating layer, wherein the grid electrode insulating layer is arranged between the active layer and the grid electrode, the active layer comprises electrode connecting regions arranged at intervals and a channel region arranged between the electrode connecting regions, the grid electrode insulating layer has a first thickness at the position corresponding to the electrode connecting regions, the grid electrode insulating layer has a second thickness at the position corresponding to the channel region, and the first thickness is larger than the second thickness. The method is used for reducing the parasitic capacitance of the thin film transistor and improving the display effect of the display device.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a manufacturing method of the thin film transistor, a display panel and a display device.
Background
The thickness of the gate insulating layer of the existing thin film transistor is 1000-2000 angstroms, and the thickness of the gate insulating layer is thin. In the case of a top gate thin film transistor, the parasitic capacitance between the gate metal layer and the conductive active layer is large because the gate insulating layer is thin. In the case of a bottom gate thin film transistor, the parasitic capacitance between the gate metal layer and the source/drain is large because the gate insulating layer is thin. In any thin film transistor, once the parasitic capacitance increases, the resistance capacitance Delay (RC Delay) effect of the circuit increases accordingly, resulting in poor display performance of the display device.
Disclosure of Invention
The invention provides a thin film transistor, a manufacturing method of the thin film transistor, a display panel and a display device, which are used for reducing the parasitic capacitance of the thin film transistor and improving the display effect of the display device.
In a first aspect, an embodiment of the present invention provides a thin film transistor, including:
the grid electrode comprises an active layer, a grid electrode and a grid electrode insulating layer, wherein the grid electrode insulating layer is arranged between the active layer and the grid electrode, the active layer comprises electrode connecting regions arranged at intervals and a channel region arranged between the electrode connecting regions, the grid electrode insulating layer has a first thickness at the position corresponding to the electrode connecting regions, the grid electrode insulating layer has a second thickness at the position corresponding to the channel region, and the first thickness is larger than the second thickness.
Optionally, the active layer is located between the gate and the substrate.
Optionally, the device further comprises an interlayer insulating layer, a source drain electrode and a passivation layer which are sequentially arranged on the gate electrode, wherein the source drain electrode is electrically connected with the electrode connection region through a via hole penetrating through the interlayer insulating layer.
Optionally, an orthographic projection of the gate insulating layer on the active layer and an orthographic projection of the via hole on the active layer are not overlapped with each other.
Optionally, the gate electrode is located between the active layer and the substrate.
Optionally, the device further comprises a source drain electrode disposed on the active layer, and the source drain electrode is directly in contact and electrically connected with the electrode connection region.
In a second aspect, embodiments of the present invention provide a display panel including the thin film transistor as described above.
In a third aspect, embodiments of the present invention further provide a display device, including the display panel described above.
In a fourth aspect, an embodiment of the present invention further provides a method for manufacturing a thin film transistor, where the method includes:
forming a pattern of an active layer on a substrate, wherein the active layer includes electrode connection regions disposed at intervals and a channel region disposed between the electrode connection regions;
forming a pattern of a gate insulating layer by using a half-tone mask plate, wherein the gate insulating layer has a first thickness at a position corresponding to the electrode connecting region, the gate insulating layer has a second thickness at a position corresponding to the channel region, and the first thickness is greater than the second thickness;
patterning a gate electrode, the gate insulating layer being disposed between the active layer and the gate electrode.
Optionally, the forming a pattern of the gate insulating layer by using a halftone mask includes:
depositing the gate insulating layer of the first thickness;
coating photoresist on the gate insulating layer;
patterning the photoresist by using a half-tone mask to form a pattern of the photoresist;
etching a third thickness of the gate insulating layer at a position corresponding to the channel region according to the pattern of the photoresist, wherein the difference between the first thickness and the third thickness is the second thickness;
and removing the pattern of the photoresist to form the pattern of the gate insulating layer.
The invention has the following beneficial effects:
in the thin film transistor, the manufacturing method thereof, the display panel and the display device provided by the embodiment of the invention, the gate insulating layer arranged between the active layer and the gate electrode has a first thickness at a position corresponding to the electrode connection region, and has a second thickness smaller than the first thickness at a position corresponding to the channel region. Therefore, the thickness of the gate insulating layer at the position corresponding to the electrode connecting area is larger, so that the parasitic capacitance of the thin film transistor at the position corresponding to the electrode connecting area is reduced, and the display effect of the display device is improved.
Drawings
FIG. 1 is a schematic structural diagram of a conventional TFT with a top gate structure;
fig. 2 is a schematic structural diagram of a thin film transistor with a top gate structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a thin film transistor with a top gate structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a thin film transistor with a bottom gate structure according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a thin film crystal having a bottom gate structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 7 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present invention;
FIG. 8 is a flow chart of another method for fabricating a thin film transistor according to an embodiment of the present invention;
fig. 9 is a flowchart of a method of step S102 in a method for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 10 is a flowchart illustrating a manufacturing process of a thin film transistor with a top-gate structure according to an embodiment of the present invention;
fig. 11 is a flowchart illustrating a manufacturing process of a thin film transistor with a top-gate structure according to an embodiment of the present invention;
fig. 12 is a flowchart illustrating a manufacturing process of a thin film transistor with a bottom gate structure according to an embodiment of the present invention.
Detailed Description
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Fig. 1 is a schematic structural diagram of a conventional thin film transistor with a top gate structure. The manufacturing process of the structure comprises the steps of firstly forming a pattern of a light shielding layer 2 on a substrate 1 by using a composition process, then depositing a buffer layer 3, then forming a pattern of an active layer 4, then depositing a gate insulating layer 5, then depositing a gate metal layer 6, forming a pattern of the gate metal layer 6 by using a wet etching process, and forming a pattern of the gate insulating layer 5 by using a dry etching process. Conducting conductor treatment on the active layer 4 outside the channel region, depositing an interlayer insulating layer 7, forming a via hole on the interlayer insulating layer 7 by using a composition process, depositing a source/drain metal layer 8, and forming a source and drain pattern by using the composition process; a passivation layer 9 is then deposited to form the thin film transistor as described in figure 1. Due to the thin thickness of the gate insulating layer 5, the parasitic capacitance between the gate metal layer 6 and the conductive active layer 4 is large, so that the rc delay effect of the corresponding loop is increased, and the display effect of the display device is poor.
In view of this, an embodiment of the present invention provides a thin film transistor, as shown in fig. 2, including: an active layer 20, a gate electrode 30 and a gate insulating layer 40 on the substrate 10, the gate insulating layer 40 being disposed between the active layer 20 and the gate electrode 30, the active layer 20 including electrode connection regions a disposed at intervals and a channel region B disposed between the electrode connection regions a. The gate insulating layer 40 has a first thickness at a position corresponding to the electrode connection region a, and the gate insulating layer 40 has a second thickness at a position corresponding to the channel region B, wherein the first thickness is greater than the second thickness. For example, if the gate insulating layer 40 has a first thickness d1 at a position corresponding to the electrode connection region a and a second thickness d2 at a position corresponding to the channel region B, the first thickness d1> d 2. The gate insulating layer 40 has a second thickness in a range of 1000 angstroms to 1500 angstroms at a position corresponding to the channel region B. Accordingly, the second thickness thereof at the position corresponding to the electrode connecting region a is larger than the range, for example, the second thickness is 2000 angstroms. In a specific implementation process, the second thickness may be the same as the thickness of the gate insulating layer 5 in the existing thin film transistor, and the first thickness is greater than the thickness of the gate insulating layer 5 in the existing thin film transistor, so that the parasitic capacitance of the thin film transistor at the position corresponding to the electrode connection area a is reduced, and the display effect of the display device is improved.
In the embodiment of the present invention, in which the thin film transistor is a top gate structure, in conjunction with fig. 2 and 3, the active layer 20 is disposed between the gate electrode 30 and the substrate 10. As shown in fig. 3, which is a schematic structural diagram of a top-gate thin film transistor, the thin film transistor further includes an interlayer insulating layer 50, a source/drain 60, and a passivation layer 103 sequentially disposed on the gate 30, wherein the source/drain 60 is electrically connected to the electrode connection region B through a via hole penetrating through the interlayer insulating layer 50. In a specific implementation process, the orthographic projection of the gate insulating layer 40 on the active layer 20 and the orthographic projection of the via hole on the active layer 20 are not overlapped with each other, so that the electrical connection between the source and drain electrodes 60 and the active layer 20 is ensured.
In the embodiment of the present invention, when the thin film transistor is a top gate structure, a light-shielding layer 101 and a buffer layer 102 are further disposed between the substrate 10 and the active layer 20, as shown in fig. 3.
In a specific implementation process, when the thin film transistor is of a top gate structure, the second thickness of the gate insulating layer 40 at the position corresponding to the channel region B may be the same as the thickness of the gate insulating layer 5 in the conventional thin film transistor shown in fig. 1, and the first thickness of the gate insulating layer 40 at the position corresponding to the electrode connection region a is greater than the thickness of the gate insulating layer 5 in the conventional thin film transistor shown in fig. 1, so that while it is ensured that the gate electrode 30 effectively controls the active layer 20 at the position corresponding to the channel region B, the parasitic capacitance between the active layer 20 and the gate electrode 30 at the position corresponding to the electrode connection region a is reduced, thereby improving the display effect of the display device.
In the embodiment of the present invention, the thin film transistor may also have a bottom gate structure as shown in fig. 4, and specifically, the gate electrode 30 is located between the active layer 20 and the substrate 10. In a specific implementation process, the thin film transistor shown in fig. 5 is another structural schematic diagram of a bottom-gate structure, and specifically, the thin film transistor further includes a source/drain 60 disposed on the active layer 20, and the source/drain 60 is directly in contact with and electrically connected to the electrode connection region a. In a specific implementation process, the second thickness of the gate insulating layer 40 at the position corresponding to the channel region B may be the same as the thickness of the gate insulating layer 5 in the existing thin film transistor shown in fig. 1, and the first thickness of the gate insulating layer 40 at the position corresponding to the electrode connection region a is greater than the thickness of the gate insulating layer 5 in the existing thin film transistor shown in fig. 1, so that while the gate 30 is ensured to effectively control the active layer 20 at the position corresponding to the channel region B, the parasitic capacitance between the source drain 60 and the gate 30 at the position corresponding to the electrode connection region a is reduced, thereby improving the display effect of the display device. In the bottom gate structure of the thin film transistor shown in fig. 5, a passivation layer 103 is further provided on the source and drain electrodes 60.
Based on the same inventive concept, embodiments of the present invention also provide a display panel including the thin film transistor as described above. Specifically, the display panel may be an electro-luminescence display panel (AMOLED), and may also be a liquid crystal display panel (LCD). The principle of the display panel to solve the problem is similar to the aforementioned thin film transistor, so the implementation of the display panel can be referred to the implementation of the aforementioned thin film transistor.
Based on the same inventive concept, as shown in fig. 6, an embodiment of the present invention further provides a display device 100 including the display panel 200 according to the embodiment of the present invention. The principle of the display device 100 to solve the problem is similar to the aforementioned thin film transistor, so the implementation of the display device 100 can refer to the implementation of the aforementioned thin film transistor, and the repeated points are not described herein again.
In specific implementation, the display device 100 provided in the embodiment of the present invention may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device 100 should be understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present invention.
Based on the same inventive concept, as shown in fig. 7, an embodiment of the present invention further provides a method for manufacturing a thin film transistor, including:
s101: forming a pattern of an active layer on a substrate, wherein the active layer includes electrode connection regions disposed at intervals and a channel region disposed between the electrode connection regions;
s102: forming a pattern of a gate insulating layer by using a half-tone mask plate, wherein the gate insulating layer has a first thickness at a position corresponding to the electrode connecting region, the gate insulating layer has a second thickness at a position corresponding to the channel region, and the first thickness is greater than the second thickness;
s103: patterning a gate electrode, the gate insulating layer being disposed between the active layer and the gate electrode.
In a specific implementation, when the thin film transistor has a top gate structure, the sequence of steps S101 to S103 is as shown in fig. 7, specifically, first, a pattern of an active layer 20 is formed on a substrate 10, wherein the active layer 20 includes electrode connection regions a disposed at intervals and channel regions B disposed between the electrode connection regions a. Then, using a half-tone mask, a pattern of a gate insulating layer 40 is formed, the gate insulating layer 40 having a first thickness at a position corresponding to the electrode connection region a, and the gate insulating layer 40 having a second thickness smaller than the first thickness at a position corresponding to the channel region B. Then, the gate electrode 30 is patterned, and the gate insulating layer 40 is disposed between the active layer 20 and the gate electrode 30.
In a specific implementation, when the thin film transistor is a bottom gate structure, the sequence of steps S101 to S103 is as shown in fig. 8, specifically, first, a pattern of the gate electrode 30 is formed on the substrate 10, and then, a pattern of the gate insulating layer 40 is formed by using a half-tone mask, where the gate insulating layer 40 has a first thickness at a position corresponding to the electrode connection region a, and the gate insulating layer 40 has a second thickness smaller than the first thickness at a position corresponding to the channel region B. Then, the active layer 20 is patterned on the gate insulating layer 40.
In a specific implementation process, when the thin film transistor in the embodiment of the present invention is of a top gate structure or a bottom gate structure, the second thickness may be the same as a thickness of the gate insulating layer 5 in the existing thin film transistor, and the first thickness is greater than the thickness of the gate insulating layer 5 in the existing thin film transistor, so that a parasitic capacitance of the thin film transistor at a position corresponding to the electrode connection area a is reduced, thereby improving a display effect of the display device.
In the embodiment of the present invention, as shown in fig. 9, step S102: forming a pattern of a gate insulating layer using a half-tone mask, including:
s201: depositing the gate insulating layer of the first thickness;
s202: coating photoresist on the gate insulating layer;
s203: patterning the photoresist by using a half-tone mask to form a pattern of the photoresist;
s204: etching a third thickness of the gate insulating layer at a position corresponding to the channel region according to the pattern of the photoresist, wherein the difference between the first thickness and the third thickness is the second thickness;
s205: and removing the pattern of the photoresist to form the pattern of the gate insulating layer.
In a specific implementation process, when the thin film transistor is of a top gate structure, the specific implementation process of steps S201 to S205 may be that, first, after the pattern of the active layer 20 is formed, the gate insulating layer 40 with a first thickness is deposited on the active layer 20, then the photoresist 70 is coated on the gate insulating layer 40, and then the photoresist 70 is patterned by using a halftone mask. Then, the gate insulating layer 40 outside the region where the photoresist 70 is located is etched away by a second thickness according to the pattern of the photoresist 70. Then, ashing is performed on the photoresist 70 at a position corresponding to the channel region B, and then the exposed gate insulating layer 40 is etched to a third thickness, wherein a dry etching process may be used for etching. The photoresist 70 is then removed. Wherein, the difference value between the first thickness and the third thickness is the second thickness. For example, the first thickness is 2000 angstroms, the second thickness is 1500 angstroms, and the third thickness is 500 angstroms. Fig. 10 is a manufacturing flow chart corresponding to the manufacturing method shown in fig. 9 when the thin film transistor is a top gate structure. The thickness of the gate insulating layer 40 at the corresponding position of the channel region B is ensured to be the second thickness by adjusting the thickness of each part of the gate insulating layer 40, and the thickness of the gate insulating layer 40 at the corresponding position of the electrode connecting region a is ensured to be the first thickness larger than the second thickness, so that the parasitic capacitance of the thin film transistor at the electrode connecting region a is reduced, and the display effect of the display device is improved.
In a specific implementation process, when the thin film transistor has a top gate structure, the specific implementation process of steps S201 to S205 may also be that, first, after forming the pattern of the active layer 20, the gate insulating layer 40 with a first thickness is deposited on the active layer 20, then the photoresist 70 is coated on the gate insulating layer 40, and then, the photoresist 70 is patterned by using a halftone mask to form the pattern of the photoresist 70. Then, the gate insulating layer 40 outside the region where the photoresist 70 is located is etched away by a first thickness according to the pattern of the photoresist 70. Then, the photoresist 70 at the position corresponding to the channel region B is subjected to ashing treatment, and then, the gate insulating layer 40 at the position corresponding to the channel region B is etched to a third thickness, wherein a difference between the first thickness and the third thickness is the second thickness. The photoresist 70 is then removed. Fig. 11 is a manufacturing flow chart corresponding to the manufacturing method shown in fig. 9 when the thin film transistor is a top gate structure. In this way, the thickness of the gate insulating layer 40 at the position corresponding to the channel region B is ensured to be the second thickness, and the thickness of the gate insulating layer 40 at the position corresponding to the electrode connection region a is ensured to be the first thickness greater than the second thickness, so that the parasitic capacitance of the thin film transistor at the electrode connection region a is reduced, and the display effect of the display device is improved.
In a specific implementation process, when the thin film transistor is a bottom gate structure, the specific implementation process of steps S201 to S205 may be that, first, a pattern of the gate 30 is formed on the substrate 10 through a wet etching process, then, after the pattern of the gate 30 is formed, the gate insulating layer 40 with a first thickness is deposited on the gate 30, then, the photoresist 70 is coated on the gate insulating layer 40, and then, the photoresist 70 is patterned by using a mask to form the pattern of the photoresist 70. Then, according to the pattern of the photoresist 70, the gate insulating layer 40 corresponding to the position where the active layer 20 is to be disposed is etched to a third thickness, which may be etched by a dry etching process. This patterns the gate insulating layer 40. Fig. 12 is a manufacturing flowchart corresponding to the manufacturing method shown in fig. 9 when the thin film transistor is a bottom gate structure. Wherein, the difference value between the first thickness and the third thickness is the second thickness. For example, the first thickness is 2000 angstroms, the second thickness is 1500 angstroms, and the third thickness is 500 angstroms. In this way, the thickness of the gate insulating layer 40 at the position corresponding to the channel region B is ensured to be the second thickness, and the thickness of the gate insulating layer 40 at the position corresponding to the electrode connection region a is ensured to be the first thickness greater than the second thickness, so that the parasitic capacitance of the thin film transistor at the electrode connection region a is reduced, and the display effect of the display device is improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A thin film transistor, comprising:
the grid electrode comprises an active layer, a grid electrode and a grid electrode insulating layer, wherein the grid electrode insulating layer is arranged between the active layer and the grid electrode, the active layer comprises electrode connecting regions arranged at intervals and a channel region arranged between the electrode connecting regions, the grid electrode insulating layer has a first thickness at the position corresponding to the electrode connecting regions, the grid electrode insulating layer has a second thickness at the position corresponding to the channel region, and the first thickness is larger than the second thickness.
2. The thin film transistor of claim 1, wherein the active layer is between the gate electrode and the substrate.
3. The thin film transistor according to claim 2, further comprising an interlayer insulating layer, a source drain, and a passivation layer sequentially disposed over the gate electrode, wherein the source drain is electrically connected to the electrode connection region through a via hole penetrating the interlayer insulating layer.
4. The thin film transistor according to claim 3, wherein an orthographic projection of the gate insulating layer on the active layer and an orthographic projection of the via hole on the active layer do not coincide with each other.
5. The thin film transistor of claim 1, wherein the gate electrode is between the active layer and the substrate.
6. The thin film transistor of claim 5, further comprising a source drain disposed over the active layer, the source drain being electrically connected in direct contact with the electrode connection region.
7. A display panel comprising the thin film transistor according to any one of claims 1 to 6.
8. A display device characterized by comprising the display panel according to claim 7.
9. A method of manufacturing a thin film transistor according to any one of claims 1 to 6, comprising:
forming a pattern of an active layer on a substrate, wherein the active layer includes electrode connection regions disposed at intervals and a channel region disposed between the electrode connection regions;
forming a pattern of a gate insulating layer by using a half-tone mask plate, wherein the gate insulating layer has a first thickness at a position corresponding to the electrode region, the gate insulating layer has a second thickness at a position corresponding to the channel region, and the first thickness is greater than the second thickness;
patterning a gate electrode, the gate insulating layer being disposed between the active layer and the gate electrode.
10. The method of claim 9, wherein patterning the gate insulating layer using a halftone mask comprises:
depositing the gate insulating layer of the first thickness;
coating photoresist on the gate insulating layer;
patterning the photoresist by using a half-tone mask to form a pattern of the photoresist;
etching a third thickness of the gate insulating layer at a position corresponding to the channel region according to the pattern of the photoresist, wherein the difference between the first thickness and the third thickness is the second thickness;
and removing the pattern of the photoresist to form the pattern of the gate insulating layer.
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