TWI457672B - Pixel structure and manufacturing method thereof - Google Patents

Description

Pixel structure and its manufacturing method

The present invention relates to a structure of a component and a method of fabricating the same, and more particularly to a pixel structure and a method of fabricating the same.

The flat panel display mainly has the following types: an organic electroluminescence display, a plasma display panel, and a thin film transistor liquid crystal display, wherein a thin film transistor liquid crystal display The display is the most widely used. In general, a thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer, wherein the thin film transistor array The substrate includes a plurality of scan lines, a plurality of capacitor electrode lines, a plurality of data lines, and a plurality of array-arranged active elements and a plurality of pixel electrodes connected to the active elements. Each of the active components is electrically connected to the corresponding scan line and the data line.

The fabrication process of a thin film transistor array substrate typically includes multiple lithography and etching steps. In common manufacturing techniques, the gate, scan line and capacitor electrode lines are formed only by the first conductive layer, and the source, drain and data lines are only formed by the second conductive layer, wherein the first conductive layer And having at least one dielectric layer between the second conductive layers, and the second conductive layer is closer to the pixel electrode of the two conductive layers. Such designs often affect the display voltage on the pixel electrodes due to the coupling effect between the pixel electrodes and the data lines. Therefore, a technique of fabricating a data line using only the first conductive layer is proposed, and in this technique, the capacitor electrode line can be made only by the second conductive layer to overlap the arrangement area of the capacitor electrode line and the data line to reduce the conductive layer. The configured area of the component. However, since the capacitor electrode line is at least partially overlapped with the data line, there is usually a so-called parasitic capacitance between the capacitor electrode line and the data line. The presence of parasitic capacitance will increase the load of the data line and is not conducive to the driving of the thin film transistor array.

The present invention provides a pixel structure which can reduce the parasitic capacitance of a pixel structure and thereby reduce the power consumption of the pixel structure.

The present invention provides a method of fabricating a pixel structure that simplifies the process steps to reduce the number of reticle used and reduce the cost.

The invention provides a pixel structure comprising a substrate, a scan line, a data line, a first insulating layer, an active device, a second insulating layer, a capacitor electrode and a first pixel electrode. The scan line is disposed on the substrate. The data line is disposed on the substrate, the scan line is interlaced with the data line, and the data line includes a linear transmission portion and an overhead transmission portion connected to each other, wherein the overhead transmission portion spans the scan line. The first insulating layer covers the scan line and the linear transfer portion and is located between the scan line and the jumper transfer portion. The active component is connected to the scan line and the data line, wherein the active component includes a gate, an oxide channel, a source and a drain. The gate is connected to the scan line. The oxide channel is above the gate and the first insulating layer is between the gate and the oxide channel. The source is connected to the cross-line transmission part of the data line. The source and drain are located on either side of the oxide channel. The second insulating layer includes an etch barrier pattern over the oxide channel and an isolation pattern over the linear transfer portion, and the isolation pattern contacts the first insulating layer. The capacitor electrode is disposed on the isolation pattern and above the linear transmission portion. The first pixel electrode is connected to the drain.

The present invention proposes a method of fabricating a pixel structure comprising the following steps. The patterned first conductive layer forms a scan line, a gate and a linear transmission portion on the substrate, the gate is connected to the scan line, and the linear transmission portion and the scan line are separated from each other, wherein the extending direction of the scan line is opposite to the extending direction of the linear transmission portion staggered. A first insulating layer is formed on the substrate to cover the scan lines, the gates, and the linear transfer portion. An oxide channel above the gate is formed on the first insulating layer. Forming a second insulating layer on the first insulating layer and the oxide channel, wherein the second insulating layer includes an etch blocking pattern over the oxide channel and an isolation pattern over the linear transmission portion, and the isolation pattern contacts the first insulating layer . The patterned second conductive layer forms a source, a drain, an over-line transmission portion and a capacitor electrode over the second insulating layer, and the drain electrode is located on both sides of the oxide channel, and the cross-line transmission portion spans the scan line, and the capacitor The electrode is disposed on the isolation pattern and above the linear transmission portion. A first pixel electrode is formed on the substrate and connected to the drain.

Based on the above, the pixel structure of the present invention and the method of fabricating the same, by patterning the first conductive layer to form the linear transmission portion, the scan line and the gate of the data line in the same layer, and to be located above the channel of the active device A second insulating layer as an etch barrier is further disposed on the linear transmission portion of the data line. At this time, when the capacitor electrode made of the second conductive layer is overlapped with the linear transmission portion of the data line, a plurality of insulating layers are disposed between the linear transmission portion of the data line and the capacitor electrode. In this way, not only the etching barrier pattern defined by the second insulating layer can be used to protect the channel, but also the second insulating layer can reduce the capacitive coupling effect between the data line and the capacitor electrode, thereby reducing the power consumption of the pixel electrode. .

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

Fig. 1A is a top plan view showing a pixel structure of a first embodiment of the present invention, and Fig. 1B is a cross-sectional view of the pixel structure of Fig. 1A taken along section lines I-I' and II-II'. Referring to FIG. 1A and FIG. 1B , the pixel structure 10 a of the embodiment includes a substrate 100 , a scan line 111 , a data line 112 , a first insulating layer 120 , an active device 130 , a second insulating layer 140 , a capacitor electrode 150 , and a first A pixel electrode 170. The active device includes a gate 131, an oxide semiconductor layer (or oxide channel) 133, a source 135, and a drain 137.

In detail, the scanning line 111 is disposed on the substrate 100. The data line 112 is disposed on the substrate 100, the scan line 111 is interleaved with the data line 112, and the data line 112 includes a linear transmission portion 112a and an overhead transmission portion 112b that are connected to each other, wherein the overhead transmission portion 112b spans the scan line 111. The first insulating layer 120 covers the scanning line 111 and the linear transmission portion 112a of the data line 112, and is located between the scanning line 111 and the overhead transmission portion 112b. The active component 130 is connected to the scan line 111 and the data line 112. The gate 131 is connected to the scanning line 111. The oxide channel 133 is located above the gate 131, and the first insulating layer 120 is located between the gate 131 and the oxide channel 133. The source 135 is connected to the jumper transmission portion 112b of the data line 112. The source 135 and the drain 137 are located on both sides of the oxide channel 133. The second insulating layer 140 includes an etch barrier pattern 141 over the oxide via 133 and an isolation pattern 142 over the linear transfer portion 112a, and the isolation pattern 142 is in contact with the first insulating layer 120. The capacitor electrode 150 is disposed on the isolation pattern 142 and above the linear transmission portion 112a. The first pixel electrode 170 is connected to the drain 137.

The following are the steps of the manufacturing method of the pixel structure 10a. 2A-9A are schematic top views showing the steps of the manufacturing method of the pixel structure 10a, and Figs. 2B-9B are cross-sectional views of the cross-sectional lines I-I' and II-II' of Figs. 2A-9A. First, a first conductive layer (not shown) is formed on the substrate 100, and by a photomask process (which includes lithography and etching steps, but not limited thereto, it may also include a laser stripping process) The first conductive layer is patterned to form the scanning line 111, the gate 131, and the linear transmission portion 112a of the data line 112, as shown in FIGS. 2A and 2B. However, the scanning line 111, the gate 131, and the linear transmission portion 112a of the data line 112 may be selectively formed on the substrate 100 by printing or by inkjet.

In an embodiment, the substrate 100 may be made of glass, quartz, an organic polymer, or a flexible material to carry the pixel structure 10a and provide good light transmittance. However, the substrate 100 can also be selectively made of an opaque material. The gate 131 is connected to the scanning line 111, and the linear transmission portion 112a and the scanning line 111 are separated from each other, wherein the extending direction of the scanning line 111 is staggered with the extending direction of the linear transmission portion 112a. The material of the first conductive layer (not shown) of this embodiment may include a metal material or alloy such as molybdenum (Mo), aluminum (Al), titanium (Ti), silver, gold, copper or the like or other conductive materials; The first conductive layer is not limited to a single layer, and may be composed of two or more layers of different metals, alloys, and other conductive materials.

Referring to FIGS. 3A and 3B, the first insulating layer 120 is formed on the substrate 100, and the first insulating layer 120 covers the scan line 111, the gate 131, and the linear transfer portion 112a. The first insulating layer 120 is formed by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable thin film deposition techniques, and the first insulating layer 120 is formed. It may be a single layer or a multilayer structure, and the material thereof is, for example, a dielectric material such as ruthenium oxide, tantalum nitride or ruthenium oxynitride, or a mixture of a plurality of layers of different dielectric materials. Of course, in other embodiments, the material of the first insulating layer 120 also includes an organic material prepared by a yellow light developing method, a printing method, or an ink jet method, and a multilayer stacked structure of an inorganic material and an organic material may also be utilized.

Referring to FIGS. 4A and 4B, on the first insulating layer 120, an oxide channel 133 is formed over the gate 131. In detail, a single layer or a multilayer structure of an oxide semiconductor material layer (not shown) is first formed on the first insulating layer 120, and the material thereof is, for example, indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO). ), indium gallium oxide (IGO), tin oxide (ZnO), cadmium oxide, cerium oxide (2CdO‧GeO2) or nickel cobalt oxide (NiCo2O4). The layer of oxide semiconductor material is then patterned into oxide channels 133 by a mask process or other patterning process. Of course, in other embodiments, the material of the oxide channel 133 also includes an organic material prepared by a yellow light developing method, a printing method, or an ink jet method, and a multilayer stack structure of an inorganic material and an organic material may also be utilized.

Referring to FIGS. 5A and 5B, a second insulating layer 140 is formed on the first insulating layer 120 and the oxide channel 133. The second insulating layer 140 includes an etch barrier pattern 141 and an isolation pattern 142, wherein the etch barrier pattern 141 is located above the oxide channel 133 to protect the oxide channel 133 and provide an etching stop effect. The outline of the etch barrier pattern 141 is, for example, a rectangle, but the invention is not limited thereto, and may be polygonal or curved. The isolation pattern 142 is located above the linear transmission portion 112a, and the isolation pattern 142 is in contact with the first insulating layer 120. In addition, the second insulating layer 140 of the embodiment may be a single layer or a multi-layer structure, and the material thereof is, for example, a dielectric material such as hafnium oxide, tantalum nitride or hafnium oxynitride, or may be composed of a plurality of layers of different dielectric materials. . In other embodiments, the second insulating layer 140 may use the method of fabricating the first insulating layer 120 and the materials it contains.

Referring to FIG. 6A and FIG. 6B, the first opening H1 and the second opening H2 are respectively formed in the first insulating layer 120 and the second insulating layer 140 by the mask process to form contacts exposing the opposite ends of the linear transmission portion 112a, respectively. The opening H is for electrically connecting the subsequently formed crossover transmission portion 112b to the linear transmission portion 112a. In the present embodiment, the first opening H1 and the second opening H1 that communicate with each other can be fabricated using the same mask process or using different mask processes.

Next, a second conductive layer (not shown) is formed over the second insulating layer 140, and the second conductive layer is patterned by a mask process to form the source electrode 135, the drain 137, and the jumper transmission portion 112b. And the capacitor electrode 150 is on the second insulating layer 140 as shown in FIGS. 7A and 7B, that is, the above elements are separated from each other. The material of the second conductive layer is, for example, a metal material or alloy such as aluminum (Al), molybdenum (Mo), titanium (Ti), or niobium (Nd) or other conductive material, and is not limited to a single layer, and may be composed of a plurality of layers or a plurality of conductive materials. composition. However, the source electrode 135, the drain electrode 137, the over-line transmission portion 112b, and the capacitor electrode 150 may be selectively formed on the second insulating layer 140 by printing or by inkjet.

In this embodiment, the source 135 and the drain 137 are located on both sides of the oxide channel 133 to form the active device 130 together with the gate 131, that is, the active device 130 is composed of the gate 131, the oxide channel 133, and the source. The structure of the pole 135 and the drain 137. It is worth mentioning that the oxide channel 133 is covered with an etch barrier pattern 141, so that the etchant/solvent used to pattern the second conductive layer does not contact the oxide channel 133 between the source 135 and the drain 137. In part, damage to the oxide channel 133 can be avoided. As such, the oxide channel 133 can have desirable component characteristics.

Further, the overhead transmission portion 112b straddles the scanning line 111 and is connected to the linear transmission portion 112a of the data line 112 through the contact opening H to transmit the signal via the data line 112. That is, the data line 112 is a continuous transmission path composed of different layers of conductive layers, which are interlaced with the scanning lines 111 without being in communication with the scanning lines 111. The capacitor electrode 150 is disposed on the isolation pattern 142 and is located above the linear transmission portion 112a. Further, the capacitor electrode 150 has a first portion 151 and a second portion 152 that are connected to each other, the first portion 151 substantially shielding the linear transmission portion 112a, and the extending direction of the second portion 152 is staggered in the extending direction of the first portion 151. Preferably, the width of the first portion 151 is substantially larger than the line width of the linear transmission portion 112a to completely shield the linear transmission portion 112a. The first portion 151 is in contact with the isolation pattern 142 of the second insulating layer 140, but is not limited thereto.

That is, at least the isolation pattern 142 of the first insulating layer 120 and the second insulating layer 140 is disposed between the first portion 151 of the capacitor electrode 150 and the linear transmission portion 112a of the data line 112. As a result, the capacitive coupling effect between the first portion 151 of the capacitor electrode 150 and the linear transmission portion 112a of the data line 112 is lowered by the presence of at least two insulating layers. That is, the parasitic capacitance between the first portion 151 of the capacitor electrode 150 and the linear transmission portion 112a of the data line 112 is significantly reduced, which is advantageous for reducing the load of the capacitor electrode 150 and the data line 112.

Referring to FIG. 8A and FIG. 8B , the third insulating layer 160 is covered on the substrate 100 , that is, the third insulating layer 160 covers the active device 130 and the capacitor electrode 150 , and the third opening p is formed in the third insulating layer 160 . The third insulating layer 160 may be a single layer or a multilayer structure, and the material thereof is, for example, tantalum nitride or tantalum oxide, and the method of forming the same is, for example, comprehensively deposited on the substrate by physical vapor deposition or chemical vapor deposition. At 100, a third opening p is formed in the third insulating layer 160, for example, by a patterning method such as a photolithography process. In other embodiments, the third insulating layer 160 may use the method of fabricating the first insulating layer 120 and the materials it contains.

Referring again to FIGS. 1A and 1B , the first pixel electrode 170 is formed on the substrate 100 and the first pixel electrode 170 is connected to the drain 137 . In detail, the first pixel electrode 170 is substantially located on the third insulating layer 160 and away from the side of the capacitor electrode 150, wherein the first pixel electrode 170 is electrically connected through the third opening p in the third insulating layer 160. Bungee 137. In addition, the first portion 151 of the capacitor electrode 150 substantially surrounds the edge of the first pixel electrode 170. Therefore, the capacitor electrode 150 partially overlaps the first pixel electrode 170 to form a storage capacitor, which can reduce the storage capacitor area and increase the aperture ratio. .

In the pixel structure 10a of the present embodiment, since the partial data line 112, that is, the linear transmission portion 112a of the data line 112, is disposed in the same layer as the gate 131, and the linear transmission portion 112a of the data line 112 and the capacitor electrode 150 is separated by one or more insulating layers, that is, the isolation pattern 142 of the first insulating layer 120 and the second insulating layer 140, so that not only the etching stopper pattern 141 can be formed on the oxide channel 133, but also can be reduced. The size of the capacitance between the data line 112 and the capacitor electrode 150. When the pixel structure 10a is applied to a display device, the power consumption of the display device and the display effect can be reduced. In addition, in this embodiment, since the first portion 151 of the capacitor electrode 150 is disposed between the pixel electrode 170 and the linear transmission portion 112a of the data line 112, the pixel electrode 170 and the linear transmission portion 112a of the data line 112 are not easily coupled. effect. Therefore, the pixel electrode 170 can cover the linear transmission portion 112a of the data line 112 to increase the display aperture ratio of the pixel structure 10a. When the pixel structure 10a is applied to a display device, power consumption of the display device can be reduced and brightness can be increased.

The design of the pixel structures 10b-10d will be described below in different implementations. It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

Second embodiment

Fig. 9A is a top plan view showing a pixel structure of a second embodiment of the present invention, and Fig. 9B is a cross-sectional view of the pixel structure of Fig. 9A taken along line III-III' and IV-IV'. Referring to FIG. 9A and FIG. 9B simultaneously, the pixel structure 10b of the present embodiment is similar to the pixel structure 10a of the above embodiment, and the difference is that the pixel structure 10b of the present embodiment further extends the second insulating layer 240. Formed between the first insulating layer 120 and the pixel electrode 170.

In detail, in the pixel structure 10b, the scanning line 111, the gate 131, the linear transmission portion 112a of the data line 112, the first insulating layer 120, and the oxide channel 133 can be referred to FIG. 2A in the first embodiment. 2B to the description of FIGS. 4A-4B without further elaboration. Further, after the above-described members are fabricated, as shown in FIGS. 10A and 10B, a second insulating layer 240 is formed on the first insulating layer 120 and the oxide channel 133, and the first insulating layer 120 is processed by the mask process. The second insulating layer 240 forms a plurality of openings H1, H2, H3, and H4. Specifically, the first insulating layer 120 and the second insulating layer 240 are respectively formed with a first opening H1 and a second opening H2 to form contact openings H exposing opposite ends of the linear transmission portion 112a, respectively. In addition, both the opening H3 and the opening H4 expose the oxide channels 133 and are respectively located on both sides of the gate 131. At this time, the second insulating layer 240 includes, for example, an etch barrier pattern 241 corresponding to the gate 131 and covering the oxide channel 133 and an isolation pattern 242 overlying the first insulating layer 120.

The difference between the pixel structure 10b of the present embodiment and the pixel structure 10a of the first embodiment is mainly that the photomasks used for patterning the second insulating layer 240 have different pattern layouts. Therefore, in the present embodiment, the second insulating layer 240 is only partially removed corresponding to the openings H1, H2, H3, H4, and the isolation pattern 242 covers most of the first insulating layer 120. In contrast, the isolation pattern 142 in the pixel structure 10a substantially corresponds to only the area of the linear transmission portion 112a. In addition, the shape of the opening H3 and the opening H4 is merely exemplarily illustrated in the present embodiment, and is not particularly limited to a rectangular shape, and may be other polygonal or curved shapes. In other embodiments, any opening design that exposes the locations of the oxide channels 133 that are intended to be in contact with the source and drain electrodes is applicable to the present invention and is encompassed within the scope of the present invention.

Next, as shown in FIGS. 11A and 11B, a patterned second conductive layer is formed over the second insulating layer 240 to form a source electrode 135, a drain 137, a jumper transmission portion 112b, and a capacitor electrode 150. At this time, the source 135 and the drain 137 are connected to the oxide channel 133 through the opening H3 and the opening H4 of the second insulating layer 240, and the jumper transmission portion 112b is transmitted through the first opening H1 and the second of the first insulating layer. The contact opening H formed by the second opening H2 of the insulating layer 240 is connected to the linear transmission portion 112a.

In the subsequent steps, the third insulating layer 160 may be formed on the active device 130 and the capacitor electrode 150, and the third insulating layer 160 has a third opening p, as shown in FIG. 12A and FIG. 12B. Shown. Then, the first pixel electrode 170 is formed on the substrate 100, that is, the first pixel electrode 170 is formed on the third insulating layer 160, so that the first pixel electrode 170 is connected to the drain electrode 137 via the third opening p, such as 9A and 9B are shown. In this embodiment, openings H1, H2, H3, and H4 may be formed in the first insulating layer 120 and the second insulating layer 140 by using a half-tone mask to form the openings in the first insulating layer 120 and the second insulating layer 140. Reduce manufacturing costs and simplify process steps by reducing the number of reticle uses.

Third embodiment

Fig. 13A is a top plan view showing a pixel structure of a third embodiment of the present invention, and Fig. 13B is a cross-sectional view of the pixel structure of Fig. 13A taken along line lines V-V' and VI-VI'. Referring to FIG. 13A and FIG. 13B simultaneously, the pixel structure 10c of the present embodiment is similar to the pixel structure 10a of the first embodiment, and the manufacturing method thereof can be referred to the description of FIGS. 1A-7A to 1B-7B. However, the pixel structure 10c of the present embodiment is different from the pixel structure 10a in that a second conductive layer is patterned over the second insulating layer 140 to form a source electrode 135, a drain 137, a jumper transmission portion 112b, and a capacitor. After the electrode 150, referring to FIG. 14A and FIG. 14B, the first pixel electrode 370 is formed on the substrate 100, and the first pixel electrode 370 is connected to the drain electrode 137.

Next, as shown in FIG. 15A and FIG. 15B, the third insulating layer 160 is overlaid on the substrate 100, that is, the third insulating layer 160 is covered on the active device 130, the capacitor electrode 150, the over-line transmission portion 112b, and the first drawing. On the element electrode 370, a third opening q is formed in the third insulating layer 160, and the third opening q exposes a portion of the capacitor electrode 150. Preferably, the third opening q is exposed to the linear transmission portion of the data line 112. A portion of the capacitor electrode 150 above 112a.

Finally, as shown in FIG. 13A and FIG. 13B, the second pixel electrode 380 is formed on the third insulating layer 160, in other words, the first pixel electrode 370 and the second pixel electrode 380 are respectively located on the third insulating layer 160. On both sides. The second pixel electrode 380 may be over the capacitor electrode 150 and electrically connected to the capacitor electrode 150 through the third opening q.

Further, the first pixel electrode 370 and the second pixel electrode 380 are patterned, for example, such that the first pixel electrode 370 has a substantially finger pattern (not labeled) and the second pixel electrode 380 is provided with, for example, a plurality of openings. (not marked). At this time, the area of the first pixel electrode 370 on the substrate 100 is partially exposed by the area of the second pixel electrode 380 on the substrate 100 to provide a fringe electric field effect. Therefore, the pixel structure 10c of the present embodiment can be applied to, for example, a fringe electric field conversion mode (FFS) pixel design. However, the present invention does not particularly limit the pattern design and shape of the first pixel electrode 370 and the second pixel electrode 380. The above-mentioned finger patterns and shapes are for illustrative purposes only and are not intended to limit the scope of the present invention.

Fourth embodiment

Fig. 16A is a top plan view showing a pixel structure of a fourth embodiment of the present invention, and Fig. 16B is a cross-sectional view of the pixel structure of Fig. 16A taken along section lines VII-VII' and VIII-VIII'. Referring to FIG. 16A and FIG. 16B simultaneously, the pixel structure 10d of the present embodiment is similar to the pixel structure 10c of the third embodiment, and the manufacturing method thereof can be referred to FIG. 1A-7A to FIG. 1B-7B and FIG. 14A-15A to FIG. 14B-15B. However, the pixel structure 10d of the present embodiment is different from the pixel structure 10c in that a second conductive layer is patterned over the second insulating layer 140 to form a source electrode 135, a drain 137, a jumper transmission portion 112b, and a capacitor. After the electrode 150, referring to FIG. 16A and FIG. 16B, the first pixel electrode 370 and the auxiliary electrode 471 are simultaneously formed on the substrate 100, and wherein the auxiliary electrode 471 and the first pixel electrode 370 are separated from each other, that is, the auxiliary electrode 471 is the same film layer as the first pixel electrode 370, but is not connected to each other. In detail, the first pixel electrode 370 is connected to the drain electrode 137, and the auxiliary electrode 471 directly covers and contacts the capacitor electrode 150 and is electrically connected to the capacitor electrode 150. The design pattern of the auxiliary electrode 471 is not limited to the present invention. The description of the manufacturing method of the third insulating layer 160 to the second pixel electrode 380 and the fringe electric field provided by the first pixel electrode 370 and the second pixel electrode 380 can be referred to the third embodiment and will not be described again.

In summary, the pixel structure of the present invention and the method of fabricating the same, by patterning the first conductive layer to form the linear transmission portion, the scan line and the gate arrangement of the data line in the same layer, and by the data line The overhead transmission portion is electrically connected to the linear transmission portion of the data line across the scan line. A first insulating layer is formed on the linear transmission portion of the data line, the scan line and the gate, and a second insulating layer is disposed to respectively provide an etch barrier pattern and an isolation pattern over the oxide channel and the linear transfer portion. In addition, the capacitor electrode is disposed on the second insulating layer, and finally the pixel electrode is overlaid on the capacitor electrode. Therefore, in the pixel structure of the present invention and the method of fabricating the same, the plurality of insulating layers (including the first insulating layer and the second insulating layer) may be spaced apart between the linear transmission portion of the data line and the capacitor electrode. In this way, not only an etch barrier pattern can be formed to protect the oxide channel, but also the parasitic capacitance between the data line and the capacitor electrode can be reduced, thereby reducing the power consumption of the pixel structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10a, 10b, 10c, 10d. . . Pixel structure

100. . . Substrate

111. . . Scanning line

112. . . Data line

112a. . . Linear transmission

112b. . . Cross-line transmission

120. . . First insulating layer

130. . . Active component

131. . . Gate

133. . . Oxide channel

135. . . Source

137. . . Bungee

140, 240. . . Second insulating layer

141. . . Etch blocking pattern

142. . . Isolation pattern

150. . . Capacitor electrode

151. . . First

152. . . Second part

160. . . Third insulating layer

170,370. . . First pixel electrode

180,380. . . Second pixel electrode

471. . . Auxiliary electrode

H1, H2, H3, H4, H, p, q. . . Opening

I-I', II-II, III-III', IV-IV', V-V', VI-VI', VII-VII', VIII-VIII'. . . Section line

Fig. 1A is a top plan view showing a pixel structure of a first embodiment of the present invention.

Figure 1B is a cross-sectional view of the pixel structure of Figure 1A taken along section lines I-I' and II-II'.

Fig. 2A is a top plan view showing the pixel structure of the first embodiment of the present invention.

2A and 2B are cross-sectional views of the cross-sectional lines I-I' and II-II'.

Fig. 3A is a top plan view showing the pixel structure of the first embodiment of the present invention.

3A and 3B are cross-sectional views of the cross-sectional lines I-I' and II-II'.

4A is a top plan view showing a pixel structure of a first embodiment of the present invention.

4A and 4B are cross-sectional views of the cross-sectional lines I-I' and II-II'.

Fig. 5A is a top plan view showing the pixel structure of the first embodiment of the present invention.

The cross-sectional views of the pixel structures of Figs. 5A and 5B are taken along section lines I-I' and II-II'.

Fig. 6A is a top plan view showing the pixel structure of the first embodiment of the present invention.

The cross-sectional views of the pixel structures of Figs. 6A and 6B are taken along section lines I-I' and II-II'.

Fig. 7A is a top plan view showing the pixel structure of the first embodiment of the present invention.

The cross-sectional views of the pixel structures of Figs. 7A and 7B are taken along section lines I-I' and II-II'.

Fig. 8A is a top plan view showing the pixel structure of the first embodiment of the present invention.

The cross-sectional views of the pixel structures of Figs. 8A and 8B are taken along section lines I-I' and II-II'.

Fig. 9A is a top plan view showing a pixel structure of a second embodiment of the present invention.

The cross-sectional views of the pixel structures of Figs. 9A and 9B are taken along section lines III-III' and IV-IV'.

Fig. 10A is a top plan view showing a pixel structure of a second embodiment of the present invention.

Figure 10B is a cross-sectional view of the pixel structure of Figure 10A taken along section lines III-III' and IV-IV'.

Figure 11A is a top plan view showing a pixel structure of a second embodiment of the present invention.

Figure 11B is a cross-sectional view of the pixel structure of Figure 11A taken along section lines III-III' and IV-IV'.

Figure 12A is a top plan view showing a pixel structure of a second embodiment of the present invention.

Figure 12B is a cross-sectional view of the pixel structure of Figure 12A taken along section lines III-III' and IV-IV'.

Figure 13A is a top plan view showing a pixel structure of a third embodiment of the present invention.

Figure 13B is a cross-sectional view of the pixel structure of Figure 13A taken along section lines V-V' and VI-VI'.

Fig. 14A is a top plan view showing a pixel structure of a third embodiment of the present invention.

Figure 14B is a cross-sectional view of the pixel structure of Figure 14A taken along section lines V-V' and VI-VI'.

Figure 15A is a top plan view showing a pixel structure of a third embodiment of the present invention.

Figure 15B is a cross-sectional view of the pixel structure of Figure 15A taken along section lines V-V' and VI-VI'.

Figure 16A is a top plan view showing a pixel structure of a fourth embodiment of the present invention.

Figure 16B is a cross-sectional view of the pixel structure of Figure 16A taken along section lines VII-VII' and VIII-VIII'.

10a. . . Pixel structure

100. . . Substrate

112. . . Data line

112a. . . Linear transmission

112b. . . Cross-line transmission

120. . . First insulating layer

130. . . Active component

131. . . Gate

133. . . Oxide channel

135. . . Source

137. . . Bungee

140. . . Second insulation

141. . . Etch blocking pattern

142. . . Isolation pattern

150. . . Capacitor electrode

160. . . Third insulating layer

170. . . First pixel electrode

H1, H2, H, p. . . Opening

I-I’, II-II’. . . Section line

Claims (22)

A pixel structure includes: a substrate; a scan line disposed on the substrate; a data line disposed on the substrate, the scan line is interlaced with the data line, and the data line includes a linear line connected to each other a transmission portion and a jumper transmission portion, wherein the jumper transmission portion spans the scan line; a first insulating layer covering the scan line and the linear transfer portion and located between the scan line and the jumper transfer portion; An active component is connected to the scan line and the data line, wherein the active component comprises: a gate connected to the scan line; an oxide channel located above the gate, and the first insulating layer is located at the gate Between the oxide channel and the oxide channel; a source connected to the line transmission portion of the data line; a drain, the source and the drain are located on opposite sides of the oxide channel; and a second insulating layer, including An etch stop pattern over the oxide channel and an isolation pattern over the linear transfer portion, and the isolation pattern contacts the first insulating layer; a capacitor electrode disposed on the isolation pattern and located at the The upper portion of the transmission; and a first pixel electrode connected to the drain; an auxiliary electrode directly covers the electrode and the capacitor electrode and the auxiliary The first pixel electrode is the same film layer. The pixel structure of claim 1, wherein the first insulating layer and the second insulating layer respectively have a first opening and a second opening to form a contact opening exposing the linear transmission portion. The jumper transmission portion is connected to the linear transmission portion through the contact opening. The pixel structure of claim 1, wherein the capacitor electrode has a first portion and at least a second portion connected to each other, the first portion at least partially shielding the linear transmission portion, and the second portion The extending direction is not parallel to the extending direction of the first portion. The pixel structure of claim 3, wherein the first portion and the second portion surround an edge of the first pixel electrode. The pixel structure of claim 3, wherein the first pixel electrode shields the second portion and the first portion is located at an edge of the first pixel electrode. The pixel structure of claim 3, wherein the width of the first portion is greater than the line width of the linear transmission portion to completely shield the linear transmission portion. The pixel structure of claim 3, wherein the first portion is in contact with the isolation pattern of the second insulating layer. The pixel structure of claim 1, further comprising a third insulating layer covering the active device and the capacitor electrode. The pixel structure of claim 8, wherein the first pixel electrode is substantially located on a side of the third insulating layer away from the capacitor electrode, and the third insulating layer has a third opening First pixel electrode The drain is electrically connected through the third opening. The pixel structure of claim 8, further comprising a second pixel electrode disposed on the third insulating layer and covering the capacitor electrode, the third insulating layer having at least a third opening The second pixel electrode is electrically connected to the capacitor electrode through the third opening, and an area of the first pixel electrode on the substrate is partially exposed by an area of the second pixel electrode on the substrate. To provide a fringe electric field. The pixel structure of claim 10, wherein the first pixel electrode and the second pixel electrode are respectively located on opposite sides of the third insulating layer. The pixel structure of claim 1, wherein the isolation pattern is located between the first pixel electrode and the first insulating layer. A method for fabricating a pixel structure includes: patterning a first conductive layer to form a scan line, a gate, and a linear transfer portion on a substrate, the gate is connected to the scan line, and the linear transfer portion and the The scanning lines are separated from each other, wherein an extending direction of the scanning lines is staggered with an extending direction of the linear transmission portion; a first insulating layer is formed on the substrate to cover the scan lines, the gates, and the linear transmission portion; Forming an oxide channel over the gate on the first insulating layer; forming a second insulating layer on the first insulating layer and the oxide channel, wherein the second insulating layer comprises a top of the oxide channel An etch barrier pattern and an isolation pattern above the linear transmission portion, And the isolation pattern contacts the first insulating layer; the patterned second conductive layer forms a source, a drain, a jumper transmission portion and a capacitor electrode over the second insulating layer, the source and the a drain electrode is located at two sides of the oxide channel, the jumper transmission portion spans the scan line, the capacitor electrode is disposed on the isolation pattern and located above the linear transmission portion, and a first pixel is formed on the substrate An electrode connected to the drain electrode; forming an auxiliary electrode while forming the first pixel electrode, wherein the auxiliary electrode directly covers the capacitor electrode. The method for manufacturing a pixel structure according to claim 13 , further comprising forming a first opening and a second opening on the first insulating layer and the second insulating layer to form a linearity a contact opening of the transmission portion, the jumper transmission portion being connected to the linear transmission portion through the contact opening. The method of fabricating a pixel structure according to claim 14, wherein the first opening and the second opening are fabricated using the same mask process. The method for fabricating a pixel structure according to claim 14, further comprising forming, on the second insulating layer, two openings exposing the oxide channel, the source and the drain transmitting the oxide The two openings of the channel are connected to the oxide channel, wherein the second opening and the two openings exposing the oxide channel are fabricated using the same reticle process. The method for fabricating a pixel structure according to claim 14, further comprising forming a third insulating layer to cover the source and the drain And the capacitor electrode. The method for manufacturing a pixel structure according to claim 17, wherein the first pixel electrode is formed after the third insulating layer, and the third insulating layer is further included in the third insulating layer. The layer forms a third opening to electrically connect the first pixel electrode to the drain through the third opening. The method for manufacturing a pixel structure according to claim 17, further comprising forming a second pixel electrode on the third insulating layer, the second pixel electrode covering the capacitor electrode and electrically connecting The capacitor electrode, and an area of the first pixel electrode on the substrate is partially exposed by an area of the second pixel electrode on the substrate to provide a fringe electric field, wherein the first pixel electrode is located at the first The three insulating layers are away from one side of the second pixel electrode. The method for fabricating a pixel structure according to claim 19, wherein the method for fabricating the third insulating layer further comprises: forming a third opening in the third insulating layer to pass the second pixel electrode through the third The opening is electrically connected to the capacitor electrode. The method of fabricating a pixel structure according to claim 20, wherein the first opening, the second opening, and the third opening are fabricated using the same mask process. The method of fabricating a pixel structure according to claim 21, wherein the first opening, the second opening, and the third opening are fabricated using different mask processes.