KR102090600B1 - TFT array substrate and manufacturing methods therefor - Google Patents

Abstract

In one embodiment of the present invention, in a method of manufacturing a thin film transistor array substrate including a data line formed of a two-layer structure of a semiconductor layer and a metal layer using a plurality of mask processes, the data line includes: (a) a semiconductor layer and a metal layer Sequentially forming a stack, (b) forming a photoresist having a wing pattern on the metal layer, wet etching the metal layer as a barrier, and (c) a semiconductor layer exposed by the step (b) Disclosed is a method of manufacturing a thin film transistor array substrate including dry etching.

Description

Manufacturing method of thin film transistor array substrate {TFT array substrate and manufacturing methods therefor}

The present invention relates to a method of manufacturing a thin film transistor array substrate with reduced active tail phenomenon occurring during data line formation.

A liquid crystal display device is a device that actively inputs data to pixels arranged in a matrix form and controls a light transmittance of each pixel to display a desired image. The liquid crystal display panel constituting the device is configured to control the arrangement direction of the liquid crystal by sandwiching the liquid crystal between the two electrodes to control the light transmittance.

The liquid crystal display panel includes a color filter substrate and a thin film transistor array substrate. The color filter substrate is disposed above the thin film transistor array substrate based on the direction of light travel, and a color filter is formed to display the three primary colors. The thin film transistor array substrate includes a thin film transistor that selectively inputs data input to each pixel, and gate lines, data lines, and pixel electrodes required to drive each pixel.

Meanwhile, the thin film transistor includes a source electrode, a drain electrode, and a gate electrode, and includes a semiconductor layer that selectively connects the source electrode and the drain electrode according to a signal input to the gate electrode.

However, a data line for inputting a data signal through a thin film transistor to each pixel is formed simultaneously with a source electrode and a drain electrode. For this reason, the data line is formed in a two-layer structure of a semiconductor layer and a metal layer.

However, the etching ratio of the semiconductor layer and the metal layer is different, and due to the diffraction phenomenon of light in the process of exposure, an active tail phenomenon in which the line width of the semiconductor layer is formed thicker than that of the metal layer during data line formation occurs.

However, if a liquid crystal display panel is developed in the trend of high definition as now, there is a problem in realizing high definition due to the active tail.

The present invention was created in such a background, and is intended to reduce an active tail phenomenon when forming a data line so that a data line having a fine line width can be formed.

In one embodiment of the present invention, in a method of manufacturing a thin film transistor array substrate including a data line formed of a two-layer structure of a semiconductor layer and a metal layer using a plurality of mask processes, the data line includes: (a) a semiconductor layer and a metal layer Sequentially forming a stack, (b) forming a photoresist having a wing pattern on the metal layer, wet etching the metal layer as a barrier, and (c) a semiconductor layer exposed by the step (b) Disclosed is a method of manufacturing a thin film transistor array substrate including dry etching.

In the step (c), the semiconductor layer is dry-etched to undercut the semiconductor layer, and the end of the metal layer exposed by the dry etching is wet-etched to form a step in the order of the metal layer and the semiconductor layer. Further comprising steps.

In one embodiment of the present invention, the data line in the thin film transistor substrate may be formed using a wing pattern, thereby reducing the active tail to form a fine pattern data line.

1 is a plan view showing a thin film transistor array substrate according to an embodiment of the present invention,
Figure 2 is a cross-sectional view taken along line II of Figure 1,
3 is a plan view illustrating a first mask process in a manufacturing method according to an embodiment of the present invention,
4 is a cross-sectional view taken along line II of FIG. 1,
5 is a plan view illustrating a second mask process in the manufacturing method according to an embodiment of the present invention,
6 is a cross-sectional view taken along line II of FIG. 5,
7A to 7C are views showing a photoresist pattern used in the second mask process,
8 is a view showing a plan view of a photoresist including a wing pattern,
9 is a view for explaining a process of forming a data line by a photoresist pattern including the wing pattern illustrated in FIG. 8,
10 is a plan view illustrating a third mask process in a manufacturing method according to an embodiment of the present invention,
11 is a cross-sectional view taken along line II of FIG. 10,
12 is a plan view illustrating a fourth mask process in a manufacturing method according to an embodiment of the present invention,
13 is a cross-sectional view taken along line II of FIG. 12.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description is omitted.

1 and 2 are diagrams showing a thin film transistor array substrate according to an embodiment of the present invention. Of these, FIG. 1 is a plan view, and FIG. 2 is a cross-sectional view taken along line I-I of FIG. 1.

1 and 2, the thin film transistor array substrate of the present embodiment intersects the gate insulating layer 136 on the substrate 145 with the gate line 102 and the data line 104 intersecting the pixel region defining the pixel region. It includes a thin film transistor (TFT) formed for each part, a pixel electrode 114 formed in the pixel area, a light blocking film (BLSP) for preventing light leakage in the pixel area, and a storage capacitor (Cst).

The thin film transistor (TFT) forms a channel between the source electrode 110 and the drain electrode 112 in response to a gate signal input through the two-layered gate line 102 to form data input through the data line 104. The signal is supplied to the pixel electrode 114. The thin film transistor (TFT) faces the gate electrode 108 connected to the gate line 102, the source electrode 110 connected to the data line 104, and the source electrode 110, and the drain connected to the pixel electrode 114 A semiconductor layer 154 is provided to form a channel between the source electrode 110 and the drain electrode 112 by overlapping the gate electrode 108 with the electrode 112 and the gate insulating film 136 therebetween. The semiconductor layer 154 includes an active layer 148 forming a channel between the source electrode 110 and the drain electrode 112, and an active layer excluding the channel portion for resistive contact with the small electrode 110 and the drain electrode 112. A resistive contact layer 150 formed on the surface 148 is provided.

The pixel electrode 114 is formed as a transparent electrode directly on the substrate 145 in the pixel region defined by the data line 104 and the gate line 102. The pixel electrode 114 is connected to the drain electrode 112 of the thin film transistor (TFT) and the pixel link electrode LK1 to receive a data signal transmitted through the data line 104. The pixel link electrode LK1 connects the pixel electrode 114 and the drain electrode 112 exposed through the first and second contact holes CH1 and CH2.

The storage capacitor Cst is formed by overlapping an end portion of the pixel electrode 114 and a light blocking film BLSP with a gate insulating film 136 and a protective film 152 as dielectric materials interposed therebetween. The storage capacitor Cst charges a voltage corresponding to a difference between a reference voltage applied to the light-shielding film BLSP and a data voltage applied to the pixel electrode 114, and then stores the data voltage input to the pixel electrode 114 to the next data. It remains stable until a voltage is input.

The light-shielding film BLSP is formed between the pixel electrode 114 in the pixel area, the data lines 104 disposed on the left and right sides of the pixel electrode 114, and the pixel electrode 114 and the gate line 102 disposed on the upper side. Located at, prevents light leakage from occurring in the pixel area. The light blocking film BLSP is connected to the light blocking film BLSP of a neighboring pixel in the vertical direction through the connection link 160, and is also connected to the light blocking film BLSP of a neighboring pixel in the horizontal direction. A predetermined voltage, for example, a common voltage Vcom is transmitted to the light blocking film BLSP equally to all pixels, thereby forming a reference voltage of the storage capacitor Cst.

Hereinafter, a manufacturing process of a thin film transistor array substrate according to an embodiment of the present invention configured as described above will be described. 3 is a plan view illustrating the first mask process, and FIG. 4 is a cross-sectional view taken along line I-I of FIG. 3.

The first mask process is a step of forming a two-layer gate metal pattern including a pixel electrode 114, a gate line 102, and a gate electrode 108 of a transparent electrode on the substrate 145. In the first mask process, the pixel electrode 114 and the gate metal pattern are formed together using a halftone mask or a diffraction exposure mask. Here, the pixel electrode 114 is made of a transparent conductive material such as ITO, TO, IZO, ITZO, and the gate metal is a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, etc. Made of this single layer, Al / Cr, Al / Mo, Al (Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti , Mo / Al, Mo / Ti / Al (Nd), Cu alloy / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al alloy / Mo It consists of a structure in which two or more layers of metallic materials such as alloy, Mo alloy / Al alloy, and Mo / Al alloy are stacked.

5 is a plan view illustrating the second mask process, and FIG. 6 is a cross-sectional view taken along line I-I of FIG. 5.

The second mask process is a step of forming a source / drain metal pattern including a gate insulating layer 136, a data line 104, a source electrode 110, a drain electrode 112, and a semiconductor layer 154. In this second mask process, the gate insulating layer 136 is formed on the substrate 145 on which the pixel electrode 114 and the gate metal pattern are formed using a vapor deposition method such as PECVD or sputtering. The gate insulating layer 136 may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx).

Next, as in the first mask process described above, a source / drain metal pattern is formed on the gate insulating layer 136 using a halftone mask or a diffraction exposure mask.

7A to 7C, the first semiconductor layer 211, the second semiconductor layer 213, and the third conductive layer 215 are deposited on the gate insulating layer 136 using a deposition method such as PECVD and sputtering. Lamination is sequentially formed. Here, the first semiconductor layer 211 is made of amorphous silicon doped with impurities, and the second semiconductor layer 213 is made of amorphous silicon doped with N-type or P-type impurities according to the TFT type. In addition, the third conductive layer 215 is made of a single layer of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or Al / Cr, Al / Mo, Al (Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu alloy Metallic materials such as / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al alloy / Mo alloy, Mo alloy / Al alloy, Mo / Al alloy It consists of two or more laminated structures.

Next, a first photoresist pattern PP1 and a second photoresist pattern PP2 having different thicknesses are formed on the third conductive layer 215 using a halftone mask. Among the halftone masks, a portion corresponding to the blocking portion P1 is formed with a first photoresist pattern PP1 having a first thickness, and a portion corresponding to the halftone transmitting portion P2 is a second thickness thinner than the first thickness. A second photoresist pattern PP2 having a is formed, and there is no photoresist pattern in the place corresponding to the transmissive portion P3 (see Fig. 7A).

Next, the exposed third conductive layer 215, the second semiconductor layer 213, and the first semiconductor layer 211 are sequentially etched using the first and second photoresist patterns PP1 and PP2 as a barrier. . Accordingly, the first semiconductor layer 211, the second semiconductor layer 213, and the third conductive layer 215 formed on the pixel electrode 114 are removed.

Next, the second photoresist pattern PP2 having a relatively thin thickness is removed by the ashing process using oxygen (O ₂ ) plasma, and accordingly, the third conductive layer 215 that is hidden by the second photoresist pattern PP2. ) Is exposed. At this time, the first photoresist pattern PP1 is thinned due to the ashing process (see FIG. 7B).

Next, by etching the first photoresist pattern PP1 as a barrier, the exposed third conductive layer 215 and the second semiconductor layer 213 are etched to separate the source electrode 110 and the drain electrode 112, , A semiconductor layer 154 having an active layer 148 and a resistive contact layer 150 is formed (FIG. 7C).

As described above, after forming the TFT, the first photoresist pattern PP1 remaining on the third conductive layer 215 is removed by a strip process, so that the source electrode 110, the drain electrode 112, and the data line 104 are removed. The containing source / drain metal pattern is completed.

As described above, when forming TFTs and data lines, one embodiment of the present invention uses a photoresist having a wing pattern.

8 shows a plan view of a photoresist including a wing pattern forming the data line 104. As shown in FIG. 8, the photoresist PR for forming the data line 104 includes a body BO and a wing pattern WI protruding in a serrated shape from the body BO.

Since light diffracts at the interface, when the photoresist is exposed and developed to form a pattern, the slope becomes gentle. However, when the photoresist includes a wing pattern as described above, the inclined surface is more inclined than when there is no wing pattern.

9 shows a process of forming a data line using a photoresist including such a wing pattern. In FIG. 9, the semiconductor layer is illustrated as being composed of a single layer.

In FIG. 9, after sequentially forming the semiconductor layer ac1 and the metal layer ac2, the pattern for forming a data line is completed by exposing and developing a photoresist PR having a wing pattern as illustrated in FIG. . Accordingly, photoresist is removed from the region except the region where the data line will be formed (see FIG. 9A).

In this state, the metal layer ac2 is wet-etched using the photoresist PR as a barrier. As an etchant, various forms may be selected in consideration of photoresist (PR) (see FIG. 9B).

The metal layer ac2 is selectively removed by wet etching, and the semiconductor layer ac1 formed under the metal layer ac2 is exposed. As described above, in a state where the semiconductor layer ac1 is exposed, the semiconductor layer ac1 is dry etched using the photoresist PR as a barrier. At this time, the semiconductor layer ac1 is etched so that undercut occurs so that the semiconductor layer ac1 is positioned inwardly than the metal layer ac2 remaining under the photoresist PR (see FIG. 9C).

On the other hand, the photoresist PR is also reduced in size by dry etching, and after the dry etching is completed, a part of both ends of the metal layer ac2 that is covered by the photoresist PR is exposed. The exposed metal layer ac2 is wet etched with a photoresist PR as a barrier. Accordingly, it is possible to form a data line with a reduced active tail.

10 is a plan view illustrating a third mask process, and FIG. 11 is a cross-sectional view taken along line I-I of FIG. 10.

The third mask process is a step of forming first and second contact holes CH1 and CH2 penetrating the protective layer 152 or the protective layer 152 and the gate insulating layer 136 using a photoresist pattern. In the third mask process, a TFT, a gate insulating film 136 and a protective film 152 made of an organic material are formed over the source / drain metal pattern. The protective film 152 is made of an inorganic insulating material such as the gate insulating film 136 or an acrylic organic compound having a small dielectric constant, or an organic insulating material such as BCB or PFCB.

In the third mask process, a photoresist pattern having a 1-2 contact hole pattern is formed on the passivation layer 152 as a third mask, and the exposed areas are etched to form a 1-2 contact hole (CH1-CH2) To form. Thereafter, the photoresist pattern PR is removed by a strip process. Here, the first contact hole CH1 penetrates the passivation layer 152 to expose the drain electrode 112, and the second contact hole CH2 penetrates the passivation layer 152 and the gate insulating layer 136 to form the pixel electrode ( 114).

12 is a plan view illustrating a fourth mask process, and FIG. 13 is a cross-sectional view taken along line I-I.

The fourth mask process is a step of forming an electrode metal pattern including a light shielding film BLSP.

In this fourth mask process, the fourth conductive layer 221 is formed on the protective film 152 and the first to second contact holes CH1-CH2 using a vapor deposition method such as a sputtering method. The fourth conductive layer 221 is made of a single layer of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or Al / Cr, Al / Mo, Al ( Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu alloy / Metallic materials such as Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al alloy / Mo alloy, Mo alloy / Al alloy, Mo / Al alloy It consists of two or more layered structures.

Then, the photoresist PR is patterned on the fourth conductive layer 221 using the fourth mask, and the fourth conductive layer 221 exposed to the barrier is etched. Accordingly, the fourth conductive layer 221 formed except for the pixel link electrode LK1 and the light blocking film BLSP is removed.

Next, the remaining photoresist (PR) is removed by a strip process to complete the electrode metal pattern.

In the thin film transistor substrate of the present embodiment manufactured as described above, the data line 104 may be formed using a wing pattern as described through FIGS. 8 and 9 to reduce the active tail to form a fine pattern data line.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

Claims (4)

In the method of manufacturing a thin film transistor array substrate including a data line consisting of a two-layer structure of a semiconductor layer and a metal layer using a plurality of mask processes,
The data line,
(a) sequentially stacking and forming a semiconductor layer and a metal layer,
(b) forming a photoresist having a wing pattern on the metal layer and wet etching the metal layer as a barrier to expose the semiconductor layer;
(c) dry etching the semiconductor layer exposed by the step (b) using the photoresist as a barrier to undercut the semiconductor layer while reducing the size of the photoresist;
(d) a method of manufacturing a thin film transistor array substrate, comprising exposing a portion of both ends of the semiconductor layer by wet etching a portion of both ends of the metal layer exposed outside the reduced size photoresist.
According to claim 1,
Before forming the data line,
Forming a transparent pixel electrode, a metal gate line, and a metal gate electrode on the substrate; And
And forming a gate insulating film on the substrate to cover the transparent pixel electrode, the metal gate line, and the metal gate electrode, and sequentially stacking the semiconductor layer and the metal layer on the gate insulating film. Method for manufacturing a transistor array substrate.
According to claim 2,
The semiconductor layer includes a first semiconductor layer and a second semiconductor layer,
Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness on the metal layer to be spaced apart from each other;
The first and second photoresist patterns are barriers, and the metal layer, the second semiconductor layer, and the first semiconductor layer exposed through the first and second photoresist patterns are sequentially etched to overlap the pixel electrode. Removing the metal layer, the second semiconductor layer and the first semiconductor layer at the location;
Removing the second photoresist pattern in an ashing process using oxygen plasma to expose the metal layer, and thinning the thickness of the first photoresist pattern so that the metal layer at a position corresponding to the gate electrode is exposed; And
A source electrode and a drain electrode are formed by etching the first photoresist pattern as a barrier and the metal layer and the second semiconductor layer exposed through the first photoresist pattern, and the source electrode, the drain electrode, and the gate And forming an active layer of the first semiconductor layer overlapping with an electrode and a resistive contact layer overlapping the source electrode and the drain electrode on the active layer of the first semiconductor layer.
According to claim 3,
A protective layer is formed on the gate insulating layer to cover the source electrode, the drain electrode, and the data line, and a first contact hole penetrating the protective layer to expose a portion of the drain electrode and a portion of the pixel electrode are exposed. Forming a second contact hole penetrating the protective layer and the gate insulating layer; And
Forming a conductive layer on the passivation layer and then patterning the conductive layer to form a pixel link electrode connecting the drain electrode and the pixel electrode and a light blocking layer positioned in a region between the pixel electrode and the data line Method of manufacturing a thin film transistor array substrate comprising a.

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