KR102410396B1 - Horizontal electric field type liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The present invention relates to a horizontal electric field type liquid crystal display device capable of reducing wiring resistance while reducing a channel length of a thin film transistor, and a method for manufacturing the same, wherein gate lines and data lines intersecting each other, thin film transistors, and a pixel electrode and common electrodes. Thin film transistors are disposed adjacent to intersections of the gate lines and the data lines. The pixel electrodes are connected to the data line through the thin film transistor, and are respectively disposed in the pixel areas defined by the gate lines and the data lines. The common electrode is disposed to form a horizontal electric field with the pixel electrodes. Each of the data lines includes a first impurity semiconductor region, a 1-1 metal layer, and a second metal layer of a semiconductor layer including a first impurity semiconductor region and a second impurity semiconductor region disposed with an intrinsic semiconductor region therebetween. The source electrode of the thin film transistor includes a first impurity semiconductor region of the semiconductor layer and the first metal layer. The drain electrode of the thin film transistor includes a second impurity semiconductor region of the semiconductor layer and a first 1-2 metal layer spaced apart from the 1-1 metal layer.

Description

Horizontal electric field type liquid crystal display and manufacturing method thereof

The present invention relates to a horizontal electric field type liquid crystal display device and a manufacturing method thereof, and more particularly, to a horizontal electric field type liquid crystal display device capable of reducing the resistance of wiring while reducing the channel length of a thin film transistor and a manufacturing method thereof.

A liquid crystal display displays an image by adjusting the light transmittance of liquid crystal using an electric field. The liquid crystal display is roughly classified into a vertical electric field type and a horizontal electric field type according to the direction of the electric field driving the liquid crystal.

In a vertical electric field type liquid crystal display, a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are disposed to face each other, and a TN (Twisted Nematic) mode liquid crystal is driven by a vertical electric field formed therebetween. Such a vertical electric field type liquid crystal display has an advantage of a large aperture ratio, but has a disadvantage of a narrow viewing angle of about 90 degrees.

In the horizontal electric field type liquid crystal display, liquid crystal is driven by a horizontal electric field between a pixel electrode and a common electrode arranged in parallel on a lower substrate. Such a horizontal electric field type liquid crystal display has the advantage of having a wide viewing angle of 170 degrees or more, and having a fast response speed because it is switched in a horizontal state.

Hereinafter, a conventional horizontal electric field type liquid crystal display will be described in more detail with reference to FIGS. 1 and 2 .

1 is a plan view illustrating one pixel area of a conventional horizontal electric field type liquid crystal display, and FIG. 2 is a cross-sectional view taken along line I-I' of FIG. 1 .

1 and 2 , a conventional horizontal electric field type liquid crystal display includes a plurality of gate lines G1 and G2 and data lines D1 and D2 arranged to cross each other on a substrate SUB, and a plurality of thin film transistors T disposed at intersections of the gate lines G1 and G2 and the data lines D1 and D2, the plurality of gate lines G1 and G2 and the data lines D1 and D2 ), the pixel electrodes Px and the pixel electrodes disposed in the pixel areas defined by the intersection of the pixels, connected to the data lines D1 and D2 through the thin film transistors T and a common electrode COM disposed to form a horizontal electric field with Px.

In the above configuration, the gate lines G1 and G2 and the gate electrodes GE extending from each of the gate lines toward the pixel region are disposed on the substrate SUB.

A semiconductor active layer A is disposed on the gate insulating layer GI that covers the gate lines G1 and G2 and the gate electrode GE to overlap the gate electrode GE.

Data lines D1 and D2 are disposed on the gate insulating layer GI in a direction crossing the gate lines G1 and G2, and sources extending from the data lines D1 and D2 on the semiconductor active layer A, respectively. The electrode SE is disposed. A drain electrode DE is disposed on the semiconductor active layer A to be spaced apart from the source electrode SE by a predetermined distance so that a partial region of the semiconductor active layer A is exposed. The thin film transistor T is constituted by the gate electrode GE, the semiconductor active layer A, the source electrode SE, and the drain electrode DE.

The source electrode SE, the exposed active region A and the drain electrode DE, and the data lines D1 are disposed on the gate insulating layer GI on which the thin film transistor T and the data lines D1 and D2 are disposed. , D2 , a first insulating layer INS1 is formed. A second insulating layer INS2 for planarization is disposed on the first insulating layer INS1 . The second insulating layer INS2 includes a contact hole CH exposing a partial region of the drain electrode DE.

A pixel electrode Px is disposed on the second insulating layer INS2 for each pixel area. The pixel electrode Px is connected to the drain electrode DE exposed through the contact hole CH.

A third insulating layer INS3 is disposed on the second insulating layer INS2 to cover the pixel electrode Px. The common electrode COM is disposed on the third insulating layer INS3 to overlap the pixel electrode Px. The common electrode COM includes a plurality of slits to form an electric field with the pixel electrode Px.

In the conventional horizontal electric field type liquid crystal display device described above, in order to reduce the number of mask processes, the semiconductor active layer A, the data lines D1 and D2, the source electrode SE, and the drain electrode DE are formed by using a halftone mask process. Since it is formed by the mask process of the semiconductor active layer (A), the channel length L of the semiconductor active layer (A) is determined according to the separation distance between the source electrode (SE) and the drain electrode (SE) formed by the halftone mask process.

On the other hand, since the data lines D1 and D2 are disposed over the entire area of the display area in which data is displayed, the electrical resistance increases as the size of the display device increases. Accordingly, in order to reduce the electrical resistance of the data lines D1 and D2, it is necessary to increase the thickness of each data line.

However, when the thickness of the data lines D1 and D2 is increased to reduce the electrical resistance, since the source electrode and the drain electrode are also formed together with the semiconductor active layer when the data lines are formed, etching is performed by the increase in the thickness of the data lines. As time increases, the source electrode and the drain electrode are overetched, so that the channel length of the semiconductor active layer is inevitably increased.

An increase in the channel length of the semiconductor active layer means an increase in the size of the thin film transistor, and as the size of the thin film transistor increases, the aperture ratio decreases by that amount. Therefore, there is a problem in that the brightness of the display device decreases.

After all, according to the conventional horizontal electric field type liquid crystal display device, since the thickness of the data line of the wiring part and the source electrode and the drain electrode of the thin film transistor part are the same, if the resistance of the data line is decreased by increasing these thicknesses, the length of the semiconductor active layer increases to display There is a problem in that the aperture ratio of the device increases, and when the thickness of the data line, the source electrode, and the drain electrode is thinned in order to reduce the length of the semiconductor active layer, the electrical resistance increases and the driving characteristics of the display device deteriorate.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described technical problem, and a horizontal electric field type liquid crystal display device capable of reducing the length of a semiconductor active layer of a thin film transistor while increasing the thickness of a data line of a wiring part and a source electrode and a drain electrode of a thin film transistor, and It is to provide the manufacturing method.

The present invention provides a horizontal electric field type liquid crystal display device according to the first aspect of the present invention in which gate lines and data lines, thin film transistors, pixel electrodes and a common electrode are arranged to cross each other. include those Thin film transistors are disposed adjacent to intersections of the gate lines and the data lines. The pixel electrodes are connected to the data line through the thin film transistor, and are respectively disposed in the pixel areas defined by the gate lines and the data lines. The common electrode is disposed to form a horizontal electric field with the pixel electrodes. Each of the data lines includes a first impurity semiconductor region, a 1-1 metal layer, and a second metal layer of a semiconductor layer including a first impurity semiconductor region and a second impurity semiconductor region disposed with an intrinsic semiconductor region therebetween. The source electrode of the thin film transistor includes a first impurity semiconductor region of the semiconductor layer and the first metal layer. The drain electrode of the thin film transistor includes a second impurity semiconductor region of the semiconductor layer and a first 1-2 metal layer spaced apart from the 1-1 metal layer.

In the above configuration, the gate line is disposed on a transparent substrate, the semiconductor layer is disposed on a gate insulating film covering the gate line, and the source electrode overlaps the first impurity semiconductor region of the semiconductor layer. It is disposed on the impurity semiconductor region, and the drain electrode is disposed on the second impurity semiconductor region to overlap the second impurity semiconductor region of the semiconductor layer.

In addition, the 1-1 metal layer of the data line and the first impurity semiconductor region of the semiconductor layer extend into the pixel region to form a source electrode of the thin film transistor.

In addition, the pixel electrode has one end overlapping the second metal layer and the first and second metal layers exposed through an insulating layer that covers the source electrode and the drain electrode exposed through the second metal layer, and is formed on the insulating layer. The first pixel to have one end overlapping the first pixel electrode disposed and the 1-1 metal layer exposed through an insulating layer that covers the data line, the source electrode exposed through the second metal layer, and the drain electrode and a second pixel electrode separated from the electrode and disposed on the insulating layer.

In addition, the common electrode is disposed to overlap the pixel electrode on the pixel electrode and a passivation layer disposed on the insulating layer to cover the intrinsic semiconductor region of the semiconductor layer exposed through the pixel electrode, and overlap the first pixel electrode It has a plurality of openings overlapping the first pixel electrode to form a horizontal electric field.

The horizontal electric field type liquid crystal display device according to the first aspect of the present invention provides gate lines and common lines arranged in a first direction adjacent to each other on a substrate and data arranged in a second direction crossing the first direction. Lines, thin film transistors respectively disposed adjacent to intersections of the gate lines and the data lines, a pixel connected to the data line through the thin film transistors, and defined by the gate lines and the data lines pixel electrodes respectively disposed in the regions, and a common electrode connected to the common line and disposed to form a horizontal electric field with the pixel electrode, wherein each of the data lines is disposed with an intrinsic semiconductor region therebetween A first impurity semiconductor region of a semiconductor layer including a first impurity semiconductor region and a second impurity semiconductor region, a first impurity semiconductor region, a 1-1 metal layer, and a second metal layer, wherein the source electrode of the thin film transistor is a first impurity semiconductor region of the semiconductor layer an impurity semiconductor region and the 1-1 metal layer, and the drain electrode of the thin film transistor includes a second impurity semiconductor region of the semiconductor layer and a first 1-2 metal layer spaced apart from the 1-1 metal layer.

In the above configuration, the gate line and the common line are disposed on a transparent substrate, the semiconductor layer is disposed on a gate insulating film covering the gate line and the common line, and the source electrode is a first of the semiconductor layer. It is disposed on the first impurity semiconductor region to overlap the impurity semiconductor region, and the drain electrode is disposed on the second impurity semiconductor region to overlap the second impurity semiconductor region of the semiconductor layer.

In addition, the 1-1 metal layer of the data line and the first impurity semiconductor region of the semiconductor layer extend into the pixel region to form a source electrode of the thin film transistor.

In addition, the pixel electrode has one end overlapping the second metal layer and the first and second metal layers exposed through an insulating layer that covers the source electrode and the drain electrode exposed through the second metal layer, and is formed on the insulating layer. a first pixel electrode disposed on one side of each pixel region and including a first stem portion and a plurality of branch portions extending from the first stem portion into the pixel region, the data line, and the second metal layer a second pixel electrode separated from the first pixel electrode and disposed on the insulating film to have one end overlapping the 1-1 metal layer exposed through the insulating film covering the source electrode and the drain electrode exposed through do.

In addition, the common electrode is disposed on the insulating layer and includes a second stem disposed on the other side of each pixel area and a plurality of second branch portions extending from the second stem to the inside of the pixel area, The second branch portions of the common electrode are alternately disposed with the first branch portions of the pixel electrode.

In a method for manufacturing a horizontal electric field type liquid crystal display of the present invention for achieving the above object, a gate line and a gate electrode included in the gate line are formed by a photolithography process using a first mask after depositing a first conductive metal material on a substrate. Forming a first conductive metal layer comprising: a gate insulating layer, a semiconductor material, a second conductive metal material, and a third conductive material are sequentially applied on the substrate on which the first conductive metal layer is formed, 2 Forming second conductive metal patterns including a semiconductor layer and a first metal layer overlapping each other by a photolithography process using a mask, and a second metal layer overlapping a partial region of the semiconductor layer and the first metal layer; forming a first contact hole exposing the first metal layer by a photolithography process using a third mask after coating at least one insulating layer on the gate insulating layer on which the second conductive metal patterns are disposed; After a transparent conductive material is coated on the insulating film in which the hole is formed, the transparent conductive material and the first metal layer are removed at once so that a partial region of the semiconductor layer is exposed by a photolithography process using a fourth mask, a 1-1 pixel electrode having a metal layer and a 1-2 metal layer, one end overlapping the 1-1 metal layer, and a 1-2 pixel electrode having one end overlapping the 1-1 metal layer; forming, and sequentially coating a protective film and a transparent conductive material on the 1-1 metal layer and the 1-1 metal layer formed insulating film, and then patterning the transparent conductive material by a photolithography process using a fifth mask and forming a common electrode overlapping the 1-1 metal layer.

In the above step, the forming of the second conductive metal patterns may include sequentially coating a gate insulating layer, a semiconductor material, a second conductive metal material, and a third conductive material on the substrate on which the first conductive metal layer is formed; Forming a photoresist pattern using a halftone mask after applying a photoresist all over the third conductive material, and selectively etching the third conductive material by a first wet etching to form a second metal layer, and selectively etching a second conductive material by a second wet etching to form a first metal layer, and selectively etching the semiconductor layer by dry etching to form the semiconductor layer, wherein the first metal layer and the semiconductor The layers are formed to overlap each other, and extend from a partial region of the second metal layer to the pixel region to form a source electrode of the thin film transistor.

In addition, the forming of the first contact hole may include sequentially coating a first insulating layer and a second insulating layer on the gate insulating layer, and developing the second insulating layer after exposure to a photolithography process using the third mask. and forming a second insulating layer pattern by dry etching the first insulating layer to expose a portion of the first metal layer using the second insulating layer pattern as a mask to form a first contact hole.

In addition, the first pixel electrode has an end portion overlapping the first 1-2 metal layer exposed through the first contact hole, and the second pixel electrode has the 1-1 first electrode exposed through the first contact hole. It has an end overlapping the metal layer.

A method for manufacturing a horizontal electric field type liquid crystal display device of the present invention for achieving the above object includes a gate line including a gate electrode by a photolithography process using a first mask after depositing a first conductive metal material on a substrate, and the gate forming a first conductive metal layer including a common line adjacent to and parallel to the line; After being coated with a second halftone mask, a second metal layer including a semiconductor layer and a first metal layer overlapping each other, and a second metal layer overlapping a partial region of the semiconductor layer and the first metal layer by a photolithography process using a second mask of a halftone mask Forming two conductive metal patterns, sequentially coating at least a first insulating layer and a second insulating layer on the gate insulating layer on which the second conductive metal patterns are disposed, and then performing a photolithography process using a third mask to form the first metal layer A fourth mask after forming a first contact hole exposing the first contact hole and a second contact hole exposing the common line, and coating a transparent conductive material on the second insulating layer in which the first and second contact holes are formed The 1-1 metal layer and the 1-2 metal layer separated from each other by removing the transparent conductive material and the first metal layer at once so that a partial region of the semiconductor layer is exposed through a photolithography process using forming a first pixel electrode having one end overlapping the metal layer, a second pixel electrode having one end overlapping the 1-1 metal layer, and a common electrode arranged to form a horizontal electric field with the first pixel electrode; includes

In addition, the forming of the second conductive metal patterns may include sequentially coating a gate insulating layer, a semiconductor material, a second conductive metal material, and a third conductive material on the substrate on which the first conductive metal layer is formed; Forming a photoresist pattern by using a halftone mask after applying a photoresist all over the conductive material, and selectively etching the third conductive material by a first wet etching to form a second metal layer; and selectively etching the conductive material by a second wet etching to form a first metal layer, and selectively etching the semiconductor layer by dry etching to form the semiconductor layer, wherein the first metal layer and the semiconductor layer are They are formed to overlap each other, and extend from a partial region of the second metal layer to a pixel region to form a source electrode of the thin film transistor.

In addition, the forming of the first and second contact holes may include sequentially coating a first insulating layer and a second insulating layer on the gate insulating layer, and a photolithography process using the third mask to form the second insulating layer. forming a second insulating layer pattern by developing after exposure; and dry etching the first insulating layer to expose a portion of the first metal layer using the second insulating layer pattern as a mask to form the first contact hole; and forming the second contact hole by etching the first insulating layer and the gate insulating layer to expose a portion of the common line.

In addition, the first pixel electrode has an end portion overlapping the first and second metal layers exposed through the first contact hole, and the second pixel electrode has the 1-1th electrode exposed through the first contact hole. It has an end overlapping the metal layer, and the common electrode is connected to the common line exposed through the second contact hole.

According to the horizontal electric field type liquid crystal display device and the method for manufacturing the same according to the present invention, each of the data lines formed in the wiring portion is composed of a triple layer of a conductive impurity semiconductor layer, a first metal layer, and a second metal layer. Accordingly, since the electrical resistance can be reduced by increasing the thickness of the data line, the driving ability of the display device can be increased.

In addition, since the second metal layer and the 1-1 metal layer constituting the data line are formed by different masking processes, the channel length of the thin film transistor can be reduced while increasing the thickness of the second metal layer. For example, if the pixel electrode has a thickness thinner than that of the second metal layer, the etching time can be reduced, thereby reducing the resistance of the data line while reducing the channel length of the thin film transistor.

In addition, since the first metal layer of the pixel electrode and the drain electrode and the first metal electrode of the source electrode are made in one process, an interlayer margin is secured, thereby preventing defects in the manufacturing process due to misalignment.

In addition, since the pixel electrode made of a transparent conductive material and the second metal layer made of copper do not contact each other, it is possible to prevent a problem of poor adhesion due to the characteristics between the two materials.

1 is a plan view showing a conventional horizontal electric field type liquid crystal display;
2 is a cross-sectional view taken along line II' of FIG. 1;
3 is a block diagram schematically showing a horizontal electric field type liquid crystal display according to an embodiment of the present invention;
4 is a plan view illustrating a one-pixel area of a horizontal electric field type liquid crystal display according to a first embodiment of the present invention;
5 is a cross-sectional view taken along line I-I' in FIG. 4;
6 is a plan view showing a one-pixel area of a horizontal electric field type liquid crystal display according to a second embodiment of the present invention;
7 is a cross-sectional view taken along line II-II' of FIG. 6;
8A is a plan view showing a first mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention;
Fig. 8b is a cross-sectional view taken along line I-I' in Fig. 8a;
9A is a plan view showing a second mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention;
Fig. 9b is a cross-sectional view taken along line I-I' in Fig. 9a;
10A is a plan view illustrating a third mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention;
Fig. 10b is a cross-sectional view taken along line I-I' in Fig. 10a;
11A is a plan view illustrating a fourth mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention;
11B is a cross-sectional view taken along line II' in FIG. 11A;
12A is a plan view illustrating a fifth mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention;
Fig. 12b is a cross-sectional view taken along line II' in Fig. 12a;
13A is a plan view showing a first mask process of a horizontal electric field type liquid crystal display according to a second embodiment of the present invention;
13B is a cross-sectional view taken along line II-II' of FIG. 13A;
14A is a plan view illustrating a second mask process of a horizontal electric field type liquid crystal display according to a second embodiment of the present invention;
Fig. 14b is a cross-sectional view taken along line II-II' in Fig. 4a;
15A is a plan view illustrating a third mask process of a horizontal electric field type liquid crystal display according to a second embodiment of the present invention;
Fig. 15b is a cross-sectional view taken along line II-II' in Fig. 15a;
16A is a plan view illustrating a fourth mask process of a horizontal electric field type liquid crystal display according to a second embodiment of the present invention;
Fig. 16B is a cross-sectional view taken along line II-II' of Fig. 16A;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

First, a horizontal electric field type liquid crystal display according to an embodiment of the present invention will be described with reference to FIG. 3 .

3 is a block diagram schematically illustrating a horizontal electric field type liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 3 , the liquid crystal display includes a liquid crystal display panel 10 on which a pixel array PA is formed, a source drive integrated circuit (referred to as an 'IC') 12 , and a gate driving circuit 13 . , and a timing controller 11 . A backlight unit for uniformly irradiating light to the liquid crystal display panel 10 may be disposed under the liquid crystal display panel 10 .

The liquid crystal display panel 10 includes a pixel array PA formed on a transparent substrate. The transparent substrate of the pixel array PA includes data lines DL, gate lines GL, thin film transistors, a pixel electrode of a sub-pixel connected to the thin film transistor, and a storage capacitor connected to the pixel electrode. etc are formed. Each of the sub-pixels of the pixel array PA drives the liquid crystal in the liquid crystal layer by the voltage difference between the pixel electrode charged with the data voltage through the thin film transistor and the common electrode to which the common voltage is applied to adjust the amount of light transmitted to display an image. indicate

The liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a reflective liquid crystal display, or a transflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The source drive ICs 12 are mounted on a Tape Carrier Package (TCP) 15 and bonded to the glass substrate of the liquid crystal display panel 10 by a Tape Automated Bonding (TAB) process, and a source PCB (Printed Circuit Board). (14) is connected. The source drive ICs 12 may be adhered to the transparent substrate of the liquid crystal display panel 10 by a chip on glass (COG) process.

Each of the source drive ICs 12 receives digital video data and a source timing control signal from the timing controller 11 . The source drive ICs 12 convert digital video data into positive/negative data voltages in response to a source timing control signal and supply the converted digital video data to data lines of the pixel array PA. The source drive ICs 12 output data voltages to data lines under the control of the timing controller 11 .

The gate driving circuit 13 receives a gate timing control signal from the timing controller 11 . The gate driving circuit 13 sequentially supplies a gate pulse (or a scan pulse) to the gate lines of the pixel array in response to the gate timing control signal. The gate driving circuit 13 may be mounted on the TCP and bonded to the lower glass substrate of the liquid crystal display panel 10 by a TAB process. Alternatively, the gate driving circuit 13 may be directly formed on the transparent substrate simultaneously with the pixel array PA by a GIP (Gate In Panel) process. The gate driving circuit 13 may be disposed on one side of the pixel array PA or may be disposed on both sides of the pixel array PA as shown in FIG. 3 .

The timing controller 11 receives digital video data, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and timing signals such as a dot clock from an external system board. The timing controller 11 includes a source timing control signal for controlling the operation timing of the source drive ICs 12 and a gate timing for controlling the operation timing of the gate driving circuit 13 based on digital video data and timing signals. Generates a control signal. The timing controller 11 supplies digital video data and a source timing control signal to the source drive ICs 12 . The timing controller 11 supplies a gate timing control signal to the source drive ICs 12 . The timing controller 11 is mounted on the control PCB 16 . The control PCB 16 and the source PCB 14 may be connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

Next, the pixel structure of the pixel array of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention will be described in more detail with reference to FIGS. 4 and 5 .

4 is a plan view illustrating a one-pixel region of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line I-I' of FIG. 4 .

4 and 5 , the horizontal electric field type liquid crystal display according to the first embodiment of the present invention includes gate lines G1 and G2 and data lines D1 and D2 arranged to cross each other, and a gate Thin film transistors TFT disposed adjacent to intersections of lines G1 and G2 and data lines D1 and D2, and data lines D1 and D2 through thin film transistors TFT, respectively The pixel electrodes Px and PxF connected to each other and respectively disposed in pixel regions defined by the gate lines G1 and G2 and the data lines D1 and D2, the pixel electrodes Px and the horizontal electric field and a common electrode COM disposed to form

This will be described in more detail, and on the transparent substrate SUB, the gate lines G1 and G2 are disposed at regular intervals in the vertical direction of the drawing, for example. Each of the gate lines G1 and G2 may include a gate electrode GE.

A semiconductor layer A is disposed on the gate insulating layer GI that covers the gate lines G1 and G2.

The semiconductor layer A is disposed on the gate insulating layer GI covering the gate lines G1 and G2 in a direction crossing the gate lines G1 and G2, and includes extension portions extending to each pixel area. . The semiconductor layer A is disposed in the data line formation region, the semiconductor active region, the source electrode and the drain electrode formation region, and the semiconductor active region serving as a channel of the thin film transistor TFT becomes the intrinsic semiconductor region A2, and the remaining The data line forming region, the source electrode forming region, and the drain electrode forming region, which are the regions, become impurity semiconductor regions A1 and A3 to be conductive.

A 1-1 metal layer M1a and a 1-2 metal layer M1b made of an alloy such as MoTi (molybdenum-titanium) and AlNd (aluminum-niodium) are disposed on the semiconductor layer A. The 1-1 metal layer M1a is disposed on the impurity semiconductor region A1 to overlap the impurity semiconductor region A1 of the semiconductor layer A, and the 1-2 metal layer M1b is formed of the semiconductor layer A It is disposed on the impurity semiconductor region A3 so as to overlap the impurity semiconductor region A1 . That is, one end of the 1-1 th metal layer M1a is arranged to be aligned with one end of the impurity semiconductor region A1 , and the other end is arranged to be aligned with the interface between the impurity semiconductor region A1 and the intrinsic semiconductor region A2 . do. In addition, one end of the first and second metal layers M1b is arranged to be aligned with one end of the impurity semiconductor region A3 , and the other end is arranged to be aligned with the interface between the impurity semiconductor region A3 and the intrinsic semiconductor region A2 . do. According to this configuration, the 1-1 metal layer M1a and the 1-2 metal layer M1b are disposed separately on the semiconductor layer A, and the 1-1 metal layer M1a and the 1-2 metal layer M1b are disposed separately. The intrinsic semiconductor region A2 of the semiconductor layer A is exposed between them.

The 1-1 metal layer M1a constitutes the source electrode SE together with the impurity semiconductor region A1 of the semiconductor layer A, and the 1-2 metal layer M1b is the impurity semiconductor region of the semiconductor layer A. Together with (A2), the drain electrode DE is formed.

A second metal layer M2 made of a highly conductive metal material such as Cu (copper) or Mo (molybdenum) is disposed on the 1-1 metal layer M1a in a direction crossing the gate lines G1 and G2. For the second metal layer M2, Cu is used when the first metal layer M1 is MoTi, and Mo is used when the first metal layer M1 is AlNd. The line width of the second metal layer M2 is formed to be the same as that of the 1-1th metal layer M1a. The 1-1th metal layer M1a extends from the thin film transistor TFT formation region toward the pixel region to form the source electrode SE.

According to this configuration, each of the data lines D1 and D2 has three layers of the second metal layer M2, the 1-1 metal layer M1a, and the 1-1 impurity region A1 of the semiconductor layer A. made of structure

First and second insulating films ( INS1 and INS2) are sequentially arranged. The first and second insulating layers INS1 and INS2 are a partial region of the first metal layer M1a of the source electrode SE, a partial region of the first metal layer M1b of the drain electrode DE, and the semiconductor layer A ) and a first contact hole CH1 exposing the intrinsic semiconductor region A2.

On the first and second insulating layers INS1 and INS2 in which the first contact hole CH1 is formed, the first metal layer M1b of the drain electrode DE exposed through the first contact hole CH1 and the source electrode ( A pixel electrode overlapping the first metal layer M1a of SE) is disposed.

The pixel electrode is exposed through the first contact hole CH1 and the first pixel electrode Px overlapping the first and second metal layers M1 of the drain electrode DE exposed through the first contact hole CH1. and a second pixel electrode DPx overlapping the 1-1 metal layer M1a of the source electrode SE.

The first pixel electrode Px is connected to the first and second metal layers M1b of the drain electrode DE and extends into the pixel region. One end of the first pixel electrode Px is aligned with the exposed end of the first and second metal layers M1b of the drain electrode DE.

The second pixel electrode DPx is spaced apart from the first pixel electrode and is disposed adjacent to the pixel region. Also, one end of the second pixel electrode DPx is aligned with the exposed end of the 1-1 metal layer M1a of the source electrode SE. The second pixel electrode DPx is a dummy electrode that does not affect display driving.

The intrinsic semiconductor region A2 of the semiconductor layer A is exposed between the first and second pixel electrodes Px and DPx. The first and second pixel electrodes Px and DPx are formed using a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or gallium doped zinc oxide (GZO).

A passivation layer PAS is disposed on the second insulating layer INS2 to cover the first and second pixel electrodes Px and DPx and the intrinsic semiconductor region A2 of the semiconductor layer A.

A common electrode COM is disposed on the passivation layer PAS. The common electrode COM is disposed to overlap the pixel electrodes Px and DPx. The common electrode COM has a plurality of openings SL in a region overlapping the first pixel electrode Px to form a horizontal electric field with the first pixel electrode Px. The common electrode COM is formed using a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or gallium doped zinc oxide (GZO).

According to the horizontal electric field type liquid crystal display device according to the first embodiment of the present invention described above, the impurity semiconductor layer A1 and the first metal layer M1 in which the data lines D1 and D2 formed in the wiring portion are respectively conductive. and a triple layer of the second metal layer M2. Accordingly, since the electrical resistance can be reduced by increasing the thickness of the data line, the driving ability of the display device can be increased.

In addition, since the second metal layer M2 and the 1-1 metal layer M1a constituting the data line are formed by different mask processes, the channel length of the thin film transistor is reduced while increasing the thickness of the second metal layer M2. possible effects can be obtained. For example, if the pixel electrodes Px and DPx have a thinner thickness than the second metal layer M2, the etching time can be reduced, thereby reducing the resistance of the data line and reducing the channel length of the thin film transistor. can be obtained

In addition, since the first metal layer M1 of the pixel electrode Px and the drain electrode DE and the first metal electrode M1 of the source electrode SE are made in a single process, an interlayer margin is secured and manufacturing due to misalignment It is possible to obtain the effect of preventing process defects.

In addition, since the pixel electrode made of a transparent conductive material and the second metal layer made of copper do not contact each other, it is possible to prevent a problem of poor adhesion due to the characteristics between the two materials.

Next, a pixel structure of a pixel array of a horizontal electric field type liquid crystal display according to a second embodiment of the present invention will be described in more detail with reference to FIGS. 6 and 7 .

6 is a plan view illustrating a one-pixel region of a horizontal electric field type liquid crystal display according to a second embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along line II-II′ of FIG. 6 .

6 and 7 , in the horizontal electric field type liquid crystal display according to the second embodiment of the present invention, a gate line G1 and a common line CL and gate lines G1 are adjacent to each other and disposed in parallel. . A pixel connected to the data lines D1 and D2 through the transistors TFT and the thin film transistors TFT, respectively, and defined by the gate lines G1 and G2 and the data lines D1 and D2 It includes pixel electrodes Px and DPx respectively disposed in the regions, and a common electrode COM disposed to form a horizontal electric field with the pixel electrodes Px.

This will be described in more detail, and on the transparent substrate SUB, the gate lines G1 and G2 are disposed at regular intervals in the vertical direction of the drawing, for example. A common line CL is disposed in parallel with the gate line G1 adjacent to each of the gate lines G1 and G2. Each of the gate lines G1 and G2 may include a gate electrode GE.

A semiconductor layer A is disposed on the gate insulating layer GI that covers the gate lines G1 and G2 and the common line CL.

The semiconductor layer A is disposed on the gate insulating layer GI covering the gate lines G1 and G2 in a direction crossing the gate lines G1 and G2, and includes extension portions extending to each pixel area. . The semiconductor layer A is disposed in the data line formation region, the semiconductor active region, the source electrode and the drain electrode formation region, and the semiconductor active region serving as a channel of the thin film transistor TFT becomes the intrinsic semiconductor region A2, and the remaining The data line forming region, the source electrode forming region, and the drain electrode forming region, which are the regions, become impurity semiconductor regions A1 and A3 and are conductive.

A 1-1 metal layer M1a and a 1-2 metal layer M1b made of an alloy such as MoTi (molybdenum-titanium) and AlNd (aluminum-niodium) are disposed on the semiconductor layer A. The 1-1 metal layer M1a is disposed on the impurity semiconductor region A1 to overlap the impurity semiconductor region A1 of the semiconductor layer A, and the 1-2 metal layer M1b is formed of the semiconductor layer A It is disposed on the impurity semiconductor region A3 so as to overlap the impurity semiconductor region A1 . That is, one end of the 1-1 th metal layer M1a is arranged to be aligned with one end of the impurity semiconductor region A1 , and the other end is arranged to be aligned with the interface between the impurity semiconductor region A1 and the intrinsic semiconductor region A2 . do. In addition, one end of the first and second metal layers M1b is arranged to be aligned with one end of the impurity semiconductor region A3 , and the other end is arranged to be aligned with the interface between the impurity semiconductor region A3 and the intrinsic semiconductor region A2 . do. According to this configuration, the 1-1 metal layer M1a and the 1-2 metal layer M1b are disposed separately on the semiconductor layer A, and the 1-1 metal layer M1a and the 1-2 metal layer M1b are disposed separately. The intrinsic semiconductor region A2 of the semiconductor layer A is exposed between them.

The 1-1 metal layer M1a constitutes the source electrode SE together with the impurity semiconductor region A1 of the semiconductor layer A, and the 1-2 metal layer M1b is the impurity semiconductor region of the semiconductor layer A. Together with (A2), the drain electrode DE is formed.

A second metal layer M2 made of a highly conductive metal material such as Cu (copper) or Mo (molybdenum) in a direction crossing the gate lines G1 and G2 and the common line CL on the 1-1 metal layer M1a this is placed For the second metal layer M2, Cu is used when the first metal layer M1 is MoTi, and Mo is used when the first metal layer M1 is AlNd. The line width of the second metal layer M2 is formed to be the same as that of the 1-1th metal layer M1a. The 1-1th metal layer M1a extends from the thin film transistor TFT formation region toward the pixel region to form the source electrode SE.

According to this configuration, each of the data lines D1 and D2 has three layers of the second metal layer M2, the 1-1 metal layer M1a, and the 1-1 impurity region A1 of the semiconductor layer A. made of structure

First and second insulating films ( INS1 and INS2) are sequentially arranged. The first and second insulating layers INS1 and INS2 are a partial region of the first metal layer M1a of the source electrode SE, a partial region of the first metal layer M1b of the drain electrode DE, and the semiconductor layer A ) includes a first contact hole CH exposing the intrinsic semiconductor region A2 and a second contact hole CH2 exposing the common line CL.

The pixel electrodes Px and DPx and the common electrode COM are disposed on the first and second insulating layers INS1 and INS2 in which the first contact hole CH1 and the second contact hole CH2 are formed.

The pixel electrode is exposed through the first contact hole CH1 and the first pixel electrode Px overlapping the first and second metal layers M1 of the drain electrode DE exposed through the first contact hole CH1. and a second pixel electrode DPx overlapping the 1-1 metal layer M1a of the source electrode SE.

The first pixel electrode Px is connected to the first and second metal layers M1b of the drain electrode DE and extends into the pixel region. The first pixel electrode Px includes a first stem portion PA overlapping the gate line GL, and a plurality of first branch portions Pb extending from the first stem portion Pa to the pixel area. . One end of the first stem Pa of the first pixel electrode Px is aligned with the exposed end of the first and second metal layers M1b of the drain electrode DE.

The second pixel electrode DPx is spaced apart from the first pixel electrode and is disposed adjacent to the pixel region. Also, one end of the second pixel electrode DPx is aligned with the exposed end of the 1-1 metal layer M1a of the source electrode SE. The second pixel electrode DPx is a dummy electrode that does not affect display driving.

The common electrode COM includes a second stem portion Ca disposed to overlap the common line CL, and a plurality of second branch portions Cb extending from the second stem portion Ca to the pixel area. . The second stem Ca of the common electrode COM is connected to the common line CL exposed through the second contact hole CH2. The first branch portions Pb of the first pixel electrode Px and the second branch portions Cb of the common electrode COM are alternately disposed in the same pixel area along the gate line direction to form a horizontal electric field.

The first pixel electrode Px, the second pixel electrode DPx, and the common electrode are formed on the second insulating layer INS2 in which the first pixel electrode Px, the second pixel electrode DPx, and the common electrode COM are disposed. COM) and a protective film PAS is disposed to protect the exposed intrinsic semiconductor region A2 of the semiconductor layer A. The passivation layer PAS is disposed over the entire display area.

The first pixel electrode Px, the second pixel electrode DPx, and the common electrode COM are made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or gallium doped zinc oxide (GZO). to form

According to the horizontal electric field type liquid crystal display according to the second embodiment of the present invention described above, the impurity semiconductor layer A1 and the first metal layer M1 in which the data lines D1 and D2 formed in the wiring portion are respectively conductive. and a triple layer of the second metal layer M2. Accordingly, since the electrical resistance can be reduced by increasing the thickness of the data line, the driving ability of the display device can be increased.

In addition, since the second metal layer M2 and the 1-1 metal layer M1a constituting the data line are formed by different mask processes, the channel length of the thin film transistor is reduced while increasing the thickness of the second metal layer M2. possible effects can be obtained. For example, if the pixel electrodes Px and DPx have a thinner thickness than the second metal layer M2, the etching time can be reduced, thereby reducing the resistance of the data line and reducing the channel length of the thin film transistor. can be obtained

In addition, since the first metal layer M1 of the pixel electrode Px and the drain electrode DE and the first metal electrode M1 of the source electrode SE are made in a single process, an interlayer margin is secured and manufacturing due to misalignment It is possible to obtain the effect of preventing process defects.

In addition, since the pixel electrode made of a transparent conductive material and the second metal layer made of copper do not contact each other, it is possible to prevent a problem of poor adhesion due to the characteristics between the two materials.

Next, a method of manufacturing the horizontal electric field type liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS. 8A to 12B .

First, a first mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS. 8A and 8B .

8A is a plan view illustrating a first mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along line I-I' of FIG. 8A.

8A and 8B , after depositing a first conductive metal material on the transparent substrate SUB, a first photoresist is applied to the entire surface. Thereafter, a first photoresist pattern is formed by performing a photolithography process using a first photomask. Then, the first conductive metal material is etched using the first photoresist pattern as a mask, the first photoresist pattern is removed, and the gate lines GL and the gate are arranged in a first direction (eg, a horizontal direction). A first conductive metal layer including the gate electrode GE included in the line GL is formed.

The first conductive metal includes a low-resistance metal material such as copper (Cu) or aluminum (Al), and a metal material with strong corrosion resistance such as titanium (Ti), nickel (Ni), or molybdenum (Mo). As another example, it may have a structure in which a copper layer and a titanium-molybdenum alloy layer are stacked, a structure in which a molybdenum layer and an aluminum-neodium alloy layer are stacked, or a double-layer structure in which a copper layer and a molybdenum layer are stacked. As another example, it may have a triple-layer structure in which a nickel layer, a copper layer, and a titanium-molybdenum alloy layer are stacked.

Next, a second mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS. 9A and 9B .

FIG. 9A is a plan view illustrating a second mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along line I-I' of FIG. 9A.

9A and 9B, an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is coated on the substrate SUB on which the first conductive metal patterns are formed to form a gate insulating layer GI do. Then, a semiconductor material, a second conductive metal material, and a third conductive material are sequentially coated on the entire surface of the gate insulating film GI, and then the semiconductor layer A and the first metal layer ( M1) and second conductive metal patterns including the second metal layer are formed.

More specifically, the second mask process is performed using a halftone mask. To this end, a second photoresist is coated on the uppermost layer of the semiconductor material sequentially deposited on the gate insulating layer GI, the second conductive metal material, and the third conductive material. A metal material such as Cu or Mo is used as the second conductive metal material, and an alloy material such as TiMo and AlNd is used as the third conductive metal material. Thereafter, a second photoresist pattern is formed by performing a photolithography process using a halftone mask (second photomask). Then, the third conductive material is etched using the second photoresist pattern as a mask, the second conductive material and the semiconductor material are etched, and the second photoresist pattern is removed to form the semiconductor layer (A) and the first metal layer. (M1) and a second metal layer (M2) are formed.

Specifically, since the second conductive material and the third conductive material have different properties, the third conductive material is first selectively etched by first wet etching, and then the second conductive material is subjected to the second wet etching. is selectively etched by The semiconductor layer A is selectively etched by dry etching.

The semiconductor layer A and the first metal layer M1 are disposed in regions where data lines and source and drain electrodes of the thin film transistor are to be formed. The second metal layer M2 becomes an upper metal layer of the data lines D1 and D2. According to this configuration, each of the data lines D1 and D2 has a three-layer structure of the second metal layer M2 , the first metal layer M1 , and the semiconductor layer A .

Next, a third mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS. 10A and 10B .

10A is a plan view illustrating a third mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along line I-I' of FIG. 10A.

10A and 10B, a first insulating layer INS1 made of an inorganic insulating material such as silicon nitride or silicon oxide on the gate insulating layer GI on which the thin film transistor TFT and the data line DL are disposed; A second insulating layer INS2 made of an organic insulating material such as photo acrylic (PAC) is sequentially applied over the entire surface. Then, by performing a photolithography process using a third mask, the second insulating layer is developed after exposure to light, thereby patterning the second insulating layer. Then, using the patterned second insulating layer INS2 as a mask, the first insulating layer INS1 is dry-etched to expose a portion of the first metal layer M1 to form a first contact hole CH1 . The portion of the first metal layer M1 exposed through the first contact hole CH1 is a region in which the source electrode and the drain electrode of the thin film transistor are to be formed.

Next, a fourth mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS. 11A and 11B .

11A is a plan view illustrating a fourth mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along line I-I' of FIG. 11A.

11A and 11B , transparent such as indium tin oxide (ITO), indium zinc oxide (IZO), or gallium doped zinc oxide (GZO) on the second insulating layer INS2 in which the first contact hole CH1 is formed A conductive material and a fourth photoresist are applied over the entire surface. Thereafter, a fourth photoresist pattern is formed by performing a photolithography process using the fourth photomask. Then, using the fourth photoresist pattern as a mask, wet-etching the transparent conductive material and the first metal layer at once, and removing the fourth photoresist pattern, the transparent conductive material is patterned on pixel electrodes (Px, DPx); The first metal layer M1 is patterned to form the divided 1-1 metal layer M1a and the 1-2 metal layer M1b.

The semiconductor layer A is an intrinsic semiconductor region disposed between the impurity semiconductor regions A1 and A3 conductiveized by implanting impurities into the semiconductor material, and the impurity semiconductor regions A1 and A3 and operating as a channel of the thin film transistor. (A2) is included.

The 1-1 metal layer M1a is disposed on the impurity semiconductor region A1 of the semiconductor layer A to overlap the impurity semiconductor region A1, and the 1-2 metal layer M1b is formed in the impurity semiconductor region A3. It is disposed on the impurity semiconductor region A3 of the semiconductor layer A so as to overlap with the semiconductor layer A.

Accordingly, the source electrode SE of the thin film transistor has a two-layer structure of the 1-1 metal layer M1a and the conductive impurity semiconductor region A1 of the semiconductor layer A disposed thereunder. The drain electrode DE of the thin film transistor has a two-layer structure of the first and second metal layers M1b and the conductive impurity semiconductor region A3 of the semiconductor layer A disposed thereunder.

The pixel electrode is exposed through the first contact hole CH1 and the first pixel electrode Px overlapping the first and second metal layers M1b of the drain electrode DE exposed through the first contact hole CH1. and a second pixel electrode DPx overlapping the 1-1 metal layer M1a of the source electrode SE.

The first pixel electrode Px is connected to the first and second metal layers M1b of the drain electrode DE and extends into the pixel region. One end of the first pixel electrode Px is aligned with the exposed end of the first and second metal layers M1b of the drain electrode DE.

The second pixel electrode DPx is spaced apart from the first pixel electrode and is disposed adjacent to the pixel region. Also, one end of the second pixel electrode DPx is aligned with the exposed end of the 1-1 metal layer M1a of the source electrode SE. The intrinsic semiconductor region A2 of the semiconductor layer A is exposed between the first and second pixel electrodes Px and DPx.

Next, a fifth mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS. 12A and 12B .

12A is a plan view illustrating a fifth mask process of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention, and FIG. 12B is a cross-sectional view taken along line I-I' of FIG. 12A.

12A and 12B , on the second insulating layer INS2 on which the pixel electrodes Px and DPx are formed, a protective layer PAS made of an inorganic insulating material such as silicon nitride or silicon oxide, and indium tin oxide (ITO) ), a transparent conductive material such as indium zinc oxide (IZO), gallium doped zinc oxide (GZO), and a fifth photoresist are sequentially coated all over the surface. Thereafter, a fifth photoresist pattern is formed by performing a photolithography process using a fifth photomask. Then, the transparent conductive material is wet-etched using the fifth photoresist pattern as a mask, and the fifth photoresist pattern is removed to form a common electrode COM. The common electrode COM is disposed to overlap the first pixel electrode Px disposed in each pixel region, and has a plurality of openings SL to form a horizontal electric field with the first pixel electrode Px.

According to the manufacturing method of the horizontal electric field type liquid crystal display according to the first embodiment of the present invention as described above, the impurity semiconductor layer A1 in which each of the data lines D1 and D2 formed in the wiring portion is made into a conductor, the first It is composed of a triple layer of a first metal layer (M1) and a second metal layer (M2). Accordingly, since the electrical resistance can be reduced by increasing the thickness of the data line, the driving ability of the display device can be increased.

In addition, since the second metal layer M2 and the 1-1 metal layer M1a constituting the data line are formed by different mask processes, the channel length of the thin film transistor is reduced while increasing the thickness of the second metal layer M2. possible effects can be obtained. For example, if the pixel electrodes Px and DPx have a thinner thickness than the second metal layer M2, the etching time can be reduced, thereby reducing the resistance of the data line and reducing the channel length of the thin film transistor. can be obtained

In addition, since the first metal layer M1 of the pixel electrode Px and the drain electrode DE and the first metal electrode M1 of the source electrode SE are made in a single process, an interlayer margin is secured and manufacturing due to misalignment It is possible to obtain the effect of preventing process defects.

In addition, since the pixel electrode made of a transparent conductive material and the second metal layer made of copper do not contact each other, it is possible to prevent a problem of poor adhesion due to the characteristics between the two materials.

Next, a method of manufacturing a horizontal electric field type liquid crystal display according to a second embodiment of the present invention will be described with reference to FIGS. 13A to 16B .

First, a first mask process of the horizontal electric field type liquid crystal display according to the second embodiment of the present invention will be described with reference to FIGS. 13A and 13B .

13A is a plan view illustrating a first mask process of a horizontal electric field type liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along line II-II′ of FIG. 13A.

13A and 13B , after depositing a first conductive metal material on the transparent substrate SUB, a first photoresist is applied to the entire surface. Thereafter, a first photoresist pattern is formed by performing a photolithography process using a first photomask. Then, by wet etching the first conductive metal material using the first photoresist pattern as a mask, and removing the first photoresist pattern, gate lines arranged in a first direction (eg, a horizontal direction) (G1, G2), the gate electrode GE included in the gate lines G1 and G2, and the common line CL spaced apart from the gate lines G1 and G2 and arranged in parallel with the gate lines G1 and G2 To form a first conductive metal layer comprising a.

The first conductive metal includes a low-resistance metal material such as copper (Cu) or aluminum (Al), and a metal material with strong corrosion resistance such as titanium (Ti), nickel (Ni), or molybdenum (Mo). As another example, it may have a structure in which a copper layer and a titanium-molybdenum alloy layer are stacked, a structure in which a molybdenum layer and an aluminum-neodium alloy layer are stacked, or a double-layer structure in which a copper layer and a molybdenum layer are stacked. As another example, it may have a triple-layer structure in which a nickel layer, a copper layer, and a titanium-molybdenum alloy layer are stacked.

Next, a second mask process of the horizontal electric field type liquid crystal display according to the second embodiment of the present invention will be described with reference to FIGS. 14A and 14B .

14A is a plan view illustrating a second mask process of a horizontal electric field type liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 14B is a cross-sectional view taken along line II-II′ of FIG. 14A.

14A and 14B , an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is applied to the entire surface of the substrate SUB on which the first conductive metal patterns are formed to form a gate insulating layer GI. do. Subsequently, a semiconductor material, a second conductive metal material, and a third conductive material are sequentially coated on the entire surface of the gate insulating layer GI, and then the semiconductor layer A and the first metal layer are formed by a photolithography process using a second mask. Second conductive metal patterns including (M1) and the second metal layer (M2) are formed.

More specifically, the second mask process is performed using a halftone mask. To this end, a second photoresist is entirely coated on the uppermost layer of the semiconductor material, the second conductive metal material, and the third conductive material sequentially deposited on the gate insulating layer GI. A metal material such as Cu or Mo is used as the second conductive metal material, and an alloy material such as TiMo and AlNd is used as the third conductive metal material. Thereafter, a second photoresist pattern is formed by performing a photolithography process using a halftone mask (second photomask). Then, the third conductive material is etched using the second photoresist pattern as a mask, the second conductive material and the semiconductor material are etched, and the second photoresist pattern is removed to form the semiconductor layer (A) and the first metal layer. (M1) and the second metal layer (M2) are formed.

Specifically, since the second conductive material and the third conductive material have different properties, the third conductive material is first selectively etched by first wet etching, and then the second conductive material is subjected to the second wet etching. is selectively etched by The semiconductor layer A is selectively etched by dry etching.

The semiconductor layer A and the first metal layer M1 are disposed in regions where data lines and source and drain electrodes of the thin film transistor are to be formed. The second metal layer M2 becomes an upper metal layer of the data lines D1 and D2. According to this configuration, each of the data lines D1 and D2 has a three-layer structure of the second metal layer M2 , the first metal layer M1 , and the semiconductor layer A .

The semiconductor layer A and the first metal layer M1 are disposed in regions where data lines and source and drain electrodes of the thin film transistor are to be formed. The second metal layer M2 becomes an upper metal layer of the data lines D1 and D2. According to this configuration, each of the data lines D1 and D2 has a three-layer structure of the second metal layer M2 , the first metal layer M1 , and the semiconductor layer A .

Next, a third mask process of the horizontal electric field type liquid crystal display according to the second embodiment of the present invention will be described with reference to FIGS. 15A and 15B .

15A is a plan view illustrating a third mask process of a horizontal electric field type liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along line II-II′ of FIG. 15A.

15A and 15B, a first insulating layer INS1 made of an inorganic insulating material such as silicon nitride or silicon oxide on the gate insulating layer GI on which the thin film transistor TFT and the data line DL are disposed; A second insulating layer INS2 made of an organic insulating material such as photo acrylic (PAC) is sequentially applied over the entire surface. Then, by performing a photolithography process using a third mask, the second insulating layer is developed after exposure to light, thereby patterning the second insulating layer. Then, using the patterned second insulating layer INS2 as a mask, the first insulating layer INS1 is dry-etched to form the first contact hole CH1 and a portion of the second contact hole, and the gate insulating layer GI is dry-etched. A second contact hole CH2 is formed by etching. The first contact hole CH1 exposes a portion of the first metal layer M1 , and the second contact hole CH2 exposes a portion of the common line CL. The portion of the first metal layer M1 exposed through the first contact hole CH1 is a region in which the source electrode and the drain electrode of the thin film transistor are to be formed.

Next, a fourth mask process of the horizontal electric field type liquid crystal display according to the second embodiment of the present invention will be described with reference to FIGS. 16A and 16B .

FIG. 16A is a plan view illustrating a fourth mask process of the horizontal electric field type liquid crystal display according to the second embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along line II-II' of FIG. 16A.

16A and 16B , indium tin oxide (ITO), indium zinc oxide (IZO), and gallium doped (GZO) on the second insulating layer INS2 in which the first and second contact holes CH1 and CH2 are formed A transparent conductive material such as zinc oxide) and a fourth photoresist are coated on the entire surface. Thereafter, a fourth photoresist pattern is formed by performing a photolithography process using the fourth photomask. Then, using the fourth photoresist pattern as a mask, the transparent conductive material and the first metal layer are wet-etched together, and the fourth photoresist pattern is removed to form the transparent conductive material-patterned pixel electrodes (Px, DPx) and the common The electrode COM and the first metal layer M1 are patterned to form the divided 1-1 metal layer M1a and the 1-2 metal layer M1b.

The semiconductor layer A is an intrinsic semiconductor region disposed between the impurity semiconductor regions A1 and A3 conductiveized by implanting impurities into the semiconductor material, and the impurity semiconductor regions A1 and A3 and operating as a channel of the thin film transistor. (A2) is included.

The 1-1 metal layer M1a is disposed on the impurity semiconductor region A1 of the semiconductor layer A to overlap the impurity semiconductor region A1, and the 1-2 metal layer M1b is formed in the impurity semiconductor region A3. It is disposed on the impurity semiconductor region A3 of the semiconductor layer A so as to overlap with the semiconductor layer A.

Accordingly, the source electrode SE of the thin film transistor has a two-layer structure of the 1-1 metal layer M1a and the conductive impurity semiconductor region A1 of the semiconductor layer A disposed thereunder. The drain electrode DE of the thin film transistor has a two-layer structure of the first and second metal layers M1b and the conductive impurity semiconductor region A3 of the semiconductor layer A disposed thereunder.

The pixel electrode is exposed through the first contact hole CH1 and the first pixel electrode Px overlapping the first and second metal layers M1b of the drain electrode DE exposed through the first contact hole CH1. and a second pixel electrode DPx overlapping the 1-1 metal layer M1a of the source electrode SE.

The first pixel electrode Px is connected to the first and second metal layers M1b of the drain electrode DE and extends into the pixel region. The first pixel electrode Px includes a first stem portion PA overlapping the gate line GL, and a plurality of first branch portions Pb extending from the first stem portion Pa to the pixel area. . One end of the first stem Pa of the first pixel electrode Px is aligned with the exposed end of the first and second metal layers M1b of the drain electrode DE.

The second pixel electrode DPx is spaced apart from the first pixel electrode and is disposed adjacent to the pixel region. Also, one end of the second pixel electrode DPx is aligned with the exposed end of the 1-1 metal layer M1a of the source electrode SE. The second pixel electrode DPx is a dummy electrode that does not affect display driving.

The common electrode COM includes a second stem portion Ca disposed to overlap the common line CL, and a plurality of second branch portions Cb extending from the second stem portion Ca to the pixel area. . The second stem Ca of the common electrode COM is connected to the common line CL exposed through the second contact hole CH2. The first branch portions Pb of the first pixel electrode Px and the second branch portions Cb of the common electrode COM are alternately disposed in the same pixel area along the gate line direction to form a horizontal electric field.

Next, on the second insulating layer INS2 on which the first pixel electrode Px, the second pixel electrode DPx, and the common electrode COM are disposed, the first pixel electrode Px, the second pixel electrode DPx, and A passivation layer PAS is disposed to cover the common electrode COM and to protect the exposed intrinsic semiconductor region A2 of the semiconductor layer A. Referring to FIG. The passivation layer PAS is disposed over the entire display area.

According to the manufacturing method of the horizontal electric field type liquid crystal display according to the second embodiment of the present invention as described above, the impurity semiconductor layer A1 formed in each of the data lines D1 and D2 formed in the wiring portion is formed into a conductor, the first It is composed of a triple layer of a first metal layer (M1) and a second metal layer (M2). Accordingly, since the electrical resistance can be reduced by increasing the thickness of the data line, the driving ability of the display device can be increased.

In addition, since the second metal layer M2 and the 1-1 metal layer M1a constituting the data line are formed by different mask processes, the channel length of the thin film transistor is reduced while increasing the thickness of the second metal layer M2. possible effects can be obtained. For example, if the pixel electrodes Px and DPx have a thinner thickness than the second metal layer M2, the etching time can be reduced, thereby reducing the resistance of the data line and reducing the channel length of the thin film transistor. can be obtained

In addition, since the first metal layer M1 of the pixel electrode Px and the drain electrode DE and the first metal electrode M1 of the source electrode SE are made in a single process, an interlayer margin is secured and manufacturing due to misalignment It is possible to obtain the effect of preventing process defects.

In addition, since the pixel electrode made of a transparent conductive material and the second metal layer made of copper do not contact each other, it is possible to prevent a problem of poor adhesion due to the characteristics between the two materials.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

D1, D2: data line G1, G2: gate line
A: semiconductor layer DE: source electrode
GE: gate electrode SE: drain electrode
M1: first metal layer M2: second metal layer
COM: common electrode
Ca: the stem of the common electrode (the first stem)
Cb: branch portion (first branch portion) of the common electrode
Px: first pixel electrode DPx: second pixel electrode
Pa: stem portion of the first pixel electrode (second stem portion)
Pb: branch portion (second branch portion) of the first pixel electrode

Claims (18)

gate lines and data lines disposed to cross each other;
thin film transistors disposed adjacent to intersections of the gate lines and the data lines;
pixel electrodes connected to the data line through the thin film transistor and respectively disposed in pixel areas defined by the gate lines and the data lines; and
a common electrode disposed to form a horizontal electric field with the pixel electrodes;
Each of the data lines includes a first impurity semiconductor region, a 1-1 metal layer, and a second metal layer of a semiconductor layer including a first impurity semiconductor region and a second impurity semiconductor region disposed with an intrinsic semiconductor region therebetween. lose,
The source electrode of the thin film transistor consists of a first impurity semiconductor region of the semiconductor layer, and the 1-1 metal layer,
The drain electrode of the thin film transistor includes a second impurity semiconductor region of the semiconductor layer, and a first and second metal layer spaced apart from the 1-1 metal layer.
The method of claim 1,
the gate line is disposed on a transparent substrate;
The semiconductor layer is disposed on a gate insulating film covering the gate line,
the source electrode is disposed on the first impurity semiconductor region to overlap the first impurity semiconductor region of the semiconductor layer;
and the drain electrode is disposed on the second impurity semiconductor region to overlap the second impurity semiconductor region of the semiconductor layer.
3. The method of claim 2,
and a 1-1 metal layer of the data line and a first impurity semiconductor region of the semiconductor layer extend into a pixel region to form a source electrode of the thin film transistor.
4. The method of claim 3,
The pixel electrode is
a first pixel electrode disposed on the insulating layer to have one end overlapping the second metal layer and the first and second metal layers exposed through an insulating layer that covers the source electrode and the drain electrode exposed through the second metal layer; and
On the insulating layer separated from the first pixel electrode so as to have one end overlapping the 1-1 metal layer exposed through an insulating layer that covers the data line and the source electrode and the drain electrode exposed through the second metal layer A horizontal electric field type liquid crystal display including a second pixel electrode disposed thereon.
5. The method of claim 4,
The common electrode is disposed to overlap the pixel electrode on the pixel electrode and a protective layer disposed on the insulating layer to cover the intrinsic semiconductor region of the semiconductor layer exposed through the pixel electrode,
A horizontal electric field type liquid crystal display having a plurality of openings overlapping the first pixel electrode to form a horizontal electric field with the first pixel electrode.
gate lines and common lines arranged side by side in a first direction adjacent to each other on a substrate;
data lines arranged in a second direction crossing the first direction;
thin film transistors respectively disposed adjacent to intersections of the gate lines and the data lines;
pixel electrodes connected to the data line through the thin film transistors and respectively disposed in pixel areas defined by the gate lines and the data lines; and
and a common electrode connected to the common line and arranged to form a horizontal electric field with the pixel electrode;
Each of the data lines includes a first impurity semiconductor region, a 1-1 metal layer, and a second metal layer of a semiconductor layer including a first impurity semiconductor region and a second impurity semiconductor region disposed with an intrinsic semiconductor region therebetween. lose,
The source electrode of the thin film transistor consists of a first impurity semiconductor region of the semiconductor layer, and the 1-1 metal layer,
The drain electrode of the thin film transistor includes a second impurity semiconductor region of the semiconductor layer, and a first and second metal layer spaced apart from the 1-1 metal layer.
7. The method of claim 6,
the gate line and the common line are disposed on a transparent substrate;
the semiconductor layer is disposed on a gate insulating layer covering the gate line and the common line;
the source electrode is disposed on the first impurity semiconductor region to overlap the first impurity semiconductor region of the semiconductor layer;
and the drain electrode is disposed on the second impurity semiconductor region to overlap the second impurity semiconductor region of the semiconductor layer.
8. The method of claim 7,
and a 1-1 metal layer of the data line and a first impurity semiconductor region of the semiconductor layer extend into a pixel region to form a source electrode of the thin film transistor.
9. The method of claim 8,
The pixel electrode is
It is disposed on the insulating layer to have one end overlapping the second metal layer and the first and second metal layers exposed through the insulating layer that covers the source electrode and the drain electrode exposed through the second metal layer, a first pixel electrode including a first stem disposed on one side and a plurality of branch portions extending from the first stem into the pixel region; and
On the insulating layer separated from the first pixel electrode so as to have one end overlapping the 1-1 metal layer exposed through an insulating layer that covers the data line and the source electrode and the drain electrode exposed through the second metal layer A horizontal electric field type liquid crystal display including a second pixel electrode disposed thereon.
10. The method of claim 9,
The common electrode is disposed on the insulating layer, and includes a second stem disposed on the other side of each pixel area and a plurality of second branches extending from the second stem to the inside of the pixel area,
The second branch portions of the common electrode are alternately disposed with the first branch portions of the pixel electrode.
depositing a first conductive metal material on a substrate and then forming a first conductive metal layer including a gate line and a gate electrode included in the gate line by a photolithography process using a first mask;
A gate insulating layer, a semiconductor material, a second conductive metal material, and a third conductive material are sequentially coated on the substrate on which the first conductive metal layer is formed, and then the semiconductors overlapped with each other by a photolithography process using a second mask of a halftone mask forming second conductive metal patterns including a layer and a first metal layer, and a second metal layer overlapping a portion of the semiconductor layer and the first metal layer;
forming a first contact hole exposing the first metal layer by a photolithography process using a third mask after applying at least one insulating layer on the gate insulating layer on which the second conductive metal patterns are disposed;
After a transparent conductive material is coated on the insulating film in which the first contact hole is formed, the transparent conductive material and the first metal layer are removed at once so that a partial region of the semiconductor layer is exposed by a photolithography process using a fourth mask, The first 1-th pixel electrode having the separated 1-1 metal layer and the 1-2 metal layer, one end overlapping the 1-1 metal layer, and one end overlapping the 1-1 metal layer 2 forming a pixel electrode; and
After sequentially coating a protective film and a transparent conductive material on the 1-1 metal layer and the insulating film on which the 1-1 metal layer is formed, the transparent conductive material is patterned by a photolithography process using a fifth mask. 1 comprising the step of forming a common electrode overlapping the metal layer,
A method of manufacturing a horizontal electric field type liquid crystal display device, wherein the data line includes the semiconductor layer of the second conductive metal pattern, the first metal layer, and the second metal layer.
12. The method of claim 11,
The forming of the second conductive metal patterns includes:
sequentially coating a gate insulating layer, a semiconductor material, a second conductive metal material, and a third conductive material on the substrate on which the first conductive metal layer is formed;
forming a photoresist pattern by using a halftone mask after applying photoresist to the entire surface of the third conductive material; and
The third conductive material is selectively etched by a first wet etch to form a second metal layer, the second conductive material is selectively etched by a second wet etch to form a first metal layer, and the semiconductor layer is etched by dry etching and selectively etching to form the semiconductor layer,
The first metal layer and the semiconductor layer are formed to overlap each other, and extend from a partial region of the second metal layer to a pixel region to form a source electrode of a thin film transistor.
13. The method of claim 12,
The forming of the first contact hole comprises:
sequentially coating a first insulating film and a second insulating film on the gate insulating film;
forming a second insulating layer pattern by exposing and developing the second insulating layer through a photolithography process using the third mask; and
and forming a first contact hole by dry etching the first insulating layer to expose a portion of the first metal layer using the second insulating layer pattern as a mask.
14. The method of claim 13,
the first pixel electrode has an end overlapping the first and second metal layers exposed through the first contact hole;
The method of manufacturing a horizontal electric field type liquid crystal display device, wherein the second pixel electrode has an end overlapping the 1-1 metal layer exposed through the first contact hole.
After depositing a first conductive metal material on a substrate, a first conductive metal layer including a gate line including a gate electrode and a common line disposed in parallel adjacent to the gate line is formed by a photolithography process using a first mask. forming;
A gate insulating layer, a semiconductor material, a second conductive metal material, and a third conductive material are sequentially coated on the substrate on which the first conductive metal layer is formed, and then the semiconductors overlapped with each other by a photolithography process using a second mask of a halftone mask forming second conductive metal patterns including a layer and a first metal layer, and a second metal layer overlapping a portion of the semiconductor layer and the first metal layer;
a first contact hole for exposing the first metal layer by a photolithography process using a third mask after sequentially coating at least a first insulating layer and a second insulating layer on the gate insulating layer on which the second conductive metal patterns are disposed; forming a second contact hole exposing the common line; and
After a transparent conductive material is coated on the second insulating layer in which the first and second contact holes are formed, a photolithography process using a fourth mask is performed to expose a portion of the semiconductor layer to expose the transparent conductive material and the first metal layer. A first pixel electrode having a 1-1 metal layer and a 1-2 metal layer separated from each other by removing at once, a first pixel electrode having one end overlapping the first 1-2 metal layer, and one end overlapping the 1-1 metal layer forming a second pixel electrode and a common electrode disposed to form a horizontal electric field with the first pixel electrode;
A method of manufacturing a horizontal electric field type liquid crystal display device, wherein the data line includes the semiconductor layer of the second conductive metal pattern, the first metal layer, and the second metal layer.
16. The method of claim 15,
The forming of the second conductive metal patterns includes:
sequentially coating a gate insulating layer, a semiconductor material, a second conductive metal material, and a third conductive material on the substrate on which the first conductive metal layer is formed;
forming a photoresist pattern by using a halftone mask after applying photoresist to the entire surface of the third conductive material; and
The third conductive material is selectively etched by a first wet etch to form a second metal layer, the second conductive material is selectively etched by a second wet etch to form a first metal layer, and the semiconductor layer is etched by dry etching and selectively etching to form the semiconductor layer,
The first metal layer and the semiconductor layer are formed to overlap each other, and extend from a partial region of the second metal layer to a pixel region to form a source electrode of a thin film transistor.
17. The method of claim 16,
The forming of the first and second contact holes includes:
sequentially coating a first insulating film and a second insulating film on the gate insulating film;
forming a second insulating layer pattern by exposing and developing the second insulating layer through a photolithography process using the third mask; and
Using the second insulating layer pattern as a mask, the first insulating layer is dry-etched to expose a portion of the first metal layer to form the first contact hole, and the first insulating layer and the common line are partially exposed. and forming the second contact hole by etching a gate insulating layer.
18. The method of claim 17,
the first pixel electrode has an end overlapping with the first and second metal layers exposed through the first contact hole;
the second pixel electrode has an end overlapping with the 1-1 metal layer exposed through the first contact hole;
The common electrode is connected to the common line exposed through the second contact hole.

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