KR20060068442A - Tft substrate for display apparatus and making method of the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate for a display device and a method of manufacturing the same. A thin film transistor substrate for a display device according to the present invention is formed on a substrate, a gate wiring formed on the substrate, the gate wiring including a gate line and a gate electrode, and the same layer as the gate wiring in a direction perpendicular to the extension direction of the gate line. A data line spaced apart from the gate line, an insulating film formed on the gate line and the data line, a bridge wiring formed between the data line adjacent to the insulating film, and the data line and the bridge wiring It characterized in that it comprises a connecting electrode for connecting. As a result, a thin film transistor substrate for a display device having an improved aperture ratio is provided.

Description

Thin film transistor substrate for display device and manufacturing method thereof {TFT SUBSTRATE FOR DISPLAY APPARATUS AND MAKING METHOD OF THE SAME}

1 is a layout view of a thin film transistor substrate according to a first embodiment of the present invention,

2 is a cross-sectional view taken along II-II of FIG. 1,

3A to 6B are views for explaining a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention,

7 is a layout view of main parts of a thin film transistor substrate according to a second exemplary embodiment of the present invention;

8 is a cross-sectional view taken along the line VIII-VIII of FIG. 7.

Explanation of Signs of Major Parts of Drawings

21: gate line 22: gate electrode

23: shift register 31: insulating film

32 semiconductor layer 33 resistive contact layer

34: organic film 41: data line

42: bridge wiring 43: drain electrode

44: data pad portion 51: pixel electrode

52: pad portion protective layer 53: connecting electrode                 

61, 62, 63: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a display device and a method for manufacturing the same, and more particularly, to a thin film transistor substrate for a display device and a method for manufacturing the same, which minimize the capacitance formation between the data line and the pixel electrode and improve the aperture ratio. .

BACKGROUND ART A liquid crystal display device is a device for displaying a screen by using optical anisotropy of a liquid crystal. The liquid crystal display device is excellent in resolution, color display, image quality, and the like, and is actively applied to a notebook or a desktop monitor.

The liquid crystal display is largely comprised of a liquid crystal panel, a backlight unit, a driver, a chassis, and the like. The liquid crystal panel includes a thin film transistor substrate on which a thin film transistor is formed, a color filter substrate on which a color filter is formed, and a liquid crystal layer positioned between both substrates.

In such a liquid crystal display, in order to obtain a high quality display screen, the aperture ratio must be improved. The aperture ratio is the actual light transmission ratio with respect to the area of the pixel electrode.

Wires such as gate lines and data lines are formed on the thin film transistor substrate, and pixel electrodes are formed thereon. An insulating film and / or a protective film are formed between the wiring and the pixel electrode. Specifically, both the insulating film and the protective film are formed between the gate line and the pixel electrode, and only the protective film is formed between the data line and the pixel electrode.                         

The insulating film and the protective film are usually made of silicon nitride (SiNx) and are deposited on the wiring by chemical vapor deposition (CVD). When the wiring and the pixel electrode are close to each other, cross talk occurs because silicon nitride located between the wiring and the pixel electrode having the voltage difference becomes a dielectric to form a capacitance.

The capacitance C formed is represented by C = εA / d, where ε is the dielectric constant of the dielectric (silicon nitride), A is the overlapping area between the wiring and the pixel electrode, and d is the distance between the wiring and the pixel electrode. In the case of the data line, only a protective film exists between the data line and the pixel electrode, so that the distance d is short and thus the capacitance is large.

In order to reduce capacitance formation between the data line and the pixel electrode, the pixel electrode is designed such that the overlapped area A is reduced by a considerable distance from the data line. However, in such a design, there is a problem that the area of the pixel electrode is reduced and the aperture ratio is decreased.

Accordingly, an object of the present invention is to provide a thin film transistor substrate for a display device in which the capacitance formation between the data line and the pixel electrode is reduced and the aperture ratio is improved.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a display device, in which capacitance formation between the data line and the pixel electrode is reduced and the aperture ratio is improved.

The above object is a substrate, a gate wiring formed on the substrate, the gate wiring including a gate line and a gate electrode, and the same layer as the gate wiring, formed in a direction perpendicular to the extension direction of the gate line, and spaced apart from the gate line. A data line, an insulating film formed on the gate wiring and the data line, a bridge wiring formed between the adjacent data lines on the insulating film, and a connection electrode for electrically connecting the data line and the bridge wiring. A thin film transistor substrate for a display device is included.

A protective film having a contact hole for exposing the bridge wire and the data line is formed on the bridge wire, and the connection electrode may electrically connect the bridge wire and the data line through the contact hole.

Preferably, the contact hole is formed in each of the bridge wiring and the data wiring.

Preferably, the insulating film and the protective film are made of silicon nitride.

It is preferable that at least one part of the bridge wiring overlaps with the gate electrode.

It is preferably formed of the same layer as the bridge wiring, and further comprising a drain electrode facing the bridge wiring with the gate electrode therebetween.

It is preferable that the bridge wiring does not overlap the data line.

At least part of the bridge wiring preferably overlaps with the data line.

It is preferable that the said bridge wiring is formed across the said gate line.

It is preferable to further include a pixel electrode formed of the same layer as the connection electrode.

 According to another aspect of the present invention, a gate wiring including a gate line and a gate electrode is formed by depositing and patterning a first wiring material on a substrate, and data formed in a direction perpendicular to the extension direction of the gate line and spaced apart from the gate line. Forming a line, forming an insulating film on the gate wiring and the data line, depositing and patterning a second wiring material on the insulating film to form a bridge wiring crossing the gate line; Forming a passivation layer having a contact hole exposing the bridge line and the data line on the bridge line; depositing and patterning a transparent electrode material on the passivation layer to electrically connect the bridge line and the data line. A thin film transistor substrate for display device comprising the step of forming a connection electrode It is achieved by the method.

Preferably, the contact hole is formed in each of the bridge wiring and the data wiring.

The bridge wiring may be formed to partially overlap the gate electrode.

In the forming of the bridge wiring, it is preferable to further form a drain electrode facing the bridge wiring with the gate electrode therebetween.

It is preferable to form a pixel electrode at the time of forming the connection electrode.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor substrate 1 according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along II-II of FIG. 1.

Gate wirings 21 and 22 are formed on the substrate 11. The gate lines 21 and 22 include a gate line 21 extending in parallel to each other in the horizontal direction and a gate electrode 22 connected to the gate line 21.

The gate lines 21 are connected to shift registers 23 formed on the substrate 11, respectively. The shift register 23 also receives a drive signal from an external circuit (not shown) and serves as a gate driver. The driving signals received include the first clock signal CKV which is a gate-on voltage, the second clock signal CKVB having a phase opposite to that of the first clock signal, the scan start signal STV, and the gate-off voltage V _off . And so on.

The data line 41 and the data pad portion 44 are formed on the same layer as the gate lines 21 and 22. The data line 41 extends in the direction perpendicular to the extension direction of the gate line 21 and is not connected to the gate line 21 back and forth. The data pad unit 44 receives a drive signal from the outside as an extension of the data line 41 and transfers it to the data line 41.

An insulating film 31 made of silicon nitride (SiNx) or the like is formed on the substrate 11, the gate wirings 21 and 22, and the data line 41.

A semiconductor layer 32 made of a semiconductor such as amorphous silicon is formed on the insulating layer 31 of the gate electrode 22, and n + hydrogenation in which the silicide or n-type impurity is heavily doped is formed on the semiconductor layer 32. An ohmic contact layer 33 made of a material such as amorphous silicon is formed. The semiconductor layer 32 is formed like an island on the gate electrode 22, and the ohmic contact layer 33 is divided into two parts around the gate electrode 22.

The bridge wiring 42 and the drain electrode 43 are formed on the ohmic contact layer 33 and the gate insulating film 31. The bridge wiring 42 is positioned between the adjacent data lines 41 and is formed across the gate line 21. The bridge wiring 42 does not overlap the data line 41 but partially overlaps the gate electrode 22. The portion overlapping the gate electrode 22 serves as a source electrode. The drain electrode 43 faces the bridge wiring 42 with the gate electrode 22 therebetween. As described above, the data line 41 and the data pad part 44 of the data wires 41, 42, 43, and 44 are formed of the same layer as the gate wires 21, 22, and the bridge wire 42 and the drain. The electrode 43 is formed of a layer different from the gate wirings 21 and 22 with the insulating film 31 interposed therebetween.

A protective film 34 is formed on the bridge wiring 42 and the drain electrode 43. The protective film 34 is also made of silicon nitride or the like as the insulating film 31. In the passivation layer 34, a contact hole 61 exposing the drain electrode, a contact hole 62 exposing the data pad part 44, and a contact hole 63 exposing the data line 41 and the bridge wiring 43 are formed. have. The insulating film 31 is also removed in the contact hole 62 which exposes the data pad part 44 and the contact hole 63 which exposes the data line 41 among these.

The transparent electrode layers 51, 52, and 53 are formed on the organic layer 34. The transparent electrode layers 51, 52, and 53 are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials. The transparent electrode layers 51, 52, and 53 are in contact with the data pad part 44 through the pixel electrode 51 and the contact hole 62, which are in electrical contact with the drain electrode 43 through the contact hole 61. The pad part protection layer 52 and the connection electrode 53 electrically connecting the data line 41 and the bridge line 43 through the contact hole 63 are included.

In the above structure, the data lines 41 arranged in a line in the vertical direction of the gate line 21 are connected to each other via the bridge line 43 and the connection electrode 53. The signal applied to the data pad unit 44 is transmitted in the order of the data line 41, the connecting electrode 53, the bridge wiring 43, the connecting electrode 53, and the adjacent data line 41.

Here, the pixel electrode 51 is formed wide, and the distance D ₁ between the pixel electrode 51 and the drain line 41 is very small. This will be described with reference to the 'A' part of FIG. 2 as follows. In the first embodiment, both the insulating film 31 and the protective film 34 are positioned between the data line 41 and the pixel electrode 51 unlike in the prior art. In the case where both the insulating film 31 and the protective film 34 are formed of silicon nitride at C =? A / d,? Is the dielectric constant of silicon nitride. On the other hand, d is the sum of the thicknesses of both the insulating film 31 and the protective film 34, so that the capacity C decreases. Accordingly, the pixel electrode 51 can be formed adjacent to the data line 41, so that the aperture ratio is improved. Unlike the embodiment, the pixel electrode 51 may be formed to overlap the data line 41, in which case the aperture ratio is further improved. In addition, since the gate line 21 and the data line 41 are formed in the same layer, a defect due to a short circuit between the gate line 21 and the data line 41 does not occur.

Hereinafter, a method of manufacturing the thin film transistor substrate 1 according to the first embodiment of the present invention will be described with reference to FIGS. 3A to 6B. 3A, 4A, 5A, and 6A are layout views of main parts according to manufacturing steps, and FIGS. 3B, 4B, 5B, and 6B are cross-sectional views, respectively.

First, as shown in FIGS. 3A and 3B, the first wiring material is deposited on the substrate 11, and then patterned by a photolithography process using a mask to form the gate line 21, the gate electrode 22, and the data line 41. Form. As described above, since the gate line 21 and the data line 41 are simultaneously formed in the same layer, a short circuit does not occur between the gate line 21 and the data line 41.

Next, as shown in FIGS. 4A and 4B, three-layer films of the gate insulating film 31, the semiconductor layer 32, and the ohmic contact layer 33 are sequentially stacked on the gate lines 21 and 22 and the data line 41, and the semiconductors are stacked. The layer 32 and the ohmic contact layer 33 are etched to form an island-like semiconductor layer 32 and an ohmic contact layer 33 on the gate insulating layer 31 on the gate electrode 22.

Next, as shown in FIGS. 5A and 5B, a second wiring material is deposited and patterned by a photolithography process using a mask to bridge bridge wiring 42 formed across the gate lines 21 between adjacent data lines 41. The drain electrode 43 facing the bridge wiring 42 is formed with the gate electrode 22 therebetween. Subsequently, the ohmic contact layer 33, which is not covered by the bridge wiring 42 and the drain electrode 43, is etched to separate both sides of the gate electrode 22, and the semiconductor layer 32 is exposed. Subsequently, in order to stabilize the exposed surface of the semiconductor layer 32, it is preferable to perform an oxygen plasma.

Next, as shown in FIGS. 6A and 6B, a protective film 34 made of a silicon nitride film is formed and patterned to expose the contact hole 61 exposing the drain electrode 43, the data line 41, and the bridge wiring 42. A sphere 63 is formed. Since both the insulating film 31 and the protective film 34 exist on the data line 41, the contact hole 63 exposing the data line 41 is also removed. In this case, when both the insulating layer 31 and the passivation layer 34 are formed of silicon nitride, the same etching conditions may be used.

Subsequently, when the transparent conductive material is deposited and patterned to form the transparent electrode layers 51, 52, and 53, the thin film transistor substrate 1 of FIGS. 1 and 2 is completed. The pixel electrode 51 of the transparent electrode layers 51, 52, 53 is formed adjacent to or overlapping with the data line 41.

Hereinafter, a thin film transistor substrate 1 for a display device according to a second embodiment of the present invention will be described with reference to FIGS. 7 and 8.

7 is a layout view of main parts of the thin film transistor substrate 1 according to the second exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. The following description will focus on parts different from the first embodiment.

The bridge wiring 42 connects adjacent data lines 41 through the connecting electrode 54. In this case, the bridge wiring 42 is partially overlapped with the data line 41. In addition, the contact holes 64 exposing the bridge wiring 42 and the data line 41 are not provided separately from the bridge wiring 42 and the data line 41 but are provided as a single unit. Accordingly, the shape of the connecting electrode 54 is also provided differently from that of the first embodiment.

Similarly, in the second embodiment, the insulating film 31 and the protective film 34 are together between the data line 41 and the pixel electrode 51 (refer to the portion 'B'), thereby reducing the formation of capacitance.

The manufacturing process is similar to that of the first embodiment. However, the process of forming the contact hole 64 for connecting the data line 41 and the bridge wiring 42 is somewhat different. After the protective film 34 is deposited, the photoresist film is applied, and then the photoresist film is patterned to remove the photoresist film at the portion where the contact hole 64 is to be provided. In the subsequent etching, the insulating layer 31 under the bridge wiring 42 is not removed because the bridge wiring 42 serves as a mask. As a result, the edges of the insulating film 31 and the bridge wiring 42 in the region of the contact hole 64 coincide with each other (see section 'C').

The above embodiments may be variously modified. For example, the bridge wiring 42 is not limited to the form crossing the gate line 31, and may be variously modified according to the shape of the thin film transistor. In addition, the bridge wiring 42 and the source electrode may be formed separately to electrically connect them.

The thin film transistor substrate 1 according to the present invention is not limited thereto, but may be used in a display device such as a liquid crystal display device or an organic light emitting diode (OLED).

As described above, according to the present invention, there is provided a thin film transistor substrate for a display device, in which capacitance formation between the data line and the pixel electrode is reduced and the aperture ratio is improved.

In addition, a method of manufacturing a thin film transistor substrate for a display device having improved capacitance by reducing capacitance between the data line and the pixel electrode is provided.

Claims (15)

A substrate; A gate wiring formed on the substrate and including a gate line and a gate electrode; A data line formed on the same layer as the gate line in a direction perpendicular to the extension direction of the gate line and spaced apart from the gate line; An insulating film formed on said gate wiring and said data line; A bridge wiring formed between said data lines adjacent to said insulating film; And a connection electrode electrically connecting the data line and the bridge line. The method of claim 1, On the bridge wiring, a protective film having a contact hole for exposing the bridge wiring and the data line is formed, The connection electrode is a thin film transistor substrate for a display device, characterized in that for electrically connecting the bridge line and the data line through the contact hole. The method of claim 2, The contact hole is a thin film transistor substrate for the display device, characterized in that formed in the bridge wiring and the data wiring, respectively. The method of claim 2, The thin film transistor substrate of claim 1, wherein the insulating layer and the protective layer are made of silicon nitride. The method of claim 1, And at least a portion of the bridge wiring overlaps the gate electrode. The method of claim 1, It is formed of the same layer as the bridge wiring, And a drain electrode facing the bridge line with the gate electrode interposed therebetween. The method of claim 1, And the bridge wiring does not overlap the data line. The method of claim 1, And at least a portion of the bridge wiring overlaps the data line. The method of claim 1, And the bridge wiring is formed across the gate line. The method of claim 1, The thin film transistor substrate of claim 1, further comprising a pixel electrode formed of the same layer as the connection electrode. Depositing and patterning a first wiring material on a substrate to form a gate wiring including a gate line and a gate electrode, and a data line formed in a direction perpendicular to the extending direction of the gate line and spaced apart from the gate line; Forming an insulating film on the gate line and the data line; Depositing and patterning a second wiring material on the insulating layer to form a bridge wiring crossing the gate line; Forming a protective film on the bridge wiring, the protective film having a contact hole for exposing the bridge wiring and the data line; And depositing and patterning a transparent electrode material on the passivation layer to form a connection electrode electrically connecting the bridge line and the data line. The method of claim 11, And the contact hole is formed in the bridge wiring and the data wiring, respectively. The method of claim 11, The bridge wiring is formed to overlap with the gate electrode, the method of manufacturing a thin film transistor substrate for a display device. The method of claim 11, In the step of forming the bridge wiring, And forming a drain electrode facing the bridge line with the gate electrode interposed therebetween. The method of claim 11, And forming a pixel electrode at the time of forming the connection electrode.

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