CN101393364A - TFT LCD pixel structure and method for manufacturing same - Google Patents
TFT LCD pixel structure and method for manufacturing same Download PDFInfo
- Publication number
- CN101393364A CN101393364A CNA2007101221586A CN200710122158A CN101393364A CN 101393364 A CN101393364 A CN 101393364A CN A2007101221586 A CNA2007101221586 A CN A2007101221586A CN 200710122158 A CN200710122158 A CN 200710122158A CN 101393364 A CN101393364 A CN 101393364A
- Authority
- CN
- China
- Prior art keywords
- sweep trace
- drain electrode
- signal wire
- ohmic contact
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Abstract
The present invention discloses a TFT LCD pixel structure, which comprises a substrate, and a grid scan line, a grid electrode, a signal wire, a source electrode and a drain electrode which are formed on the substrate, wherein the grid scan line or the signal line is disconnected at the junction of the grid scan line and the signal line; an insulating layer covers the upper parts of the grid scan line, the grid electrode, the signal wire, the source electrode and the drain electrode; connection through holes are formed on two ends of the disconnecting position of the grid scan line or the signal wire, and connection through holes are formed on the source electrode and the drain electrode; an active layer and an ohmic contact layer are sequentially formed on the insulating layer above the grid electrode and are connected with the source electrode and the drain electrode via the connection through holes; a pixel electrode is connected with the drain electrode; the structure also comprises a protecting layer of the ohmic contact layer and a channel; and connection lines of the grid scan line and the signal line connect the disconnected grid scan line or the disconnected signal line via the connection through holes. The present invention also discloses a method for manufacturing the TFT LCD pixel structure. The method can simplify the process flow, improve the utilization ratio of the material and reduce waste.
Description
Technical field
The present invention relates to Thin Film Transistor-LCD (TFT LCD), relate in particular to the dot structure and the manufacture method thereof of TFT thin film transistor monitor.
Background technology
In the present TFT-LCD factory, adopt 5mask technology for the manufacturing of array more.Its concrete processing procedure is:
At first, use magnetically controlled sputter method, preparation one layer thickness is 1000 on the glass array substrate
To 7000
The grid metallic film, the grid metal material uses metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually, also can use the combination of above-mentioned different materials film, with the gate mask version by exposure technology and chemical etching technology, on certain zone of glass array substrate grid metallic film etching is formed certain pattern, this pattern comprises controlling grid scan line, grid.
Then, utilize the deposit 1000 on the array base palte of the pattern of finishing controlling grid scan line and grid of chemical vapor deposited method
To 6000
The gate insulator layer film, as gate insulator.The material of gate insulator is silicon nitride normally, also can use monox and silicon oxynitride etc., utilizes the method consecutive deposition 1000 of chemical vapor deposition again
To 6000
Active layer film and 1000
To 6000
Ohmic contact layer.By exposure technique and dry etching technology ohmic contact layer and active layer film are carried out etching with the active layer mask, form the silicon island, the gate insulator between grid metal and the active layer film has played the effect that stops etching at this moment, and the silicon island is positioned on the grid.
Then, adopt and the similar method of preparation grid metallic film, on array base palte, be similar to the thickness of grid metal 1000 with magnetically controlled sputter method deposition one deck
To 7000
Metallic film, the signal wire metal level, the mask by source, drain electrode adopts exposure technique and chemical corrosion technology etching to form signal wire, source electrode and drain electrode on the grid metallic film again;
Subsequently, with and prepare gate insulator and the similar method of active layer, on whole array base palte the employing process for chemical vapor deposition of materials with via deposit a layer thickness 1000
To 6000
Passivation layer, its material is silicon nitride normally, again by the passivation layer mask, utilizes exposure technique etching on passivation layer to form via hole, via hole is in drain electrode.
At last, adopt the magnetically controlled sputter method deposit to form pixel electrode layer, use the mask of pixel electrode,, form pixel electrode by the exposure etching technics.Pixel electrode links to each other with the drain electrode of signal metal layer by the via hole in the drain electrode.Transparent pixels electrode commonly used is ITO, and thickness is 100
To 1000
Between
In sum, need altogether 7 layers of deposition grid metal level, gate insulation layer, active layer, ohmic contact layer, signal wire metal level, passivation layer and pixel electrode layers in the prior art.Need be grid Mask, active layer Mask, signals layer Mask, passivation layer mask and pixel electrode layer Mask totally 5 times.
Prior art need deposit film 7 times, is 5 mask (for 5mask technology). and technology is loaded down with trivial details, waste material.
Summary of the invention
The objective of the invention is provides a kind of TFT LCD dot structure and manufacture method thereof in order to overcome the defective of prior art.The present invention has only deposited film 5 times by front and back, has done mask 4 times, obtains the TFTLCD dot structure, thereby simplifies technological process, improves the utilization factor of material, cuts the waste.
To achieve these goals, the invention provides a kind of TFT LCD dot structure, comprising:
One substrate;
One grid sweep trace, grid, signal wire, source electrode and drain electrode are formed on the described substrate, and wherein grid sweep trace or signal wire disconnect in the position that described grid sweep trace and signal wire intersect;
One insulation course covers described grid sweep trace, grid, signal wire, source electrode and drain electrode top, and forms the connection via hole of grid sweep trace or signal wire at the two ends of described grid sweep trace or signal wire open position; On the insulation course above the described drain electrode, be formed with the via hole that drain electrode is connected with pixel electrode; Described source electrode with the drain electrode on be formed with the via hole that source-drain electrode is connected with ohmic contact layer;
One active layer and ohmic contact layer are formed on the insulation course of described grid top successively, and described ohmic contact layer is connected with drain electrode with described source electrode by the via hole that described source-drain electrode is connected with ohmic contact layer;
One pixel electrode is formed on the insulation course of the pixel cell that defines after described grid sweep trace and signal wire intersect, and is connected with drain electrode by the via hole that described drain electrode is connected with pixel electrode;
The protective seam of one ohmic contact layer is formed on described ohmic contact layer top;
One raceway groove blocks described ohmic contact layer; And
The connecting line of one grid sweep trace or signal wire, the connection via hole by described grid sweep trace or signal wire couples together grid sweep trace or the signal wire that disconnects.
In the such scheme, the material of described grid sweep trace, grid, signal wire, source electrode and drain electrode is identical.The material of the connecting line of described grid sweep trace or signal wire, the protective seam of ohmic contact layer and pixel electrode is identical.Remain with active layer and ohmic contact layer on the insulation course of the connecting line below of described grid sweep trace or signal wire.The material of described grid sweep trace, grid, signal wire, source electrode or drain electrode is molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper.The material of described insulation course is oxide, nitride or oxynitrides.
To achieve these goals, the present invention provides a kind of TFT LCD one pixel structure process method simultaneously, comprising:
In the such scheme, when composition forms the silicon island of ohmic contact layer in the described step 3, connect between the via hole composition at described grid sweep trace or signal wire and form the connecting line figure and expose the grid sweep trace or signal wire connects via hole, and in described step 4, make composition form grid sweep trace or signal line linking line be positioned at described connecting line figure above.The material that described step 1 composition forms grid sweep trace, grid, signal wire, source electrode and drain electrode is molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper.The material of the insulating layer of thin-film of deposition is oxide, nitride or oxynitrides in the described step 2.
Need deposit film 7 times with respect to prior art, be 5 mask (for 5mask technology). technology is loaded down with trivial details, waste material, the present invention has only deposited metal level and primary insulation layer, used mask 4 times, reduced material consumption greatly, shortened process has reduced the production cost of TFT.
Description of drawings
Fig. 1 is the vertical view of TFT LCD dot structure specific embodiment 1 of the present invention;
Fig. 2 is the sectional view at A-A ' position among Fig. 1;
Fig. 3 is the sectional view at the position of B-B ' among Fig. 1;
Fig. 4 is the vertical view after ground floor metal level composition is finished in the method for making of the specific embodiment of the invention 1;
Fig. 5 is the sectional view at A-A ' position among Fig. 4;
Fig. 6 is the sectional view at the position of B-B ' among Fig. 4;
Fig. 7 is the vertical view after composition is finished behind depositing insulating layer and the active layer in the method for making of the specific embodiment of the invention 1;
Fig. 8 is the sectional view at A-A ' position among Fig. 7;
Fig. 9 is the sectional view at the position of B-B ' among Fig. 7;
Figure 10 is the vertical view that etches away in the method for making of the specific embodiment of the invention 1 behind the via hole place insulation course;
Figure 11 is the sectional view at A-A ' position among Figure 10;
Figure 12 is the sectional view at the position of B-B ' among Figure 10;
Figure 13 is the vertical view after composition is finished behind the deposition ohmic contact layer in the method for making of the specific embodiment of the invention 1;
Figure 14 is the sectional view at A-A ' position among Figure 13;
Figure 15 is the sectional view at the position of B-B ' among Figure 13;
Figure 16 is the vertical view after composition is finished behind the deposit transparent electrode layer in the method for making of the specific embodiment of the invention 1;
Figure 17 is the sectional view at A-A ' position among Figure 16;
Figure 18 is the sectional view at the position of B-B ' among Figure 16;
Figure 19 is the vertical view of TFT LCD dot structure specific embodiment 2 of the present invention;
Figure 20 is the sectional view at A-A ' position among Figure 19;
Figure 21 is the sectional view at the position of B-B ' among Figure 19;
Figure 22 is the vertical view after ground floor metal level composition is finished in the method for making of the specific embodiment of the invention 2;
Figure 23 is the sectional view at A-A ' position among Figure 22;
Figure 24 is the sectional view at the position of B-B ' among Figure 22;
Figure 25 is the vertical view after composition is finished behind depositing insulating layer and the active layer in the method for making of the specific embodiment of the invention 2;
Figure 26 is the sectional view at A-A ' position among Figure 25;
Figure 27 is the sectional view at the position of B-B ' among Figure 25;
Figure 28 is the vertical view that etches away in the method for making of the specific embodiment of the invention 2 behind the via hole place insulation course;
Figure 29 is the sectional view at A-A ' position among Figure 28;
Figure 30 is the sectional view at the position of B-B ' among Figure 28;
Figure 31 is the vertical view after composition is finished behind the deposition ohmic contact layer in the method for making of the specific embodiment of the invention 2;
Figure 32 is the sectional view at A-A ' position among Figure 31;
Figure 33 is the sectional view at the position of B-B ' among Figure 31;
Figure 34 is the vertical view after composition is finished behind the deposit transparent electrode layer in the method for making of the specific embodiment of the invention 2;
Figure 35 is the sectional view at A-A ' position among Figure 34;
Figure 36 is the sectional view at the position of B-B ' among Figure 34.
Identify among the figure: 1, signal wire; 2, grid sweep trace; 3, source electrode; 4, drain electrode; 5, grid; 6, insulation course; 7, the grid sweep trace connects via hole; 71, signal wire connects via hole; 8, the via hole that is connected with ohmic contact layer of source-drain electrode; 9, the via hole that is connected with pixel electrode of drain electrode; 10, ohmic contact layer; 11, pixel electrode; 12, grid sweep trace connecting line; 121, signal line linking line; 13, the protective seam of ohmic contact layer; 14, active layer; 15, raceway groove.
Embodiment
Below in conjunction with description of drawings and first-selected specific embodiment, the present invention is further elaborated.
Fig. 1 is the vertical view of TFT LCD dot structure specific embodiment 1 of the present invention; Fig. 2 is the sectional view at A-A ' position among Fig. 1; Fig. 3 is the sectional view at the position of B-B ' among Fig. 1.As Fig. 1, Fig. 2 and shown in Figure 3, dot structure of the present invention comprises: substrate, be formed on grid sweep trace 2 and signal wire 1 on the substrate, grid sweep trace 2 and signal wire 1 are in in one deck structure, and grid sweep trace 2 disconnects in the position that intersects with signal wire 1, the grid sweep trace that is formed with insulation course 6 at the two ends of the grid sweep trace 2 that disconnects connects via hole 7, and the grid sweep trace 2 of disconnection connects via hole 7 by the grid sweep trace to be realized being connected with grid sweep trace connecting line 12.Grid sweep trace 2 and pixel cell of signal wire 1 intersection definition, each pixel cell comprises: film transistor device and pixel electrode 11.Wherein film transistor device comprises grid 5 (for the branch of grid sweep trace 2); Source electrode 3; The drain electrode 4 (with data line 3 be one); Insulation course 6, insulating effect is played in the top of cover gate 5, source electrode 3 and the metal-layer structures such as 4 that drain, and on source electrode 3 and the insulation course of drain electrode above 4, be formed with the via hole 8 that source-drain electrode is connected with ohmic contact layer, on the insulation course that drains above 4, be formed with the via hole 9 that drains and be connected with pixel electrode; Active layer 14 and ohmic contact layer 10 are formed on the insulation course 6 on the grid 5 successively, and ohmic contact layer 10 is connected with source-drain electrode by the via hole 8 that source-drain electrode is connected with ohmic contact layer; Raceway groove 15 blocks ohmic contact layer 10; The protective seam 13 of ohmic contact layer covers on the ohmic contact layer 10.Pixel electrode 11 is connected with drain electrode 4 by the via hole 9 that drain electrode is connected with pixel electrode.
The protective seam 13 of above-mentioned grid sweep trace connecting line 12, ohmic contact layer is identical with the material of pixel electrode 11, and can further below grid sweep trace connecting line 12, remain with active layer 14 and ohmic contact layer 10, can strengthen the distance between grid sweep trace connecting line 12 and the signal wire 1 like this, reduce the generation of stray capacitance; And the active layer below keeping or and ohmic contact layer, can make the following smooth as far as possible of connecting line, otherwise broken string easily.Scheme as an alternative, the below of grid sweep trace connecting line 12 also can not keep active layer 14 and ohmic contact layer 10.
Above-mentioned signal wire 1, source electrode 3 can be metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper with the material of drain electrode 4, grid sweep trace 2 and grid 5.Insulating layer material is silicon nitride normally, also can use monox and silicon oxynitride etc.
Above-mentioned TFT LCD array base palte can be finished by following method manufacturing.
At first, use magnetically controlled sputter method, preparation one layer thickness exists on glass substrate
Extremely
Metallic film.This metal material uses metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually.Also can use the combination of above-mentioned different materials film.With mask by exposure technology and chemical etching technology, (this grid sweep trace 2 is divided into sectional by signal wire 1 to form grid sweep trace 2 on certain zone of glass substrate, can utilize transparent conductive material to connect in the back operation), grid 5, signal wire 1, source electrode 3 and 4 the pattern of draining, the vertical view of finishing a pixel region after the making as shown in Figure 4, the sectional view at its A-A ' position and B-B ' position is respectively as shown in Figure 5 and Figure 6.
Then, utilize method consecutive deposition on array base palte of chemical vapor deposition
Arrive
Insulation course 6 films and
Arrive
Active layer 14 films.Insulating layer material is silicon nitride normally, also can use monox and silicon oxynitride etc.With the mask of the active layer back of exposing the active layer film is carried out etching, form that the grid sweep trace connects via hole 7, source-drain electrode is connected via hole 8 and is connected via hole 9 with pixel electrode with drain electrode with ohmic contact layer.And the insulation course 6 between metal level and the active layer 14 plays the effect that stops etching.The vertical view of a pixel region after completing as shown in Figure 7, the sectional view at its A-A ' position and B-B ' position is respectively as Fig. 8 and shown in Figure 9.
Next, do not use mask, the insulation course that will expose with the mode of doing quarter etches away, they comprise that the grid sweep trace connects via hole 7, source-drain electrode and is connected via hole 8 and drain electrode are connected via hole 9 positions with pixel electrode insulation course with ohmic contact layer, the underlying metal of these positions just comes out like this, uses for connecting in the subsequent technique.The vertical view of a pixel region after completing as shown in figure 10, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 11 and shown in Figure 12.
Subsequently, the method with chemical vapor deposition deposits one deck again
Arrive
Ohmic contact layer 10, utilize mask to form the silicon island of ohmic contact layer.At via hole 8 places that source-drain electrode is connected with ohmic contact layer, ohmic contact layer will be connected with underlying metal by the via hole 8 that source-drain electrode is connected with ohmic contact layer; And connect via hole 7 places at the grid sweep trace; ohmic contact layer 10 (as N+ silicon) does not enter via hole; only cover the via hole center section; play the effect of protection via hole intermediate insulating layer and active layer; and owing to have active layer and ohmic contact layer to exist on the insulation course; can increase the distance between grid sweep trace connecting line and the signal wire during follow-up formation grid sweep trace connecting line, reduce the stray capacitance between the two.In this step, the active layer that is covered by ohmic contact layer will not be etched away yet.The vertical view of a pixel region after completing as shown in figure 13, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 14 and shown in Figure 15.
After finishing top step, deposit the layer of transparent electrode again, transparency electrode commonly used is ITO, and thickness exists
Extremely
Between.Use the mask of transparency electrode, form pixel electrode 11, be connected via hole 9 with pixel electrode by drain electrode pixel electrode 11 and drain electrode 4 are coupled together; Grid sweep trace connecting line 12, it couples together by the grid sweep trace of grid sweep trace connection via hole 7 with segmentation; The protective seam 13 of ohmic contact layer becomes two independently transparent electrode layers on the silicon island of ohmic contact layer, only the center section 15 of the silicon island of ohmic contact layer is exposed.The vertical view of a pixel region after completing as shown in figure 16, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 17 and shown in Figure 180.
At last, do not use mask, use the method for doing quarter will be exposed to outer ohmic contact layer, promptly raceway groove 15 places etch away, and it is carved break, until the active layer that exposes under it.The vertical view of the pixel region after completing as shown in Figure 1, the sectional view at its A-A ' position and B-B ' position is respectively as shown in Figures 2 and 3.
Figure 19 is the vertical view of TFT LCD dot structure specific embodiment 2 of the present invention; Figure 20 is the sectional view at A-A ' position among Figure 19; Figure 21 is the sectional view at the position of B-B ' among Figure 19.As Figure 19, Figure 20 and shown in Figure 21, dot structure of the present invention comprises: substrate, be formed on grid sweep trace 2 and signal wire 1 on the substrate, grid sweep trace 2 and signal wire 1 are in in one deck structure, and signal wire 1 disconnects in the position that intersects with grid sweep trace 2, the signal wire that is formed with insulation course 6 at the two ends of the signal wire 1 that disconnects connects via hole 71, and the signal wire 1 of disconnection connects via hole 71 by signal wire to be realized being connected with signal line linking line 121.Grid sweep trace 2 and pixel cell of signal wire 1 intersection definition, each pixel cell comprises: film transistor device and pixel electrode 11.Wherein film transistor device comprises grid 5 (for the branch of grid sweep trace 2); Drain electrode 4; Source electrode 3 (with data line 3 be one); Insulation course 6, insulating effect is played in the top of metal-layer structures such as cover gate 5, source electrode 3, drain electrode 4, and on source electrode 3 and the insulation course of drain electrode above 4, be formed with the via hole 8 that source-drain electrode is connected with ohmic contact layer, on the insulation course that drains above 4, be formed with the via hole 9 that drains and be connected with pixel electrode; Active layer 14 and ohmic contact layer 10 are formed on the insulation course 6 on the grid 5 successively, and ohmic contact layer 10 is connected with source-drain electrode by the via hole 8 that source-drain electrode is connected with ohmic contact layer; Raceway groove 15 blocks ohmic contact layer 10; The protective seam 13 of ohmic contact layer covers on the ohmic contact layer 10.Pixel electrode 11 is connected with drain electrode 4 by the via hole 9 that drain electrode is connected with pixel electrode.
The protective seam 13 of above-mentioned signal line linking line 121, ohmic contact layer is identical with the material of pixel electrode 11; and the below of signal line linking line 121 keeps active layer 14 and ohmic contact layer 10; can strengthen the distance between signal line linking line 121 and the grid sweep trace 1 like this; reduce the generation of stray capacitance; and the active layer below keeping or and ohmic contact layer; can make the following smooth as far as possible of connecting line, otherwise break easily.Scheme as an alternative, the below of signal line linking line 121 also can not remain with active layer and ohmic contact layer 10.
Above-mentioned signal wire 1, source electrode 3 can be metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper with the material of drain electrode 4, grid sweep trace 2 and grid 5.Insulating layer material is silicon nitride normally, also can use monox and silicon oxynitride etc.
Above-mentioned TFT LCD array base palte can be finished by following method manufacturing.
At first, use magnetically controlled sputter method, preparation one layer thickness exists on glass substrate
Extremely
Metallic film.This metal material uses metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually.Also can use the combination of above-mentioned different materials film.With mask by exposure technology and chemical etching technology, on certain zone of glass substrate, form controlling grid scan line 2, grid 5, (signal wire 1 is divided into sectional signal wire 1 by controlling grid scan line, can utilize transparent conductive material to connect in the back operation), source electrode 3 and 4 the pattern of draining, the vertical view of finishing a pixel region after the making as shown in figure 22, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 23 and shown in Figure 24.
Then, utilize method consecutive deposition on array base palte of chemical vapor deposition
Arrive
Insulation course 6 films and
Arrive
Active layer 14 films.Insulating layer material is silicon nitride normally, also can use monox and silicon oxynitride etc.With the active mask layer by layer back of exposing active layer is carried out etching, form that signal wire connects via hole 71, source-drain electrode is connected via hole 8 and is connected via hole 9 with pixel electrode with drain electrode with ohmic contact layer.And the insulation course 6 between metal level and the active layer 14 plays the effect that stops etching.The vertical view of a pixel region after completing as shown in figure 25, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 26 and shown in Figure 27.
Next, do not use mask, the insulation course that will expose with the mode of doing quarter etches away, they comprise that signal wire connects via hole 71, source-drain electrode and is connected via hole 8 and drain electrode are connected via hole 9 positions with pixel electrode insulation course with ohmic contact layer, the underlying metal of these positions just comes out like this, uses for connecting in the subsequent technique.The vertical view of a pixel region after completing as shown in figure 28, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 29 and shown in Figure 30.
Subsequently, the method with chemical vapor deposition deposits one deck again
Arrive
Ohmic contact layer, utilize mask to form the silicon island of ohmic contact layer.At via hole 8 places that source-drain electrode is connected with ohmic contact layer, ohmic contact layer will be connected with underlying metal by via hole; And connecting via hole 71 places at signal wire, ohmic contact layer (as N+ silicon) does not enter via hole, only covers the via hole center section, plays the effect of protection via hole intermediate insulating layer and active layer.The vertical view of a pixel region after completing as shown in figure 31, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 32 and shown in Figure 33.
After finishing top step, deposit the layer of transparent electrode again, transparency electrode commonly used is ITO, and thickness exists
Extremely
Between.Use the mask of transparency electrode, form pixel electrode 11, be connected via hole 9 with pixel electrode by drain electrode pixel electrode 11 and drain electrode 4 are coupled together; Signal line linking line 121, it couples together by the signal wire of signal wire connection via hole 71 with segmentation; The protective seam 13 of ohmic contact layer becomes an independently transparent electrode layer on the silicon island of ohmic contact layer, only the center section 15 of the silicon island of ohmic contact layer is exposed.The vertical view of a pixel region after completing as shown in figure 34, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 35 and shown in Figure 36.
At last, do not use mask, use the method for doing quarter will be exposed to outer ohmic contact layer, promptly raceway groove 15 places etch away, and it is carved break, until the active layer that exposes under it.The vertical view of the pixel region after completing as shown in figure 19, the sectional view at its A-A ' position and B-B ' position is respectively as Figure 20 and shown in Figure 21.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (10)
1, a kind of TFT LCD dot structure is characterized in that, comprising:
One substrate;
One grid sweep trace, grid, signal wire, source electrode and drain electrode are formed on the described substrate, and wherein said grid sweep trace or signal wire disconnect in the position that grid sweep trace and signal wire intersect;
One insulation course covers described grid sweep trace, grid, signal wire, source electrode and drain electrode top, and forms grid sweep trace or signal wire connection via hole at the two ends of described open position; On the insulation course above the described drain electrode, be formed with the via hole that drain electrode is connected with pixel electrode; Described source electrode with the drain electrode on be formed with the via hole that source-drain electrode is connected with ohmic contact layer;
One active layer and ohmic contact layer are formed on the insulation course of described grid top successively, and described ohmic contact layer is connected via hole by described source-drain electrode and is connected with draining with described source electrode with ohmic contact layer;
One pixel electrode is formed on the insulation course of the pixel cell that defines after described grid sweep trace and signal wire intersect, and is connected with drain electrode by the via hole that described drain electrode is connected with pixel electrode;
The protective seam of one ohmic contact layer is formed on described ohmic contact layer top;
One raceway groove blocks described ohmic contact layer; And
The connecting line of one grid sweep trace or signal wire, the connection via hole by described grid sweep trace or signal wire couples together grid sweep trace or the signal wire that disconnects.
2, dot structure according to claim 1 is characterized in that: the material of described grid sweep trace, grid, signal wire, source electrode and drain electrode is identical.
3, dot structure according to claim 1 is characterized in that: the material of the connecting line of described grid sweep trace or signal wire, the protective seam of ohmic contact layer and pixel electrode is identical.
4, dot structure according to claim 1 is characterized in that: remain with active layer and ohmic contact layer on the insulation course of the connecting line below of described grid sweep trace or signal wire.
5, according to the arbitrary described dot structure of claim 1 to 4, it is characterized in that: the material of described grid sweep trace, grid, signal wire, source electrode or drain electrode is molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper.
6, according to the arbitrary described dot structure of claim 1 to 4, it is characterized in that: the material of described insulation course is oxide, nitride or oxynitrides.
7, a kind of TFT LCD one pixel structure process method is characterized in that, comprising:
Step 1 is used magnetically controlled sputter method, prepares metallic film on substrate, forms grid sweep trace, grid, signal wire, source electrode and drain electrode by composition, and wherein said grid sweep trace or signal wire disconnect in the position that grid sweep trace and signal wire intersect;
Step 2, utilize the insulating layer of thin-film and the active layer film of method successive sedimentation on the substrate of completing steps 1 of chemical vapor deposition, composition forms the grid sweep trace or signal wire connects via hole, source-drain electrode is connected via hole and is connected via hole with drain electrode with pixel electrode with ohmic contact layer, and wherein said insulation course plays the effect that stops etching; Then, with the mode of do carving described grid sweep trace or signal wire are connected via hole, source-drain electrode and is connected via hole with ohmic contact layer and is connected the insulation course that is exposing in the via hole with pixel electrode with drain electrode and etches away, expose described grid sweep trace or signal wire connection via hole, source-drain electrode and be connected via hole and drain electrode with ohmic contact layer and be connected grid sweep trace or signal wire, source electrode and drain electrode below the via hole with pixel electrode;
Step 3, method with chemical vapor deposition deposits the Ohmic contact layer film on the substrate of completing steps 2, composition forms the silicon island of ohmic contact layer, makes described ohmic contact layer be connected via hole with ohmic contact layer by described source-drain electrode and is connected with drain electrode with described source electrode;
Step 4, deposit transparent electrode material layer on the substrate of completing steps 3, the protective seam of composition formation pixel electrode, ohmic contact layer, and grid sweep trace or signal line linking line wherein make described pixel electrode be connected via hole by described drain electrode with pixel electrode and described drain electrode couples together; Making described grid sweep trace or signal line linking line connect via hole by described grid sweep trace or signal wire couples together grid sweep trace and the signal wire that disconnects; The protective seam that makes described ohmic contact layer exposes the center section of described ohmic contact layer, and will be exposed to outer ohmic contact layer and etch away with doing the method for carving.
8, manufacture method according to claim 7, it is characterized in that: when composition forms the silicon island of ohmic contact layer in the described step 3, connect between the via hole composition at described grid sweep trace or signal wire and form the connecting line figure and expose the grid sweep trace or signal wire connects via hole, and in described step 4, make composition form grid sweep trace or signal line linking line be positioned at described connecting line figure above.
9, according to claim 7 or 8 described manufacture methods, it is characterized in that: the material that described step 1 composition forms grid sweep trace, grid, signal wire, source electrode and drain electrode is molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper.
10, according to claim 7 or 8 described manufacture methods, it is characterized in that: the material of the insulating layer of thin-film of deposition is oxide, nitride or oxynitrides in the described step 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101221586A CN101393364B (en) | 2007-09-21 | 2007-09-21 | TFT LCD pixel structure and method for manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101221586A CN101393364B (en) | 2007-09-21 | 2007-09-21 | TFT LCD pixel structure and method for manufacturing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101393364A true CN101393364A (en) | 2009-03-25 |
| CN101393364B CN101393364B (en) | 2010-06-09 |
Family
ID=40493712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101221586A Active CN101393364B (en) | 2007-09-21 | 2007-09-21 | TFT LCD pixel structure and method for manufacturing same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101393364B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102637684A (en) * | 2012-05-08 | 2012-08-15 | 南京中电熊猫液晶显示科技有限公司 | Array substrate used for display equipment and manufacturing method thereof |
| CN103560113A (en) * | 2013-11-15 | 2014-02-05 | 北京京东方光电科技有限公司 | Array structure and manufacturing method thereof, array substrate and display device |
| CN103915443A (en) * | 2013-04-02 | 2014-07-09 | 上海天马微电子有限公司 | Array substrate, preparation method thereof and liquid crystal display panel |
| KR20180099791A (en) * | 2016-05-20 | 2018-09-05 | 우한 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | Array substrate and manufacturing method thereof |
| WO2019237551A1 (en) * | 2018-06-11 | 2019-12-19 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| WO2020051986A1 (en) * | 2018-09-14 | 2020-03-19 | 惠科股份有限公司 | Display panel and manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI255935B (en) * | 2000-09-13 | 2006-06-01 | Chi Mei Optoelectronics Corp | Method to manufacture address line of flat-panel display having repairing layer, and structure thereof |
| CN1313876C (en) * | 2005-01-19 | 2007-05-02 | 广辉电子股份有限公司 | Method for manufacturing dot structure of thin film transistor liquid crystal display |
| CN100386866C (en) * | 2006-03-22 | 2008-05-07 | 友达光电股份有限公司 | Method for manufacturing pixel array substrate |
-
2007
- 2007-09-21 CN CN2007101221586A patent/CN101393364B/en active Active
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102637684B (en) * | 2012-05-08 | 2014-11-12 | 南京中电熊猫液晶显示科技有限公司 | Array substrate used for display equipment and manufacturing method thereof |
| CN102637684A (en) * | 2012-05-08 | 2012-08-15 | 南京中电熊猫液晶显示科技有限公司 | Array substrate used for display equipment and manufacturing method thereof |
| CN103915443B (en) * | 2013-04-02 | 2018-04-27 | 上海天马微电子有限公司 | A kind of array base palte and preparation method thereof, liquid crystal display device |
| CN103915443A (en) * | 2013-04-02 | 2014-07-09 | 上海天马微电子有限公司 | Array substrate, preparation method thereof and liquid crystal display panel |
| WO2015070610A1 (en) * | 2013-11-15 | 2015-05-21 | 京东方科技集团股份有限公司 | Array structure and manufacturing method therefor |
| CN103560113B (en) * | 2013-11-15 | 2017-02-01 | 北京京东方光电科技有限公司 | Array structure and manufacturing method thereof, array substrate and display device |
| CN103560113A (en) * | 2013-11-15 | 2014-02-05 | 北京京东方光电科技有限公司 | Array structure and manufacturing method thereof, array substrate and display device |
| US10229937B2 (en) | 2013-11-15 | 2019-03-12 | Boe Technology Group Co., Ltd. | Array structure, manufacturing method thereof, array substrate and display device |
| KR20180099791A (en) * | 2016-05-20 | 2018-09-05 | 우한 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | Array substrate and manufacturing method thereof |
| KR102154418B1 (en) | 2016-05-20 | 2020-09-09 | 우한 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | Array substrate and its manufacturing method |
| WO2019237551A1 (en) * | 2018-06-11 | 2019-12-19 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| US10964768B1 (en) | 2018-06-11 | 2021-03-30 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel |
| WO2020051986A1 (en) * | 2018-09-14 | 2020-03-19 | 惠科股份有限公司 | Display panel and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101393364B (en) | 2010-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100462825C (en) | Array base board structure of thin film transistor liquid crystal display and its producing method | |
| CN100517075C (en) | Manufacturing method for array substrate of thin film transistor LCD | |
| CN100466182C (en) | Manufacturing method of plain conductor, electrode and thin-film transistor array substrate | |
| CN100483232C (en) | TFT LCD array substrate structure and its production method | |
| CN101393364B (en) | TFT LCD pixel structure and method for manufacturing same | |
| CN100466266C (en) | A TFT LCD array base plate and manufacture method | |
| CN100454558C (en) | TFT matrix structure and making method thereof | |
| US11114474B2 (en) | Thin film transistor, manufacturing method thereof, array substrate, and display panel | |
| CN102033343B (en) | Array substrate and manufacturing method thereof | |
| CN101539697B (en) | Thin-film transistor liquid crystal display pixel structure and manufacturing method thereof | |
| CN100587573C (en) | TFT-LCD array base-plate structure and manufacture method thereof | |
| CN1996603A (en) | Pixel structure of a thin film transistor LCD and its making method | |
| CN101097928A (en) | Thin film transistor array substrate and method of fabricating the same | |
| CN101359669B (en) | TFT LCD array substrate construction and manufacturing method thereof | |
| CN102468243B (en) | TFT (Thin Film Transistor) array substrate, manufacturing method and liquid crystal display device | |
| CN101013709A (en) | TFT array structure and manufacturing method thereof | |
| CN107871753A (en) | Array base palte and preparation method thereof | |
| CN103413834B (en) | A kind of thin-film transistor and preparation method thereof, array base palte and display unit | |
| US8093113B2 (en) | Array substrate for LCD and method of fabrication thereof | |
| CN105552028A (en) | Array substrate, fabrication method thereof, display panel and display device | |
| US10361261B2 (en) | Manufacturing method of TFT substrate, TFT substrate, and OLED display panel | |
| CN103915451A (en) | Array substrate, manufacturing method thereof and display device | |
| CN108538725B (en) | Thin film transistor and method of manufacturing the same | |
| CN104576526A (en) | Array substrate and preparation method thereof as well as display device | |
| CN100454559C (en) | TFT matrix structure and making method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20141208 Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20141208 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100176 DAXING, BEIJING TO: 100015 CHAOYANG, BEIJING |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20141208 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE Technology Group Co., Ltd. Patentee after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Address before: 100176 Beijing economic and Technological Development Zone, West Central Road, No. 8 Patentee before: Beijing BOE Photoelectricity Science & Technology Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201202 Address after: 215200 No. 1700, Wujiang economic and Technological Development Zone, Suzhou, Jiangsu, Zhongshan North Road Patentee after: Gaochuang (Suzhou) Electronics Co.,Ltd. Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd. Address before: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee before: BOE TECHNOLOGY GROUP Co.,Ltd. Patentee before: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |