CN107871753A - Array base palte and preparation method thereof - Google Patents
Array base palte and preparation method thereof Download PDFInfo
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- CN107871753A CN107871753A CN201711091327.4A CN201711091327A CN107871753A CN 107871753 A CN107871753 A CN 107871753A CN 201711091327 A CN201711091327 A CN 201711091327A CN 107871753 A CN107871753 A CN 107871753A
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- array base
- base palte
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- 238000002360 preparation method Methods 0.000 title claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 40
- 238000002834 transmittance Methods 0.000 claims abstract description 27
- 239000012212 insulator Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000003384 imaging method Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 30
- 238000002161 passivation Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 239000002238 carbon nanotube film Substances 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 229910021389 graphene Inorganic materials 0.000 claims description 3
- 238000009738 saturating Methods 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000002955 isolation Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 20
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 18
- 239000010409 thin film Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 15
- 239000010949 copper Substances 0.000 description 13
- 239000011787 zinc oxide Substances 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000010276 construction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910004205 SiNX Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 239000002253 acid Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005334 plasma enhanced chemical vapour deposition Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of preparation method of array base palte, including：The first metal layer is formed in substrate surface；In the first metal layer gate insulator, active layer, intermediate layer, second metal layer and photoresist layer, gate insulator isolation the first metal layer and active layer are sequentially depositing away from substrate side；Using intermediate tone mask plate exposure imaging, intermediate tone mask plate includes the first transmittance section and the second transmittance section, and corresponding first transmittance section of photoresist layer forms the first photoresistance area, and corresponding second transmittance section of photoresist layer forms the second photoresistance area；At the first photoresistance area, removing photoresistance layer, second metal layer and intermediate layer are gone to, makes active layer exposed, to form raceway groove and source electrode and drain electrode；At the second photoresistance area, removing photoresistance layer, second metal layer are gone, makes intermediate layer exposed, forms pixel electrode.The present invention also disclosed a kind of array base palte.The preparation cost of product is reduced, shortens the production cycle.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of array base palte and preparation method thereof.
Background technology
With social progress and the lifting of people's demand, display also develops towards large scale, high-resolution direction, adopted
The resolution ratio and size of display can be improved with the thin-film transistor array base-plate of high selvage guide line.But lead material using height
The problem of metallic atom diffusion is often run into when (such as copper) is connected up, causes device performance degradation.Therefore, in metal line
Insertion intermediate layer is usually required between layer and active layer to solve the high adhesive force and diffusion problem for leading wiring layer.
In the prior art, the preparation section in intermediate layer is complicated, have intermediate layer array base palte formed thin film transistor (TFT) with
The process of pixel electrode needs to undergo multiple mask and patterning processes, causes the preparation cost of product high, production cycle length.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and preparation method thereof, to solve prior art
The preparation process of middle array base palte needs to undergo multiple mask and patterning processes, causes the preparation cost of product high, the production cycle
The problem of long.
In order to solve the above technical problems, the present invention provides a kind of preparation method of array base palte, including：
The first metal layer is formed in substrate surface；
In the first metal layer gate insulator, active layer, intermediate layer, second are sequentially depositing away from the substrate side
Metal level and photoresist layer, the gate insulator isolate the first metal layer and the active layer；
Using intermediate tone mask plate exposure imaging, the intermediate tone mask plate includes the first transmittance section and the second transmittance section,
The photoresist layer corresponds to first transmittance section and forms the first photoresistance area, and the photoresist layer correspond to the second transmittance section formation the
Two photoresistance areas；
At the first photoresistance area, the photoresist layer, the second metal layer and the intermediate layer are removed, makes described to have
Active layer is exposed, to form raceway groove and source electrode and drain electrode；
At the second photoresistance area, the photoresist layer, the second metal layer are removed, makes the intermediate layer exposed, shape
Pixel electrode.
In a kind of embodiment, the intermediate tone mask plate also includes non-transparent portion, and the photoresist layer corresponds to described non-
Light portion forms the 3rd photoresistance area, and the first photoresistance area is between two the 3rd photoresistance areas, the system of the array base palte
Preparation Method also includes the photoresist layer for removing the 3rd photoresistance area, exposes the source electrode and the drain electrode.
In a kind of embodiment, after the substrate surface forms the first metal layer, on the first metal layer
Before depositing the gate insulator, the preparation method of the array base palte also includes patterning the first metal layer formation grid
Pole and the first capacitor plate, first capacitor plate correspond to the 3rd photoresistance area.
In a kind of embodiment of array base palte, the photoresist layer also includes the 4th photoresistance area, is exposed using intermediate tone mask plate
While photodevelopment, the preparation method of the array base palte also includes the photoresist layer for exposing the 4th photoresistance area, and carves
The second metal layer, the intermediate layer and the active layer in the corresponding 4th photoresistance area of erosion, pattern second gold medal
Belong to layer, the intermediate layer and the active layer and form source-drain electrode and the second capacitor plate.
In a kind of embodiment, after removing all photoresist layers, the preparation method of the array base palte also includes deposition passivation
Layer protects the array base palte.
In a kind of embodiment, after depositing the passivation layer, the preparation method of the array base palte is also included described in etching
The passivation layer of pixel electrode surface, exposes the pixel electrode.
In a kind of embodiment, first transmittance section is different with the transmitance of second transmittance section, is correspondingly formed
The first photoresistance area is different from the thickness of the photoresist layer in the second photoresistance area.
In a kind of embodiment, the intermediate layer is transparent conductive metal oxide, graphene or carbon nano-tube film.
In a kind of embodiment, the intermediate layer etches by magnetically controlled sputter method film forming, and by wet processing；Or institute
State intermediate layer to prepare by solwution method, and etched by dry process.
The present invention also provides a kind of array base palte, including grid, gate insulator, active layer, intermediate layer, source electrode and leakage
Pole, the grid, the gate insulator and the active layer are cascading, and the gate insulator completely cuts off the grid
With the active layer, the source electrode and the drain electrode are wrapped positioned at the active layer away from the side of the grid, the intermediate layer
The Part I and Part II mutually completely cut off is included, the Part I is described between the source electrode and the active layer
Between the drain electrode and the active layer, the intermediate layer is used to obstruct the source electrode or described drained to institute Part II
Active layer diffusing metal atoms are stated, and the Part I or the Part II are used as pixel electrode.
Beneficial effects of the present invention are as follows：Using intermediate tone mask plate exposure imaging, the first transmittance section of development formed the
Second metal layer corresponding to the removal of one photoresistance area and intermediate layer, reservation active layer form raceway groove, so as to form thin film transistor (TFT), show
Expose transparent intermediate layer after second metal layer corresponding to the second photoresistance area removal that the transmittance section of shadow second is formed, and with intermediate layer
As pixel electrode, i.e., thin film transistor (TFT) and pixel electrode are formed by a mask process, simplify the preparation of array base palte
Process, the preparation cost of product is reduced, shortens the production cycle.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other obvious modes of texturing are obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the preparation method of array base palte provided in an embodiment of the present invention.
Fig. 2 is the step S101 of the preparation method of array base palte provided in an embodiment of the present invention schematic diagram.
Fig. 3 is the step S102 of the preparation method of array base palte provided in an embodiment of the present invention schematic diagram.
Fig. 4 is the step S103 of the preparation method of array base palte provided in an embodiment of the present invention schematic diagram.
Fig. 5 and Fig. 6 is the step S104 of the preparation method for the array base palte that inventive embodiments provide schematic diagram.
Fig. 7 and Fig. 8 is the step S105 of the preparation method for the array base palte that inventive embodiments provide schematic diagram.
Fig. 9 is the step S106 of the preparation method for the array base palte that inventive embodiments provide schematic diagram.
Figure 10 is the structural representation for the array base palte that inventive embodiments provide.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The preparation method of array base palte provided in an embodiment of the present invention is used to prepare array base palte, specifically, array base palte
Including elements such as thin film transistor (TFT) (Thin-film transistor, TFT), pixel electrode, data wire, scan lines, wherein, sweep
The grid that line is electrically connected to thin film transistor (TFT) is retouched, data wire and pixel electrode are respectively electrically connected to source electrode or the leakage of thin film transistor (TFT)
One of pole, scan line provide connection or off-state of the scanning signal control source electrode with drain electrode, when source electrode connects with drain electrode, number
The voltage swing of data-signal control pixel electrode is transmitted so as to controlling the content of liquid crystal display panel display image according to line.
Referring to Fig. 1, the step of preparation method of array base palte 10 provided in an embodiment of the present invention, is as follows：
S101, the surface of substrate 10 formed the first metal layer 20.
Referring to Fig. 2, in the present embodiment, substrate 10 is glass substrate 10 or other transparent non-conductive substrates 10, substrate
The 10 main supporting body as array base palte 10, each film layer and structure of array base palte 10 may be contained within substrate 10.
In a kind of embodiment, the first metal layer 20 can be the metal materials such as Cu, Mo, Ti, Al, Cr, Ag, Au, or aoxidize
Indium tin (ITO), indium zinc oxide (IZO), the zinc oxide (AZO) of aluminium doping, indium gallium zinc oxide (IGZO), zinc-tin oxide (ZTO)
Deng the laminated construction of one or more multi-element metal oxide conductive materials in multi-element metal oxide conductive material, and
The thickness of one metal level 20 can be 500A~20000A.
In the present embodiment, after forming the first metal layer 20 on the surface of substrate 10, patterned first metal layer 20 forms grid
22 and first pole plate 24, corresponding the 3rd photoresistance area 76 being subsequently formed of the first pole plate 24.Specifically, the pole plate 24 of grid 22 and first
Mutually isolation, grid 22, which is electrically connected on array base palte 10, is used to transmitting the scan line of scanning signal, the first pole plate 24 with it is follow-up
The second pole plate 66 that step is formed is relative to form electric capacity.
In the present embodiment, the first metal layer 20 can by physical vapour deposition (PVD) (Physical Vapor Deposition,
PVD) method film forming is on substrate 10, and shaping can be performed etching by wet processing to form the pole plate of grid 22 and first
24.In a kind of embodiment, the material of the first metal layer 20 is Cu, thickness 300nm, by magnetically controlled sputter method film forming, by wet
Method etching (copper acid) mode is realized graphically.
The preparation method of the first metal layer 20 is simply easily realized, standard is done to be subsequently formed thin film transistor (TFT) and pixel electrode 52
It is standby.
S102, in the first metal layer 20 it is sequentially depositing gate insulator 30, active layer 40, intermediate layer away from the side of substrate 10
50th, second metal layer 60 and photoresist layer 70, gate insulator 30 isolate the first metal layer 20 and active layer 40.
Incorporated by reference to Fig. 3, in the present embodiment, gate insulator 30 covers the surface of the first metal layer 20, not only by the first gold medal
Category layer 20 is isolated with active layer 40 to insulate, also that the grid 22 in the first metal layer 20 and the first pole plate 24 is mutually isolated with exhausted
Edge.Specifically, gate insulator 30 can be SiOx、SiNx、HfO2、Al2O3Deng the one or more insulation in insulating dielectric materials
The laminated construction of dielectric material, the thickness of gate insulator 30 can be 100A~10000A, and can pass through chemical vapor deposition
(Chemical Vapor Deposition, CVD) method film forming.In a kind of embodiment, gate insulator 30 is SiNxWith
SiOxLaminated construction, SiNxThickness be 100nm, SiOxThickness be 300nm, and by by plasma enhanced chemical
Vapour deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD) method film forming.
In the present embodiment, active layer 40 is oxide semiconductor, specifically, active layer 40 can be indium gallium zinc oxide
(IGZO), the zinc oxide (AZO) of aluminium doping, indium zinc oxide (IZO), indium gallium zinc oxide (IGTO), zinc-tin oxide (ZTO) etc. are saturating
Bright oxide semiconductor material.The thickness of active layer 40 can be 300A~1000A.In a kind of embodiment, layer material of having chance with is
IGZO, thickness 50nm, etched by magnetically controlled sputter method film forming, and by wet processing.
In the present embodiment, intermediate layer 50 can be tin indium oxide (ITO), indium zinc oxide (IZO), the zinc oxide of aluminium doping
(AZO), the transparent conductive metal oxide material such as indium gallium zinc oxide (IGZO), or graphene, carbon nano-tube film etc. are transparent
Conductive material.The material transparent of intermediate layer 50 is conductive, and is needed between the material of active layer 40 and the material of second metal layer 60 with one
Etching ratio is determined, to be used as the function of pixel electrode 52.In a kind of embodiment, intermediate layer 50 is IZO, thickness 30nm, by magnetic
Sputtering method film forming is controlled, is etched by wet processing.
In the present embodiment, second metal layer 60 can be the metal materials such as Cu, Mo, Ti, Al, Cr, Ag, Au, or tin indium oxide
(ITO), indium zinc oxide (IZO), the zinc oxide (AZO) of aluminium doping, indium gallium zinc oxide (IGZO), zinc-tin oxide (ZTO) etc. are more
The laminated construction of one or more multi-element metal oxide conductive materials in first metal conductive oxide material, and the second gold medal
The thickness for belonging to layer 60 can be 500A~20000A.In a kind of embodiment, the material of second metal layer 60 is Cu, thickness 300nm,
By magnetically controlled sputter method film forming, pass through wet processing (copper acid) etching.
In the present embodiment, photoresist layer 70 is photoresist, and photoresist layer 70 shows in the exposure subsequently through intermediate tone mask plate 80
The different photoresistance area of thickness is formed during shadow, so as to form corresponding structure.
S103, use the exposure imaging of intermediate tone mask plate 80.
Incorporated by reference to Fig. 4, in the present embodiment, intermediate tone mask plate 80 includes the first transmittance section 82 and the second transmittance section 84, light
Corresponding first transmittance section 82 of resistance layer 70 forms the first photoresistance area 72, and corresponding second transmittance section 84 of photoresist layer 70 forms the second photoresistance area
74.Specifically, the first transmittance section 82 is different with the transmitance of the second transmittance section 84, the first photoresistance area 72 and second being correspondingly formed
The thickness of the photoresist layer 70 in photoresistance area 74 is different.Photoresist layer 70 is patterned for subsequent etch pair by intermediate tone mask plate 80
Answer device architecture corresponding to film layer (one or more in second metal layer 60, the intermediate layer 50, active layer 40) formation in region.
In a kind of embodiment, the transmitance of the first transmittance section 82 is more than the transmitance of the second transmittance section 84, the first light being correspondingly formed
The thickness for hindering area 72 is less than the thickness in the second photoresistance area 74.In the present embodiment, the first photoresistance area 72, which is subsequently correspondingly formed, unidirectionally to be connected
Source electrode 64 and the raceway groove of drain electrode 62 are connect, the second photoresistance area 74 is subsequently correspondingly formed pixel electrode 52.Utilize intermediate tone mask plate 80
Exposure imaging, the first photoresistance area 72 that the first transmittance section 82 of development is formed remove corresponding to second metal layer 60 and intermediate layer 50,
Retain active layer 40 and form raceway groove, so as to form thin film transistor (TFT), the second photoresistance area 74 that the second transmittance section 84 of development is formed is gone
Except exposing transparent intermediate layer 50 after corresponding second metal layer 60, and using intermediate layer 50 as pixel electrode 52, i.e., by one
Secondary mask process forms thin film transistor (TFT) and pixel electrode 52, simplifies the preparation process of array base palte 10, reduces product
Cost is prepared, shortens the production cycle.
In the present embodiment, intermediate tone mask plate 80 also includes non-transparent portion 86, and the corresponding non-transparent portion 86 of photoresist layer 70 is formed
3rd photoresistance area 76, the first photoresistance area 72 is between two the 3rd photoresistance areas 76.Specifically, non-transparent portion 86 covers for halftoning
80 lighttight part of diaphragm plate, the light for exposure can not pass through alternatively non-transparent district, and the 3rd photoresistance area 76 keeps photoresist layer 70 to apply
The thickness of thickness when covering, i.e. the 3rd photoresistance area 76 is maximum.In a kind of embodiment, the quantity in the 3rd photoresistance area 76 is three,
Wherein, between two the 3rd photoresistance areas 76, two the 3rd photoresistance areas 76 are used to subsequently be correspondingly formed in the first photoresistance area 72
Source electrode 64 and drain electrode 62, the first photoresistance area 72 is used to subsequently be correspondingly formed raceway groove, so as to form thin film transistor (TFT)；Another the 3rd
The position of corresponding first pole plate 24 in photoresistance area 76, for being subsequently formed electric capacity.It is non-using the exposure imaging of intermediate tone mask plate 80
Light portion 86 is correspondingly formed source electrode 64, drain electrode 62 and electric capacity, so as to form array base palte 10, i.e., is formed by a mask process thin
Film transistor and pixel electrode 52, simplify the preparation process of array base palte 10, reduce the preparation cost of product, shorten life
Produce the cycle.
In the present embodiment, photoresist layer 70 also includes the 4th photoresistance area 710, uses the same of the exposure imaging of intermediate tone mask plate 80
When, the photoresist layer 70 in the 4th photoresistance area 710 of exposure.Specifically, intermediate tone mask plate 80 does not cover the 4th photoresistance area 710, in profit
While the first photoresistance area 72 and the second photoresistance area 74 being exposed with intermediate tone mask plate 80, the photoresistance of exposure light direct irradiation the 4th
The photoresist layer 70 in area 710, by 70 whole exposure imagings of photoresist layer in the 4th photoresistance area 710, expose the second of the 4th photoresistance area 710
Metal level 60.Follow-up second metal layer 60, intermediate layer 50 and the active layer 40 for removing corresponding 4th photoresistance area 710 is to realize film layer
Patterning.
Developed using intermediate tone mask plate 80 by single exposure and form the first photoresistance area 72, the second photoresistance area simultaneously
74th, the 3rd photoresistance area 76, the 4th photoresistance area 710, for being subsequently correspondingly formed the devices such as thin film transistor (TFT), pixel electrode 52 and electric capacity
Part structure, the preparation process of array base palte 10 is simplified, reduce the preparation cost of product, shorten the production cycle.
S104, at the first photoresistance area 72, go to removing photoresistance layer 70, second metal layer 60 and intermediate layer 50, make active layer 40
It is exposed, to form raceway groove and source electrode 64 and drain electrode 62.
Incorporated by reference to Fig. 5, in the present embodiment, formed before raceway groove, also to etch the second metal for removing the 4th photoresistance area 710
Layer 60, intermediate layer 50 and active layer 40.In a kind of embodiment, the material of second metal layer 60 is Cu, thickness 300nm, by magnetic
Control sputtering method film forming, by wet processing (copper acid) etching, intermediate layer 50 is IZO, thickness 30nm, by magnetically controlled sputter method into
Film, etched by wet processing, layer material of having chance with is IGZO, thickness 50nm, by magnetically controlled sputter method film forming, passes through wet method work
Skill etches.Specifically, the 4th photoresistance area 710 is used to carry out film pattern, to realize the global pattern of array base palte 10.
Incorporated by reference to Fig. 6, in the present embodiment, first using O2Plasma etching is ashed photoresist layer 70, so as to remove first
The photoresist layer 70 in photoresistance area 72, exposes second metal layer 60, then etches the second metal layer 60 for removing corresponding first photoresistance area 72
With intermediate layer 50, retain active layer 40 and form raceway groove.In a kind of embodiment, the material of second metal layer 60 is Cu, and thickness is
300nm, by magnetically controlled sputter method film forming, by wet processing (copper acid) etching, intermediate layer 50 is IZO, thickness 30nm, by magnetic control
Sputtering method film forming, is etched by wet processing.
S105, at the second photoresistance area 74, go removing photoresistance layer 70, second metal layer 60, make intermediate layer 50 exposed, formed picture
Plain electrode 52.
Incorporated by reference to Fig. 7, in the present embodiment, first using O2Plasma etching is ashed photoresist layer 70, so as to remove second
The photoresist layer 70 in photoresistance area 74, exposes second metal layer 60, then etches the second metal layer 60 for removing corresponding second photoresistance area 74,
Retain intermediate layer 50 and form pixel electrode 52.In a kind of embodiment, the material of second metal layer 60 is Cu, thickness 300nm, by
Magnetically controlled sputter method film forming, pass through wet processing (copper acid) etching.
Incorporated by reference to Fig. 8, in the present embodiment, after forming the pixel electrode 52, the photoresistance in the 3rd photoresistance area 76 is also removed
Layer 70, exposes second metal layer 60.Specifically, the second metal corresponding to two the 3rd photoresistance areas 76 of the both sides of the first photoresistance area 72
Layer 60 forms source electrode 64 and drain electrode 62 respectively, and source electrode 64 and drain electrode 62 pass through the unilaterally connected of active layer 40.In a kind of embodiment,
Source electrode 64 is contacted and electrically connected with the intermediate layer 50 of formation pixel electrode 52, and drain electrode 62 electrically connects with data wire, so as to work as source electrode
64 with drain electrode 62 conducting when data wire transmission data-signal control pixel voltage voltage change, so as to control display device to show
The content of diagram picture.Second metal layer 60 corresponding to 3rd photoresistance area 76 forms the second pole plate 66, the second pole plate 66 and the first pole
Plate 24 is correspondingly formed electric capacity, and electric capacity plays a part of discharge and recharge so as to be influenceed on pixel electrode 52.
S106, deposit passivation layer 90 protect array base palte 10, the passivation layer 90 on etching pixel electrode 52 surface, expose pixel
Electrode 52.
Incorporated by reference to Fig. 9, passivation layer 90 is used for protection device, and in the present embodiment, passivation layer 90 can be SiOx、SiNx、HfO2、
Al2O3Deng the laminated construction of one or more insulating materials in insulating materials, the thickness of passivation layer 90 can be 1000A~10000A,
And CVD method film forming can be passed through.In a kind of embodiment, gate insulator 30 is SiOxAnd SiNxLaminated construction, SiOxThickness
For 300nm, SiNxThickness be 100nm, gate insulator 30 is performed etching by PECVD method film forming by dry process.
In the present embodiment, the process that Etch Passivation 90 exposes pixel electrode 52 experienced a masking process, be formed thin
Film transistor and pixel electrode 52 experienced a mask process, therefore at least only be needed twice in the preparation process of array base palte 10
Mask process is that thin film transistor (TFT) and all patterning process in the region of pixel electrode 52 can be achieved, and simplifies array base palte 10
Preparation process, the preparation cost of product is reduced, shortens the production cycle.
Referring to Fig. 10, the embodiment of the present invention also provides a kind of array base palte 100, array base palte 100 is implemented by the present invention
It is prepared by the preparation method for the array base palte 100 that example provides.Array base palte 100 includes grid 22, gate insulator 30, active layer
40th, intermediate layer 50, source electrode 62 and drain electrode 64, grid 22, gate insulator 30 and active layer 40 are cascading, gate insulator
Layer 30 completely cuts off grid 22 and active layer 40, and source electrode 62 and drain electrode 64 deviate from the side of grid 22, intermediate layer 50 positioned at active layer 40
Including the Part I 502 and Part II 504 mutually completely cut off, specifically, intermediate layer 50 is conductive material, and Part I
502 with Part II 504 by with along be vapor-deposited after formed.Part I 502 between source electrode 62 and active layer 40,
For Part II 504 between drain electrode 64 and active layer 40, intermediate layer 50 is used to obstruct source electrode 62 or drain electrode 64 to active layer 40
Diffusing metal atoms, and Part I 502 or Part II 504 are used as pixel electrode.Specifically, Part I 502 and
Two parts 504 are that intermediate layer 50 is formed after overetch, and Part I 502 is mutually not turned on Part II 504.One kind is implemented
In mode, Part II 504 is used as pixel electrode, and drain electrode 64 is electrically connected to active layer 40 by Part II 504, and source electrode 62 is logical
Cross Part I 502 and be electrically connected to active layer 40, when grid 22 turns on, source electrode 62 passes through the one-way conduction of active layer 40 to drain electrode
64, i.e. drive signal is transferred to drain electrode 64 from source electrode 62, and then pixel electrode (Part II 504) is charged.Other embodiment party
In formula, Part I 502 can also be used as pixel electrode.Intermediate layer 50 blocks the high source electrode 62 for leading material or drain electrode 64 to having
The diffusing metal atoms of active layer 40, device performance degradation is avoided, improve the service life of array base palte 100, meanwhile, Part I
502 or Part II 504 be also used as pixel electrode, simple in construction, not increasing the manufacturing process of array base palte 100 reduces product
Preparation cost, shorten the production cycle.
The above disclosed power for being only several preferred embodiments of the present invention, the present invention can not being limited with this certainly
Sharp scope, one of ordinary skill in the art will appreciate that realizing all or part of flow of above-described embodiment, and weighed according to the present invention
Profit requires made equivalent variations, still falls within and invents covered scope.
Claims (10)
- A kind of 1. preparation method of array base palte, it is characterised in that including：The first metal layer is formed in substrate surface；In the first metal layer gate insulator, active layer, intermediate layer, the second metal are sequentially depositing away from the substrate side Layer and photoresist layer, the gate insulator isolate the first metal layer and the active layer；Using intermediate tone mask plate exposure imaging, the intermediate tone mask plate includes the first transmittance section and the second transmittance section, described Photoresist layer corresponds to first transmittance section and forms the first photoresistance area, and the photoresist layer corresponds to second transmittance section and forms the second light Hinder area；At the first photoresistance area, the photoresist layer, the second metal layer and the intermediate layer are removed, makes the active layer It is exposed, to form raceway groove and source electrode and drain electrode；At the second photoresistance area, the photoresist layer, the second metal layer are removed, makes the intermediate layer exposed, forms picture Plain electrode.
- 2. the preparation method of array base palte according to claim 1, it is characterised in that the intermediate tone mask plate also includes Non-transparent portion, the photoresist layer correspond to the non-transparent portion and form the 3rd photoresistance area, and the first photoresistance area is positioned at described in two Between 3rd photoresistance area, the preparation method of the array base palte also includes the photoresist layer for removing the 3rd photoresistance area, dew Go out the source electrode and the drain electrode.
- 3. the preparation method of array base palte according to claim 2, it is characterised in that formed in the substrate surface described After the first metal layer, before the gate insulator is deposited on the first metal layer, the preparation method of the array base palte Also include the patterning the first metal layer formation grid and the first capacitor plate, first capacitor plate correspond to the described 3rd Photoresistance area.
- 4. the preparation method of array base palte according to claim 3, it is characterised in that the photoresist layer also includes the 4th light Area is hindered, while using intermediate tone mask plate exposure imaging, the preparation method of the array base palte also includes exposure the described 4th The photoresist layer in photoresistance area, and etch the second metal layer in the corresponding 4th photoresistance area, the intermediate layer and described Active layer.
- 5. the preparation method of array base palte according to claim 4, it is characterised in that form second capacitor plate Afterwards, the preparation method of the array base palte also includes the deposit passivation layer protection array base palte.
- 6. the preparation method of array base palte according to claim 5, it is characterised in that described after depositing the passivation layer The preparation method of array base palte also includes the passivation layer for etching the pixel electrode surface, exposes the pixel electrode.
- 7. the preparation method of the array base palte according to claim 1 to 6 any one, it is characterised in that described first is saturating Light portion is different with the transmitance of second transmittance section, the light in the first photoresistance area being correspondingly formed and the second photoresistance area The thickness of resistance layer is different.
- 8. the preparation method of the array base palte according to claim 1 to 6 any one, it is characterised in that the intermediate layer For transparent conductive metal oxide, graphene or carbon nano-tube film.
- 9. the preparation method of array base palte according to claim 8, it is characterised in that the intermediate layer passes through magnetron sputtering Method film forming, and etched by wet processing；OrThe intermediate layer is prepared by solwution method, and is etched by dry process.
- A kind of 10. array base palte, it is characterised in that including grid, gate insulator, active layer, intermediate layer, source electrode and drain electrode, The grid, the gate insulator and the active layer are cascading, the gate insulator completely cut off the grid with The active layer, the source electrode and the drain electrode deviate from the side of the grid positioned at the active layer, and the intermediate layer includes The Part I and Part II mutually completely cut off, the Part I is between the source electrode and the active layer, and described Between the drain electrode and the active layer, the intermediate layer is used to obstruct the source electrode or described drained to described for two parts Active layer diffusing metal atoms, and the Part I or the Part II are used as pixel electrode.
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| CN109037301A (en) * | 2018-09-07 | 2018-12-18 | 京东方科技集团股份有限公司 | Array substrate and production method, display device |
| CN110554004A (en) * | 2018-06-04 | 2019-12-10 | 考姆爱斯株式会社 | device and method for monitoring whether protective film for semiconductor substrate is peeled off or not |
| CN112951853A (en) * | 2021-04-14 | 2021-06-11 | 昆山龙腾光电股份有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN113644030A (en) * | 2021-07-30 | 2021-11-12 | 合肥维信诺科技有限公司 | Functional module and preparation method thereof |
| CN113690180A (en) * | 2021-08-13 | 2021-11-23 | 昆山龙腾光电股份有限公司 | Array substrate and manufacturing method |
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| CN115360142A (en) * | 2022-10-19 | 2022-11-18 | 广州华星光电半导体显示技术有限公司 | Preparation method of array substrate and array substrate |
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| CN110554004A (en) * | 2018-06-04 | 2019-12-10 | 考姆爱斯株式会社 | device and method for monitoring whether protective film for semiconductor substrate is peeled off or not |
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| CN113690180B (en) * | 2021-08-13 | 2024-03-12 | 昆山龙腾光电股份有限公司 | Array substrate and manufacturing method |
| CN114038737A (en) * | 2021-08-17 | 2022-02-11 | 重庆康佳光电技术研究院有限公司 | Mask, light-emitting device and manufacturing method thereof |
| CN114038737B (en) * | 2021-08-17 | 2022-08-26 | 重庆康佳光电技术研究院有限公司 | Mask plate using method, light-emitting device and manufacturing method thereof |
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| CN115360142A (en) * | 2022-10-19 | 2022-11-18 | 广州华星光电半导体显示技术有限公司 | Preparation method of array substrate and array substrate |
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