CN100462825C - Array base board structure of thin film transistor liquid crystal display and its producing method - Google Patents

Array base board structure of thin film transistor liquid crystal display and its producing method Download PDF

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CN100462825C
CN100462825C CN 200510132423 CN200510132423A CN100462825C CN 100462825 C CN100462825 C CN 100462825C CN 200510132423 CN200510132423 CN 200510132423 CN 200510132423 A CN200510132423 A CN 200510132423A CN 100462825 C CN100462825 C CN 100462825C
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thin film
film transistor
mask
photoresist
layer
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CN1987622A (en
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龙春平
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北京京东方光电科技有限公司;京东方科技集团股份有限公司
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Abstract

本发明公开一种薄膜晶体管液晶显示器的阵列基板结构及其制造方法。 The present invention discloses a thin film transistor liquid crystal display and a manufacturing method of an array substrate structure. 本发明公开的薄膜晶体管液晶显示器的阵列基板结构通过增大透明像素电极与薄膜晶体管的漏电极的接触面积,来形成良好的电连接。 A thin film transistor array substrate of a liquid crystal display of the present invention is disclosed by increasing the drain electrode and the transparent pixel electrode of the thin film transistor of the contact area, to form a good electrical connection. 本发明公开的薄膜晶体管液晶显示器的阵列基板的制造方法包含三次掩膜版光刻工艺步骤:首先,使用第一个普通掩膜版进行第一层金属薄膜的图案定义,形成栅极扫描线和栅电极;然后,使用第二个掩膜版,即灰色调半透明掩膜版进行第二层金属薄膜和有源层的图案定义,形成数据扫描线、硅岛、源漏电极和薄膜晶体管的沟道;最后,使用第三个普通掩膜版进行第二层绝缘薄膜,即钝化膜的图案定义,再利用离地剥离工艺形成透明导电薄膜的图案,即透明像素电极。 The method of manufacturing an array substrate of the present invention disclosed a thin film transistor liquid crystal display comprising a mask lithography process three steps: First, using a common first mask defining a first patterned metal thin film layer, and forming a gate scan line a gate electrode; then, using a second mask, i.e., a gray-tone mask for the second layer semi-transparent metal thin film and the active layer pattern definition, data line is formed, a silicon island, source and drain electrodes of the thin film transistor channel; Finally, using a third mask ordinary second insulating film, i.e., the pattern defined in the passivation film, and then forming a transparent conductive thin film pattern, i.e. the use of the transparent pixel electrode peeling-off process. 本方法减少掩膜版的数目和光刻工艺次数,简化了薄膜晶体管液晶显示器的阵列基板制造工艺。 This method reduces the number of mask lithography and the number of processes, simplifying the manufacturing process of a thin film transistor array substrate of a liquid crystal display.

Description

一种薄膜晶体管液晶显示器的阵列基板结构及其制造方法 Array substrate and a manufacturing method of a thin film transistor liquid crystal display

技术领域 FIELD

本发明涉及一种薄膜晶体管液晶显示器(TFT-LCD)的阵列基板结构及其制造方法。 The present invention relates to a thin film transistor liquid crystal display (TFT-LCD) and a manufacturing method of an array substrate structure.

背景技术 Background technique

液晶显示技术发展得非常快,由于其重量轻,液晶显示器件被广泛应用于便携式电子设备。 LCD technology is developing very fast, due to its light weight, the liquid crystal display devices are widely used in portable electronic devices. 随着应用领域的扩张,需要在制造技术方面降低成本和提高生产率。 With the expansion of application fields, the need to reduce costs and improve productivity in manufacturing technology. 一个液晶显示器件的制作是通过一组薄膜的沉积和光刻工艺形成图案来完成的。 A liquid crystal display device is produced to complete the deposition and patterned by a photolithography process of a group of film. 光刻用的掩膜版数目是衡量制造液晶显示器件工艺繁简程度。 Lithography mask number is a measure of the degree of manufacturing a liquid crystal display device engineering procedures. 一次光刻工艺使用一个掩膜版。 A photolithography process using a mask. 许多研究者已经研究了减少掩膜版数目的可能方法,因为减少一个掩膜版意味着制造成本的降低。 Many researchers have studied the possible ways to reduce the number of mask, a mask because of reduced reduce manufacturing costs mean.

通常一个液晶显示器件由彩膜基板、阵列基板和夹于二者之间的液晶组成。 A liquid crystal display device is typically a color filter substrate, an array substrate and a liquid crystal composition sandwiched therebetween. 其阵列基板的结构如图la和图lb所示。 Structure shown in Figure la and lb which the array substrate shown in FIG. 阵列基板包括一组栅极扫描线1、 栅电极2, 一组数据扫描线5、源电极6、漏电极7,薄膜晶体管开关器件以及透明像素电极10。 The array substrate includes a group of gate lines 1, the gate electrode 2, a set of data lines 5, the source electrode 6, drain electrode 7, the thin film transistor switching device 10 and the transparent pixel electrode. 栅极扫描线1相互平行与数据扫描线5交叉形成矩阵结构。 1 gate lines parallel to one another and intersect data lines 5 form a matrix structure. 在栅极扫描线1与数据扫描线5交叉的位置形成一个薄膜晶体管开关器件。 1 is formed in a thin film transistor switching device 5 and the gate scanning lines intersecting the data line location. 它包含一个从栅极扫描线1引出的栅电极2, —个从数据扫描线5引出的源电极6,和一个与源电极处于相对位置的漏电极7。 It includes a gate electrode drawn from the gate scanning line 12, - a source electrode drawn from the data lines 56, and the drain electrode 7 is in a position opposite to the source electrode. 漏电极7是薄膜晶体管开关器件的输出端。 The drain electrode 7 is an output terminal of the thin film transistor switching device. 一个透明像素电极10通过钝化层8上的过孔与漏电极7 形成电接触。 A transparent pixel electrode 7 electrode 10 makes electrical contact with the drain through the through hole 8 on the passivation layer. 栅极扫描线l的一部分,即与透明像素电极10重叠的凸起部分和透明像素电极10 —起形成存储电容。 L part of the gate scan lines, i.e. the transparent pixel electrode overlapping the convex portion 10 and the transparent pixel electrode 10 - together form a storage capacitor.

上述液晶显示器的阵列基板制造工艺流程如图2和图3所示。 The array substrate manufacturing process of the liquid crystal display shown in FIGS. 2 and 3. 五次掩膜 Five mask

技术依次通过如图2所示的五步工艺完成,使用了五块掩膜版。 Technology sequentially by five steps shown in Figure 2 is completed, using the five mask. 四次掩膜技 Four mask technology

术依次通过如图3所示的四步工艺完成,使用了四块掩膜版。 Four-step process by sequentially surgery is completed as shown in FIG. 3, using four mask. 每一步工艺基 Every step of the process base

本均由薄膜沉积、掩膜版曝光、刻蚀和光刻胶剥离四道工序组成。 Present by thin film deposition, mask exposure, etching and photoresist stripping composition of four processes.

图la和图lb所示的薄膜晶体管液晶显示器制造工艺过程如下所述。 FIGS. La and lb a thin film transistor liquid crystal display manufacturing process shown as follows. 通过栅极掩膜版在玻璃基板上面形成栅电极2及栅极扫描线1;在栅极金属上连续沉积栅极绝缘层4、有源层薄膜和欧姆接触层薄膜,通过半导体层掩膜版形成半导体层3;通过源漏电极掩膜版形成源电极6、漏电极7以及数据扫描线5;通过钝化层掩膜版形成钝化层薄膜的过孔;最后通过透明像素电极掩膜版形成透明-像素电极10。 Forming a gate electrode 2 and gate line above the glass substrate 1 through a gate mask; continuously depositing a gate metal on the gate insulating layer 4, an active layer and an ohmic contact layer thin film, the semiconductor mask layer forming a semiconductor layer 3; 6, drain electrode 7 and the data lines forming a source electrode 5 drain electrode through the source mask; through hole in the passivation layer is a thin film formed by a passivation layer mask; Finally, the transparent pixel electrode mask forming a transparent - the pixel electrode 10.

而四次掩膜技术是利用灰色调半透明掩膜版,把半导层和源漏电极的光刻工艺合并到同一次掩膜工艺当中。 The four gray-tone mask technique is to use a semi-transparent mask, the semiconductor layer and the source and drain electrodes incorporated into the same photolithographic process mask process them. 其方法是连续沉积栅极绝缘层4、有源层薄膜和欧姆接触层薄膜、以及用于形成源电极6和漏电极7的第二层金属薄 Which process is a continuous deposition of a gate insulating layer 4, an active layer and an ohmic contact layer thin film, and a second layer 6 is formed thin metal source electrode and the drain electrode 7

膜。 membrane. 首先利用灰色调半透明掩膜版的全透明区域形成薄膜晶体管器件的硅岛,然后利用灰色调半透明掩膜版的半透明区域和光刻胶的灰化工艺在薄膜晶体管硅岛上形成源电极6、漏电极7以及薄膜晶体管的沟道部分13。 Firstly, the fully transparent area of ​​the gray-tone mask translucent silicon islands formed thin film transistor device, and an ashing process using a gray-tone mask translucent translucent region and a photoresist is formed on the island silicon thin film transistor source electrode 6, drain electrode 7 and the channel portion of the thin film transistor 13. 改变掩膜版的设计和薄膜沉积工艺次序,也有其它的五次掩膜和四次掩膜工艺技术。 Change the mask design and process sequence film deposition, there are other five and four mask masking technology.

前述薄膜晶体管液晶显示器阵列基板的五次掩膜和四次掩膜工艺均存在光刻工艺复杂,使用掩膜版数量多的缺陷。 The five mask process and four mask thin film transistor array substrate of a liquid crystal display are present complex photolithography process, using the number of mask defects. 有些工艺在使用离地剥离工艺时, 使用的特殊剥离液不仅腐蚀光刻胶,还对其他材料进行腐蚀。 Some processes use upon peeling-off process, not only the special stripping solution used in etching resist, etching other materials also. 以上缺陷造成了制造中良品率低、成本高等弊端。 Defects caused by the above manufacturing yield is low, and high cost disadvantages.

发明内容 SUMMARY

为了克服现有技术的缺陷,本发明提供一种薄膜晶体管液晶显示器阵列基板结构,以及一种不同于先前的薄膜晶体管液晶显示器的阵列基板的制造方法。 In order to overcome the drawbacks of the prior art, the present invention provides a liquid crystal display thin film transistor array substrate, and a method for manufacturing an array substrate of a thin film transistor liquid crystal display previously is different. 本发明的第一个目的是提供一种薄膜晶体管液晶显示器阵列基板结构, A first object of the present invention is to provide a liquid crystal display thin film transistor array substrate structure,

使不同材料之间具有良好的接触,增加透明像素电极和漏电极的接触面积, 并降低生产中的不良率。 So between different materials having good contact, the contact area between the transparent pixel electrode and the drain electrode, and reduce the defect rate in the production. 本发明的第二个目的是提供一种采用灰色调半透明掩膜版和离地剥离工艺的薄膜晶体管液晶显示器阵列基板的制造方法,使用三次掩膜完成液晶显示器件的阵列基板制作。 A second object of the present invention is to provide a translucent gray-tone mask and a method of manufacturing a thin film transistor liquid crystal display array substrate using a peeling-off process, to complete the array substrate using three masks made of liquid crystal display device. 减少了掩膜版的数目,简化了制造工艺。 Reducing the number of mask, the manufacturing process is simplified. 本发明的第三个目的是优化离地剥离工艺,在形成钝化层图案时, 在光刻的曝光显影工艺中,使光刻胶的侧壁垂直,而在刻蚀工艺中,使钝化层侧壁内凹。 A third object of the present invention is to optimize the peeling-off process, when the passivation layer pattern is formed, exposure and development in the photolithography process, a resist vertical side wall, while the etch process, passivation recessed sidewall layer. 在进行离地剥离工艺时,利用这种侧壁结构,可使用普通剥离液,仅对光刻胶进行剥离,而不需腐蚀其它材料,提高了离地剥离工艺的效率和可靠性,降低了成本。 During peeling-off process, with this side wall structure, can be used ordinary stripping liquid, only the photoresist is stripped, other materials without etching, lifting-off process to improve the efficiency and reliability, reduced cost. 通过以下对本发明的描述以及具体实施例,还能了解到本发明的其它优点。 DETAILED the following description of embodiments of the present invention and, it can understand other advantages of the present invention.

为了实现上述目的,本发明提供一种薄膜晶体管阵列基板结构,包括: 玻璃基板,形成于玻璃基板上栅极扫描线、数据扫描线、薄膜晶体管和透明像素电极,所述透明像素电极和所述薄膜晶体管漏电极的电连接是通过透明像素电极覆盖到薄膜晶体管漏电极上表面,形成表面接触的结构实现的,所述薄膜晶体管包括栅电极,所述栅电极上依次形成有栅绝缘层、半导体层、 To achieve the above object, the present invention provides a thin film transistor array substrate, comprising: a glass substrate, a gate electrode formed on the glass substrate, the scanning lines, data lines, thin film transistors and transparent pixel electrodes, the transparent pixel electrode and said a drain electrode electrically connected to the thin film transistor is covered with the transparent pixel electrode to the drain electrode on the surface of the thin film transistor is formed, the contact surface of the thin film transistor includes a gate electrode implemented, the gate electrode are sequentially formed on the gate insulating layer, a semiconductor Floor,

源电极和漏电极、钝化层薄膜,其中,所述透明像素电极在钝化层薄膜的内凹侧壁处断开,像素电极与钝化层薄膜没有重叠的部分。 A source electrode and a drain electrode, a passivation film layer, wherein the transparent pixel electrode in the recessed sidewall passivation layer is turned off, the pixel electrode and the passivation layer does not overlap.

在制造薄膜晶体管阵列基板工艺中,对钝化层薄膜进行刻蚀时,实现内凹的侧壁形貌,因此在沉积透明像素电极时,就形成了透明像素电极在钝化层薄膜的内凹侧壁处断开的结构。 In the manufacturing process of the TFT array substrate, the passivation layer when the thin film is etched to achieve the morphology concave sidewall, so when depositing the transparent pixel electrode, a transparent pixel electrode formed in the passivation layer is concavely disconnection structure side walls.

为实现上述目的,本发明还提供一种薄膜晶体管阵列基板的制造方法, 包括下列步骤:首先,提供一个绝缘透明衬底;在绝缘村底上依次形成第一层金属薄膜和一层光刻胶;使用第一块掩膜版定义光刻胶的图案,并刻蚀形成第一层金属薄膜的图案,即栅电极和栅极扫描线;然后,在基板上沉积一层绝缘层、沉积至少一层半导体层和沉积一层金属薄膜;在金属薄膜上涂布一层光刻胶;使用第二块掩膜版,即灰色调半透明掩膜版,经过曝光显影和 To achieve the above object, the present invention also provides a method of manufacturing a thin film transistor array substrate, comprising the steps of: providing a transparent insulating substrate; forming a first metal thin film layer and a layer of photoresist on the insulating substrate village ; using a first photoresist mask defines a pattern, and etching to form a first metal thin film layer pattern, i.e., the gate electrode and gate scanning line; then, depositing an insulating layer on the substrate, depositing at least a depositing a layer of the semiconductor layer and a metal thin film; film coating on the metal layer of photoresist; block using a second mask, i.e., gray translucent mask, and after the exposure and development

刻蚀形成薄膜晶体管硅岛,利用光刻胶灰化工艺和刻蚀,形成源电极、漏电 Silicon island etching a thin film transistor, an ashing process using a photoresist and etching, a source electrode, a drain

极和薄膜晶体管开关器件的沟道;最后,在基板上沉积一层钝化层薄膜;用第三块掩膜版通过曝光显影形成光刻胶图案,在光刻时,使曝光显影后剩余光刻胶侧壁形成垂直的形貌,去除未被光刻胶覆盖的钝化层薄膜,使部分栅绝缘层和部分漏电极暴露出来,在刻蚀时,采取过刻蚀使剩余的钝化层薄膜侧壁形成内凹的形貌;在基板上沉积一层透明导电薄膜,利用离地剥离工艺, 剥离尚存的光刻胶,其上沉积的透明导电薄膜也随之去除,所述部分栅绝缘星上表面以及所述部分漏电极上表面的透明导电薄膜保留下来,形成透明像素电极。 Channel electrode and the thin film transistor switching device; finally, depositing a passivation layer on a substrate; a third block mask photoresist pattern is formed by developing the plate exposed at the lithography, so that light remaining after exposure and development forming a vertical sidewall engraved rubber morphology, removing the passivation layer not covered by the photoresist film, so that part of the gate insulating layer and the exposed portion of the drain electrode, during the etching, to take over the passivation layer is etched so that the remaining morphology concave sidewall forming film; depositing a layer of a transparent conductive film on the substrate by a stripping-off process, the remaining photoresist is stripped, a transparent conductive film deposited thereon is also removed along with the portion of the gate and the upper surface of the insulating portion star drain electrode on the transparent conductive film surface retained to form a transparent pixel electrode.

其中,所述灰色调半透明掩膜版在基板上形成多层薄膜图案的方法包括下面一些步骤:在玻璃基板上沉积薄膜;在薄膜上涂布一层光刻胶;使用灰色调半透明掩膜版对光刻胶进行曝光,形成一定的图案;所述灰色调半透明掩膜版,包括完全透明区域、半透明区域和不透光区域,完全透明区域和半透明区域是具有不同透光率的两个透光部分,使得照射在光刻胶上的光强不同;用形成图案的光刻胶作为掩膜,对薄膜材料进行刻蚀,形成薄膜图案。 The method wherein the translucent gray-tone mask for forming a multilayer thin film pattern on a substrate comprising the following steps: depositing a thin film on a glass substrate; applying a layer of photoresist on the thin film; using a gray-tone mask translucent exposing the photoresist film plate, formed in a pattern; a translucent gray-tone mask, comprising a fully transparent area, semitransparent areas, and areas opaque, fully transparent and semitransparent regions are regions having different transmittances two of the light-transmitting portion, so that the irradiation of different light intensity on the resist; patterning with photoresist as a mask, the film material is etched to form a thin film pattern. 其中,所述灰色调半透明掩膜版定义的曝光显影后无光刻胶的区域包括透明像素电极、栅极扫描线和与外部电路连接部分;半透明区域包括薄膜晶体管沟道部分;曝光显影后保留全部光刻胶的区域包括源电极、漏电极和数据扫描线。 Wherein, the gray-tone mask translucent defined exposure after development of the resist-free region comprises a transparent pixel electrode, and a gate line external circuit connecting portion; semitransparent thin film transistor including a channel region portion; exposure and development after all photoresist retention region comprises a source electrode, a drain electrode and data line. 所述第三块掩膜版,在曝光显影形成所述钝化层图案时,控制曝光显影条件,形成侧壁垂直的光刻胶图案。 Said third block mask, exposed and developed in the patterned passivation layer is formed, exposed and developed control conditions, a photoresist pattern is formed perpendicular to the side walls. 曝光显影后,对所述钝化层薄膜刻蚀时,控制刻蚀条件,形成侧壁内凹的钝化层薄膜图案。 After exposure and development, a layer of the passivation film is etched, controlling the etching conditions, a thin film forming a passivation layer pattern side concave. 采用所述离地剥离工艺时,利用所述垂直的光刻胶侧壁和内凹的钝化层薄膜侧壁结构,可以使用不含腐蚀其他材料成分的普通光刻胶剥离液,所述剥离液只与光刻胶进行化学反应,从而仅对光刻胶进行剥离,不腐蚀包括透明导电薄膜在内的其它材料,光刻胶上的透明导电薄膜随光刻胶的剥离而被去除。 Employing the peeling-off process, using the photoresist side wall and perpendicular to the concave sidewall passivation layer structure, ordinary free of corrosive photoresist stripping liquid composition other materials, the release It was subjected only to resist chemistry, whereby only the photoresist stripping, other non-corrosive material comprises a transparent conductive film including the transparent conductive film on the resist with the stripping photoresist is removed.

本发明提供一种三次掩膜工艺的薄膜晶体管液晶显示器阵列基板的制造 The present invention provides a manufacturing three mask process of a thin film transistor array substrate of the liquid crystal

方法,使液晶显示器件的制造工艺得以简化,降低了液晶显示器件阵列基板制作的成本,提高了生产效率。 Method, the manufacturing process of the liquid crystal display device can be simplified, reducing the cost of the array substrate of the liquid crystal display device production, improve production efficiency. 相对其它三次掩膜工艺中第三块掩膜版必须是灰色调半透明掩膜,本发明的第三块掩膜版可以使用普通掩膜版,这样工艺过程中不必进行光刻胶灰化处理,进一步减少了工艺步骤以及相应的产品缺陷。 Compared to other three mask process block third mask must be translucent gray tone mask, the third block mask may be used in the present invention, an ordinary mask, so the process need not be ashing treatment further reducing the process steps and the corresponding defects. 本发明提供的一种薄膜晶体管液晶显示器阵列基板的结构不同于先前阵列基板,先前阵列基板上透明像素电极是在钝化保护膜过孔处和薄膜晶体管漏电极形成接触,本发明的阵列基板结构中去除钝化保护膜的过孔,代之以漏电极表面的全接触。 Array substrate structure of a thin film transistor liquid crystal provided by the present invention differs from previous array substrate, a transparent pixel electrode previously on the array substrate electrode is formed in the passivation film through the contact hole and the thin film transistor drain, an array substrate structure of the invention removing the passivation film via protection, instead of the full-contact surface of the drain electrode. 增大了透明像素电极和漏电极的接触面积,形成更可靠的电连接,有效提高了产品良率。 Increases the contact area transparent pixel electrode and the drain electrode, a more reliable electrical connection, effectively improve the yield of products. 传统的离地剥离工艺中使用特殊的剥离液,其除了对光刻胶进行剥离外,还腐蚀其他材料,而本发明优化了离地剥离工艺,提高了离地剥离工艺的效率和可靠性,降低了成本。 Conventional stripping-off process used in the special stripping solution, which in addition to the photoresist stripping, but also other corrosive materials, and the present invention optimizes the lifting-off process, the peeling-off process to improve the efficiency and reliability, reducing the cost. 上述特征以及优点在附图和具体实施例中得到更加明显的体现。 The above features and advantages be more clearly reflected in the drawings and specific embodiments.

附图说明 BRIEF DESCRIPTION

图la是先前五次掩膜工艺制作的一种典型薄膜晶体管像素结构俯视图; 图lb是先前五次掩膜工艺制作的一种典型薄膜晶体管像素结构截面图; 图2是典型的五次掩膜工艺技术流程; 图3是典型的四次掩膜工艺技术流程; 图4是本发明的三次掩膜工艺流程; FIG la is a typical plan view of a thin film transistor pixel structure previously made five mask process; FIG. Lb is a cross-sectional view of a typical pixel structure of a thin film transistor fabricated previous five mask process; FIG. 2 is a typical five mask technology flow; FIG. 3 is a typical four mask process technical process; FIG. 4 is a three mask process of the present invention;

图5a是本发明第一次掩膜的全部工艺完成后像素的俯视图; Figure 5a is a top plan view of the entire process of the present invention, the first complete pixel mask;

图5b是本发明第一次掩膜的全部工艺完成后图5a中AA处的截面图; FIG. 5b is a sectional view at AA of Figure 5a after all the process of the invention for the first time to complete the mask;

图6是本发明第二次掩膜的全部工艺完成后像素的俯视图; FIG 6 is a plan view of the entire process of the present invention, the second mask pixels is completed;

图7a是本发明第二次掩膜的光刻工艺完成后图6中AA处截面图; FIG 7a is a sectional view at AA of FIG. 6 after the second mask lithography process of the present invention has been completed;

图7b是本发明第二次掩膜的第一次刻蚀工艺完成后图6中AA处截面图; FIG 7b is a sectional view at AA of FIG. 6 after the first etching process of the present invention, the second mask is completed;

图7c是本发明第二次掩膜的光刻胶灰化工艺完成后图6中AA处截面图; Figure 7c is a sectional view at AA of FIG. 6 after the ashing process of the present invention, the second mask is completed;

图7d是本发明第二次掩膜的第二次刻蚀形成薄膜晶体管沟道的工艺和光 7d is a second second etching mask thin film transistor of the present invention is a process and an optical channel

刻胶剥离工艺完成后,图6中AA处截面图; After the stripping process is completed engraved rubber, cross-sectional view of FIG. 6 at AA;

图8是本发明第三次掩膜的全部工艺完成后像素的俯视图; FIG 8 is a plan view of the entire process of the present invention, the third mask pixels is completed;

图9是本发明第三次掩膜的光刻工艺完成后像素的俯视图; 9 is a plan view of a photolithography process of the present invention, the third mask pixels is completed;

图10a是本发明第三次掩膜的光刻工艺完成后图9中AA处的截面图; Figure 10a is a sectional view AA of FIG. 9 after the third mask of the photolithography process of the present invention is completed;

图10b是本发明第三次掩膜的刻蚀工艺完成后图9中AA处的截面图; Figure 10b is a sectional view AA of FIG. 9 after the etching process of the present invention, the third mask is completed;

图10c是本发明第三次掩膜的透明导电镀膜沉积工艺完成后图9中AA处 Figure 10c is a rear transparent conductive film deposition process of the present invention, the third mask is completed in FIG. 9 at AA

的截面图; The cross-sectional view;

图10d是图10c中B处的放大图; Figure 10d is an enlarged view at B 1OC;

图10e是本发明第三块掩膜的工艺完成后图8中AA处的截面图。 FIG. 10e is a sectional view AA of FIG. 8 after the third block of the present invention, the mask process is completed.

图中标识:1、栅极扫描线;2、栅电极;3、半导体层;4、栅绝缘层;5、数据扫描线;6、源电极;7、漏电极;8、钝化层;9、光刻胶上的透明导电薄膜;10、透明像素电极;11、没有光刻胶覆盖的钝化层部分;12、有光刻胶覆盖的钝化层部分;13、薄膜晶体管沟道部分;14、灰色调半透明掩膜版半透明部分对应区域的光刻胶;15、灰色调半透明掩膜版的不透明部分对应区域的光刻胶;16、光刻胶侧壁;17、钝化层薄膜侧壁。 FIG identified: 1, gate scanning lines; 2, a gate electrode; 3, a semiconductor layer; 4, a gate insulating layer; 5, data lines; 6, a source electrode; 7, a drain electrode; 8, a passivation layer; 9 , a transparent conductive film on the photoresist; 10, a transparent pixel electrode; 11, a portion of the passivation layer not covered by the photoresist; 12, a passivation layer portion covered by the photoresist; 13, the thin film transistor channel portion; 14, a photoresist mask gray translucent translucent portion corresponding to the region; 15, part of the photoresist corresponding to the opaque areas of the gray-tone mask translucent; 16, photoresist sidewalls; 17, passivating sidewall film layer.

具体实施方式 Detailed ways

下面结合附图和具体实施例,对本发明进行进一步详细说明: 首先,使用第一块掩膜版,在玻璃基板上形成栅极扫描线1和栅电极2: 参看图5a和图5b,先在玻璃基板上,通过磁控賊射或其它成膜方法形成第一层金属薄膜,即栅极金属薄膜。 In conjunction with the accompanying drawings and the following specific embodiments of the present invention will be further described in detail: First, using a first mask, forming gate scanning lines 2 and the gate electrode on a glass substrate: Referring to Figures 5a and 5b, the first on a glass substrate, forming a first metal thin film layer is emitted by magnetron thief or other film forming method, i.e. the gate metal film. 栅极金属薄膜的材料可以是钼、铝、铝镍合金、鴒、铬、或铜等金属,也可以是上述几种金属材料的合金。 The gate material may be a metal thin film of molybdenum, aluminum, aluminum-nickel alloys, alba, chromium, copper, or the like, alloy thereof may be of several metal materials. 在某些情况下还可以是多层膜结构,各层薄膜的材料可以从上述材料中挑选。 In some cases may also be a multilayer film structure, the film material of each layer may be selected from the above materials. 接下来使用第一块掩膜版,通过光刻和刻蚀工艺形成栅极扫描线1和栅电极2的图案。 Next, using a first mask, forming a patterned gate lines 1 and the gate electrode 2 by photolithography and etching processes. 然后,使用第二块掩膜版,形成栅绝缘层4、半导体层3、源电极6、漏 Then, a second block mask, a gate insulating layer 4, the semiconductor layer 3, the source electrode 6, drain

电极7和数据扫描线5等的图案,其中半导体层3包括有源层和欧姆接触层。 Pattern data electrodes 7 and the scanning lines 5 and the like, wherein the semiconductor layer 3 includes an active layer and an ohmic contact layer. 先在形成了栅极扫描线1和栅电极2的基板上,依次形成栅绝缘层4、半导体层3、以及用于形成数据扫描线5、源电极6和漏电极7的第二层金属层等多层薄膜,其中半导体层3包括一层本征半导体层,即有源层和一层掺杂半导体层,即欧姆接触层。 Forming a first gate lines on the substrate 1 and the gate electrode 2, forming a gate insulating layer 4, the semiconductor layer 3, and the data for forming the scanning lines 5, a second metal layer source electrode 6 and drain electrode 7 multi-layer film, wherein the semiconductor layer 3 comprises a layer of intrinsic semiconductor layer, i.e., an active layer and a doped semiconductor layer, i.e., ohmic contact layer. 栅绝缘层4可以采用氧化物、氮化物、氮氧化物、有机绝缘介质或其它绝缘介质。 The gate insulating layer 4 may be an oxide, nitride, oxynitride, or other insulating medium, an organic insulating medium. 栅绝缘层4和半导体层3可以通过等离子体辅助化学气相沉积或其它成膜方法形成,使用的反应气体可以包括但不限于SiH4、 NH3、 N2、 N20、 SiH2Cl2、 H2、 TE0S等。 The gate insulating layer 4 and the semiconductor layer 3 may be deposited film forming method or other formed by plasma-assisted chemical vapor reaction gas used may include but are not limited to SiH4, NH3, N2, N20, SiH2Cl2, H2, TE0S like. 所述第二层金属层可以通过磁控溅射或其它成膜方法形成,其材料可以是各种合适的金属或合金。 The second metal layer may be formed by magnetron sputtering or other film-forming methods, which may be of various materials suitable metal or alloy. 形成多层薄膜后,进行光刻胶涂布,然后使用第二块掩膜版进行曝光,所述的第二块掩膜版是灰色调半透明掩膜版,若使用正性光刻胶,所述灰色调半透明掩膜版的半透明区域包括薄膜晶体管的沟道部分13;完全透明区域包括透明像素电极IO、栅极扫描线1和与外部电路连接的部分;不透光区域包括源电极6、 漏电极7和数据扫描线5。 After forming the multilayer film, a photoresist is applied, and then using a second exposure mask block, said second block mask is translucent gray-tone mask, if positive photoresist is used, the gray-tone mask is translucent translucent area 13 includes a channel portion of the thin film transistor; fully transparent region comprises a transparent pixel electrode IO, and the gate line portion 1 is connected to an external circuit; opaque region comprises a source electrode 6, drain electrode 7 and the data line 5. 经过曝光显影后,形成如图7a所示的结构。 After exposure and development, the structure shown in FIG. 7a. 灰色调半透明掩膜版半透明部分对应区域的光刻胶14与灰色调半透明掩膜版的不透明部分对应区域的光刻胶15具有不同的厚度。 Gray-tone photoresist mask translucent translucent portion corresponding to the region of the opaque portion 14 and the photoresist region corresponding to a translucent gray-tone mask 15 having different thicknesses. 其它完全曝光的区域,即对应于掩膜版完全透明区域的光刻胶被去除。 Other fully exposed areas, i.e. corresponding to the fully transparent area of ​​the photoresist mask is removed. 然后进行第一次刻蚀,去除无光刻胶覆盖区域的多层薄膜,即去除透明像素电极10、栅极扫描线l和与外部电路连接部分等区域之上覆盖的第二层金属层和半导体层3,第一次刻蚀完成后如图7b所示。 Then a first etching, the multilayer film without removing the photoresist coverage area, i.e. remove the transparent pixel electrode 10, over the gate scanning line l and the like with an external circuit connecting portion of the second region covered by the metal layer and after the semiconductor layer 3, a first etching is completed as shown in FIG 7b. 然后对剩余的光刻胶进行灰化处理,减薄其厚度,使光刻胶厚度较薄的区域,即薄膜晶体管沟道部分13区域上方的光刻胶14去除,露出其下的第二层金属层,而其它光刻胶厚度较厚的区域上的光刻胶15仍保留有一定厚度,光刻胶灰化工艺完成后的结构如图7c所示。 Then the remaining photoresist ashing process, the thickness is thinned, so that a thin region of the photoresist, i.e., photoresist 14 is removed over the region of the thin film transistor channel portion 13, which is exposed in the second layer the metal layer, the photoresist on the thickness of the photoresist other thicker regions 15 still retains a certain thickness, structure after ashing process is completed as shown in FIG 7c. 接下来对薄膜晶体管沟道部分13上方的薄膜进行刻蚀,去除其上覆盖的第二层金属层和欧姆接触层,由于采用了过刻蚀,还将刻蚀掉部分厚度的有源层,形成薄膜晶体管沟道部分13,完成后如图7d所示。 Next, the thin film transistor above the channel portion 13 is etched to remove the second metal layer coated thereon and an ohmic contact layer, the use of over-etching will etch away part of the thickness of the active layer, forming a transistor channel portion of the film 13, after the completion shown in Figure 7d. 这样仅使用一块灰色调半透明掩膜版就完 In this way only a translucent gray tone mask to finish

成了栅绝缘层4、半导体层3 (包括有源层和欧姆接触层)、源电极6、漏电极7和教:据扫描线1等的图案,完成后的图案如图6所示。 4 become the gate insulating layer, a semiconductor layer 3 (including an active layer and an ohmic contact layer), a source electrode 6, drain electrode 7 and teach: 1, according to the scanning line like pattern, the pattern is completed as shown in FIG.

最后,使用第三块4备膜版,形成钝化层8、透明像素电极IO和透明像素电极10与漏电极7的电接触部分:先在第二块掩膜版形成的如图6所示的基板上沉积一层钝化层薄膜,其材料可以是氮化硅、氮氧化硅或其它合适的绝缘材料,沉积方法可以是等离子体辅助化学气相沉积或其它成膜方法。 Finally, the third block plate 4 Preparation of film, the passivation layer 8 is formed, and the transparent pixel electrode IO transparent pixel electrode contact portion 10 and the drain electrode 7: As shown in the second block first mask 6 is formed depositing a passivation layer on the substrate film, the material may be silicon nitride, silicon oxide or other suitable insulating material, deposition method may be plasma enhanced chemical vapor deposition or other deposition methods. 然后进行光刻胶涂布,使用第三块掩膜版进行曝光,所述的第三块掩膜版为普通掩膜版,即非灰色调半透明掩膜版。 The photoresist is then coated, using a third exposing mask block, said third block mask ordinary mask, i.e., non-translucent gray-tone mask. 曝光显影后,形成如图9和图10a所示的光刻胶图案,形成没有光刻胶覆盖的钝化层部分11和有光刻胶覆盖的钝化层部分12。 After exposure and development, a resist pattern is formed as shown in FIG. 9 and 10a, forming a passivation layer portion 11 is not covered by the photoresist and the photoresist 12 covering the portion of the passivation layer. 接下来进行刻蚀,去除没有光刻胶覆盖的钝化层部分ll,这样一部分栅绝缘层4和部分漏电极7暴露出来,如图10b所示。 Next etching, removing portions of the passivation layer not covered by the photoresist ll, so that a part of the gate insulating layer 4 and the exposed portion of the drain electrode 7, shown in Figure 10b. 完成刻蚀后,接着沉积透明导电薄膜,如图10c所示。 After completion of the etching, and then depositing a transparent conductive film 10c shown in FIG. 图10d所示的图10c中B处的形貌是通过在光刻和刻蚀工艺中控制工艺条件获得的,在光刻时,使曝光显影后剩余光刻胶侧壁16形成垂直的形貌,在刻蚀时,采取过刻蚀使剩余的钝化层薄膜侧壁17形成内凹的形貌。 The remaining photoresist 16 forming a vertical sidewall morphology of topography at B in FIG. 10c shown in FIG. 10d by controlling the process conditions in the lithography and etch processes obtained when lithography, exposure and development so that when etching, over-etching of the film to take the remaining sidewall passivation layer 17 is formed concave topography. 这样当沉积透明导电薄膜时,垂直的光刻胶侧壁16和内凹的钝化层薄膜侧壁17上基本不会沉积上透明导电薄膜。 Such that when depositing a transparent conductive film, a photoresist film vertical sidewall 16 and concave sidewall passivation layer 17 does not substantially deposited on the transparent conductive film. 沉积完透明导电薄膜后,采用离地剥离工艺,剥离剩余的光刻胶及其上的透明导电薄膜, 由于垂直的光刻胶侧壁16和内凹的钝化层薄膜侧壁17上基本没有透明导电薄膜,这样透明导电薄膜在内凹的钝化层薄膜侧壁17处就断开来,光刻胶剥离液能够很容易地从所述断开处接触光刻胶侧壁16从而对光刻胶进行剥离, 因此所述的剥离液只与光刻胶进行化学反应,不腐蚀包括透明导电薄膜在内的其它材料,而光刻胶上的透明导电薄膜是随光刻胶的剥离而被去除的。 After depositing a transparent conductive film, using the lifting-off process, the remaining photoresist is peeled off and the transparent conductive thin film, since the film side wall 16 and the vertical sidewalls of the photoresist layer 17 is recessed substantially no passivation the transparent conductive film, and a transparent conductive thin film passivation layer at the concave side wall 17 is disconnected, the photoresist stripping solution in contact with the photoresist can be easily disconnected from the side wall 16 so that the light engraved rubber peeling, the peeling liquid so only chemically react with the photoresist, other non-corrosive materials include transparent conductive films are, the transparent conductive film on the resist is peeled off with the photoresist is removed. 离地剥离工艺完成后的结构如图10e所示,形成的透明像素电极10与漏电极7 的表面全接触,而且透明像素电极10与漏电极7 —侧的有缘层和欧姆接触层的侧壁也直接接触,从而使透明像素电极10与漏电极7形成良好的电连接。 Transparent pixel electrode structure after lifting-off process is completed as shown in FIG. 10e, full contact surface 10 formed on the drain electrode 7, and the transparent pixel electrode 10 and the drain electrode 7-- affinity sidewall layer side and the ohmic contact layer also in direct contact with, the pixel electrode 10 such that the transparent electrode 7 to form a good electrical connection with the drain. 在透明像素电极10其它边沿处,透明像素电极10与钝化层薄膜在内凹的钝化层薄膜侧壁17处断开。 In other edge 10 of the transparent pixel electrode, the transparent pixel electrode 10 and the passivation layer film passivation layer at the concave side wall 17 turned off. 最终形成的薄膜晶体管阵列单元结构如图8和10e 所示。 The thin film transistor array unit resulting structure shown in FIG. 8 and 10e.

通过上述步骤,使用三块掩膜版完成了本发明的薄膜晶体管阵列基板的制作。 Through the above steps, the use of three mask completed the production of the thin film transistor array substrate of the present invention. 本实施例仅用于说明而不是限定本发明所述的薄膜晶体管阵列基板及其制造方法。 The present embodiment are illustrative only, rather than a thin film transistor array substrate and a manufacturing method of the present invention is defined. 除非特别指出的部分,本发明不局限于上述描述的具体细节。 Unless otherwise indicated portion, the present invention is not limited to specific details of the foregoing description. 在不偏离实质性特征和核心工艺技术的前提下,本发明还有其它的具体实施例。 Without departing from the essential features and the core technology, there are other particular embodiments of the invention. 任何符合本发明特征的修改和变化,都在本发明的范围之内。 Any modifications and variations consistent with the characteristics of the invention are within the scope of the invention.

Claims (8)

1.一种薄膜晶体管阵列基板结构,包括:玻璃基板,形成于玻璃基板上的栅极扫描线、数据扫描线、薄膜晶体管和透明像素电极,所述透明像素电极和所述薄膜晶体管漏电极的电连接是通过透明像素电极覆盖到薄膜晶体管漏电极的上表面,形成表面接触的结构实现的,所述薄膜晶体管包括栅电极,所述栅电极上依次形成有栅绝缘层、半导体层、源电极、漏电极和钝化层薄膜,其特征在于:所述透明像素电极在钝化层薄膜的内凹侧壁处断开,所述像素电极与钝化层薄膜没有重叠的部分。 1. A thin film transistor array substrate, comprising: a glass substrate, a gate electrode formed on a glass substrate, scanning lines, data lines, thin film transistors and transparent pixel electrodes, the transparent pixel electrode and the drain electrode of the thin film transistor is electrically connected to the transparent pixel electrodes covered by a thin film transistor on the surface of the drain electrode is formed in contact with the surface of the structure to achieve the thin film transistor includes a gate electrode, a gate insulating layer are sequentially formed on the gate electrode, a semiconductor layer, a source electrode , the drain electrode and the passivation layer, wherein: the transparent pixel electrode is disconnected at the concave side wall of the passivation layer, the pixel electrode and the passivation layer of the film does not overlap.
2、 一种薄膜晶体管阵列基板的制造方法,其特征在于:首先,提供一个绝缘透明衬底;在绝缘衬底上依次形成第一层金属薄膜和一层光刻胶;使用第一块掩膜版定义光刻胶的图案,并刻蚀形成第一层金属薄膜的图案,即栅电极和栅极扫描线;然后,在基板上沉积一层绝缘层、沉积至少一层半导体层和沉积一层金属薄膜;在金属薄膜上涂布一层光刻胶;使用第二块掩膜版,即灰色调半透明掩膜版,经过曝光显影和刻蚀形成薄膜晶体管硅岛,利用光刻胶灰化工艺和刻蚀,形成源电极、漏电极和薄膜晶体管开关器件的沟道;最后,在基板上沉积一层钝化层薄膜;用第三块掩膜版通过曝光显影形成光刻胶图案,在光刻时,使曝光显影后剩余光刻胶侧壁形成垂直的形貌,去除未被光刻胶覆盖的钝化层薄膜,使部分栅绝缘层和部分漏电极暴露出来,在刻蚀时 2. A method for manufacturing a thin film transistor array substrate, comprising: providing a transparent insulating substrate; forming a first metal thin film layer and a layer of photoresist on the insulating substrate; using a first mask version defined photoresist pattern, and etching to form a first metal thin film layer pattern, i.e., the gate electrode and gate scanning line; then, depositing an insulating layer on the substrate, depositing at least one semiconductor layer and depositing a layer a metal thin film; applying a layer of photoresist on the metal film; a second block mask, i.e. translucent gray tone mask, development and etching through the exposed silicon thin film transistor islands, using a photoresist ashing and etching process, forming a source electrode, a drain electrode and a thin film transistor switching device channels; finally, depositing a passivation layer on a substrate; a third block mask pattern is developed to form a photoresist by exposure, in when photolithography, the exposed photoresist remaining after development form a vertical sidewall morphology, removing the passivation layer not covered by the photoresist film, so that part of the gate insulating layer and the exposed portion of the drain electrode, when etching 采取过刻蚀使剩余的钝化层薄膜侧壁形成内凹的形貌; 在基板上沉积一层透明导电薄膜,利用离地剥离工艺,剥离尚存的光刻胶, 其上沉积的透明导电薄膜也随之去除,所述部分栅绝缘层上表面以及所述部分漏电极上表面的透明导电薄膜保留下来,形成透明像素电极。 Taking over-etching the thin film remaining sidewall passivation layer is formed concave morphology; depositing a layer of a transparent conductive film on the substrate by a stripping-off process, the remaining photoresist is stripped, a transparent conductive deposited thereon also will remove a thin film, the surface portion of the gate insulating layer and the upper portion of the drain electrode of the transparent conductive film surface retained to form a transparent pixel electrode.
3、 根据权利要求2所述的一种薄膜晶体管阵列基板的制造方法,其特征在于:由所述灰色调半透明掩膜版定义的曝光显影々无光刻胶的区域包括透明像素电极、栅极扫描线和与外部电路连接部分;半透明区域包括薄膜晶体管沟道部分;保留全部光刻胶的区域包括源电极、漏电极和数据扫描线。 3, a method for manufacturing a thin film transistor array substrate according to claim 2, wherein: said exposure and developing 々 a translucent gray-tone mask defined region without resist comprising a transparent pixel electrode, the gate scan electrode lines and the external circuit connecting portion; semitransparent thin film transistor including a channel region portion; retaining all photoresist region comprises a source electrode, a drain electrode and data line.
4、 根据权利要求2或3所述的一种薄膜晶体管阵列基板的制造方法,其特征在于:所述曝光显影形成所述钝化层图案时,控制曝光显影条件形成侧壁垂直的光刻胶图案。 A method for manufacturing a thin film transistor array substrate 4, according to claim 2 or claim 3, wherein: said exposure and developing the passivation layer pattern is formed, the control conditions of exposure and development of photoresist is formed perpendicular to the side walls pattern.
5、 根据权利要求2或3所述的一种薄膜晶体管阵列基板的制造方法,其特征在于:对所述钝化层薄膜刻蚀时,形成侧壁内凹的钝化层薄膜图案。 A method for manufacturing a thin film transistor array substrate 5, as claimed in claim 2 or claim 3, wherein: of said passivation layer is etched, and the passivation layer pattern is formed concave sidewalls.
6、 根据权利要求4所述的一种制作薄膜晶体管阵列基板的制造方法,其特征在于:对所述钝化层薄膜刻蚀时,形成侧壁内凹的钝化层薄膜图案。 A method for manufacturing a thin film transistor array substrate making 6, according to claim 4, wherein: of said passivation layer is etched, and the passivation layer pattern is formed concave sidewalls.
7、 根据权利要求2或3所述的一种薄膜晶体管阵列基板的制造方法,其特征在于:所述第三块掩膜版是普通的掩膜版;采用所述离地剥离工艺时, 剥离液只与光刻胶进行化学反应,不腐蚀包括透明导电薄膜在内的其它材料, 光刻胶上的透明导电薄膜随光刻胶的剥离而被去除。 7. The method of manufacturing a thin film transistor array substrate of claim 2 or 3, wherein: said third mask is an ordinary block mask; peeling-off process using the peeling was subjected only to resist chemistry, other non-corrosive material comprises a transparent conductive film including the transparent conductive film on the resist with the stripping photoresist is removed.
8、 根据权利要求6所述的一种薄膜晶体管阵列基板的制造方法,其特征在于:所述第三块掩膜版是普通的掩膜版;采用所述离地剥离工艺时,剥离液只与光刻胶进行化学反应,不腐蚀包括透明导电薄膜在内的其它材料,光刻胶上的透明导电薄膜随光刻胶的剥离而被去除。 8. The method for manufacturing a thin film transistor array substrate according to claim 6, wherein: said third mask is an ordinary block mask; using the peeling-off process, only the stripping solution chemical reaction with the photoresist, other non-corrosive material comprising a transparent conductive film including the transparent conductive film on the resist with the stripping the photoresist is removed.
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