WO2018094595A1

WO2018094595A1 - Manufacturing method of array substrate

Info

Publication number: WO2018094595A1
Application number: PCT/CN2016/106886
Authority: WO
Inventors: 洪日
Original assignee: 深圳市柔宇科技有限公司
Priority date: 2016-11-23
Filing date: 2016-11-23
Publication date: 2018-05-31
Also published as: CN107836039A

Abstract

The present application provides a manufacturing method of an array substrate, comprising: forming a gate, a gate insulating layer, a metal oxide semiconductor layer, and a metal layer sequentially on a substrate; coating a photoresist on the metal layer; providing a multi-grayscale mask plate which is used to pattern the photoresist so as to form a semi-exposed region on the photoresist; etching the metal layer by using the photoresist as a masking layer such that the etched metal layer has a source drain layer pattern; removing the photoresist at the semi-exposed region to expose the metal layer under the semi-exposed region; dry etching the metal layer exposed under the semi-exposed region to expose the metal oxide semiconductor layer so as to form a channel; and removing the photoresist. The present application will not damage the metal layer during the formation of the channel, thereby improving the production yield of the array substrate.

Description

Array substrate manufacturing method

Technical field

The present application relates to the field of display technologies, and in particular, to a method for fabricating an array substrate.

Background technique

Currently, a metal oxide material is used as an active layer in the array substrate. In the manufacturing process of the array substrate in the prior art, there are mainly the following problems: when the conventional wet etching performs the patterning process of the source and the drain, an acid etching pattern is used, and the metal oxide is generally not resistant to acid, so that the conventional process may corrode part. The active layer affects the performance of the array substrate. If dry etching is used, the etching gas damages the surface of the source and drain metal layers, which also affects the performance of the array substrate.

Summary of the invention

The purpose of the application is to provide a method for manufacturing an array substrate, which can avoid corrosion of the active layer during the manufacturing process and improve the performance of the array substrate.

To achieve the above objective, the present application provides the following technical solutions:

The present application provides a method of fabricating an array substrate, the method comprising:

Forming a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, and a source/drain metal layer on the substrate;

Forming a metal layer covering the gate insulating layer and the metal oxide semiconductor layer and coating a photoresist on the source and drain layers on the metal layer;

Providing a multi-gray mask for patterning the photoresist with the multi-gray mask to form a half-exposure region on the photoresist;

Etching the metal layer source and drain layers with the photoresist as a shielding layer, so that the etched metal layer has a source/drain layer patterning;

Removing the photoresist at the half-exposed area to expose the metal layer under the half-exposed area;

Dry etching the exposed metal layer under the half exposed region to expose the metal oxide semiconductor layer to form a channel;

The photoresist is removed.

Wherein the step of dry etching the exposed metal layer under the semi-exposed region to expose the metal oxide semiconductor layer to form a trench includes using an etching gas to the source/drain layer metal layer A portion exposed to the fully exposed region is bombarded to expose the metal oxide semiconductor layer to form a channel.

Wherein, by controlling an etching rate and an etching time of the etching gas in the source/drain layer metal layer, the metal oxide semiconductor layer is partially exposed to the channel, wherein an etching rate and the etching time are both Is the default value.

Wherein, the etching gas is a mixture of one or any of SF6, O2, Cl2, He, Ar.

Wherein, the photoresist is used as a shielding layer, and the metal layer is etched, so that the etched metal layer has a source/drain layer pattern with the photoresist as a shielding layer, and the source and drain electrodes are The layer is etched such that the source and drain layer patterning step includes etching the etchant on the source/drain layer metal layer for etching, and removing the etchant after the source/drain layer metal layer is patterned.

Wherein, the etching solution comprises H2O2, a metal chelating agent or an organic acid.

Wherein the step of removing the photoresist at the semi-exposed region to expose the metal layer under the semi-exposed region comprises ashing the photoresist to make the semi-exposed region The photoresist at the place is removed.

Wherein the ashing treatment comprises exciting oxygen into a plasma to react with the photoresist, so that the photoresist at the half-exposed region is removed.

Wherein the step of removing the photoresist comprises: removing the photoresist by an ashing process or a wet etching process.

Wherein, the multi-gray mask is a halftone mask or a gray mask.

Wherein, the metal oxide semiconductor layer is made of an IGZO material.

The embodiments of the present application have the following advantages or benefits:

In the method for fabricating the array substrate of the present application, a photoresist is coated on the source/drain metal layer, and a half-exposure region is formed on the photoresist by a multi-gray mask, and the photoresist is used as a mask. a layer, the metal layer is etched such that the metal layer has a source/drain layer pattern, and then the semi-exposed region of the photoresist is converted into a fully exposed region, and the metal layer under the half-exposed region is dried Etching to expose the metal oxide semiconductor layer, thereby causing no damage to the metal layer during dry etching to expose the metal oxide semiconductor layer, improving the production yield of the array substrate.

DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings to be used in the embodiments will be briefly described below. Obviously, the drawings in the following description are only some of the present application. For the embodiments, those skilled in the art can obtain other drawings according to the drawings without any creative work.

1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present application.

2 to 8 are schematic views of processes of the manufacturing method shown in Fig. 1.

detailed description

The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.

The ordinal qualifiers used in the following embodiments of the present application, the first, second, etc. are merely for the purpose of clearly indicating the distinctive features of the similar features in the present application, and do not represent the order of the corresponding features or the order of use.

The array substrate produced by the manufacturing method of the present application can be applied to a liquid crystal display or an organic display. The flexible display screen according to the embodiment of the present invention is used for, but not limited to, a mobile phone, a tablet computer, a palmtop computer, a personal digital assistant (PDA), or an e-reader.

Please refer to FIG. 1. FIG. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present application. The manufacturing method provided by the present application mainly includes the following steps:

Step S001: sequentially forming a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, and a metal layer on the substrate.

Specifically, please refer to Figure 2. The substrate 10 is a transparent glass substrate on which a first metal thin film is deposited. The first metal film may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs. A pattern of a gate line (not shown), a common electrode line (not shown), and a gate electrode 20 is formed by a patterning process using a conventional photoresist. Then, on the basis of this, the gate insulating layer 30 is deposited by a PECVD (plasma enhanced chemical vapor deposition) method, and the gate insulating layer 30 may be an oxide, a nitride or an oxynitride.

Then, the metal oxide semiconductor layer 40 is deposited on the gate insulating layer 30 by sputtering or thermal evaporation. The metal oxide semiconductor layer 40 may be IGZO (indium gallium zinc oxide), HIZO, IZO. , a-InZnO, a-InZnO, ZnO: F, In2O3: Sn, In2O3: Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxide. Preferably, it can be made of IGZO material.

Next, a metal layer 50 is formed on the substrate 10 by sputtering or thermal evaporation. The metal layer 50 is made of a metal or an alloy which is excellent in electrical conductivity and which is easy to dry. For example, a metal or an alloy such as Al, Cr, W, Cu, Ti, Ta, or Mo may be used, and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs. Preferably, it may be made of a copper or copper alloy material.

Step S002: coating a photoresist on the metal layer.

Optionally, the thickness of the photoresist may be between 1.5 um and 2 um, and the specific thickness may be adjusted according to actual conditions.

Step S003: providing a multi-gray mask, the photoresist is patterned by using the multi-gray mask to form a half-exposure region on the photoresist.

Specifically, please refer to Figure 3. A photoresist 60 is coated on the metal layer 50; a multi-gray mask 80 is provided over the photoresist 60. Optionally, the multi-gray mask 70 may be a half tone mask or a gray tone mask. The photoresist 60 is exposed and developed (i.e., patterned). The multi-gray mask 80 is provided with a fully transparent region 81, a semi-transmissive region 82, and an opaque region 83. The photoresist 60 is photolithographically exposed through the multi-gray mask 80. Referring to FIG. 4, the photoresist 60 under the fully transparent region 81 is completely photolithographically formed to form the full exposed region 61, and the metal layer 50 under the fully exposed region 61 is exposed to the photoresist 60. The photoresist 60 under the semi-transmissive region 82 is partially photolithographic to form a half-exposure region 62. The photoresist 60 under the opaque region 81 is retained. That is, the photoresist 60 is patterned to form a half-exposure region 81 thereon.

Optionally, the thickness of the half-exposure region 81 may be between 0.5 um and 1 um, and the specific thickness may be adjusted according to actual conditions.

S004: etching the metal layer by using the photoresist as a shielding layer, and the etched metal layer has a source/drain layer pattern.

Specifically, please refer to Figure 5. An etchant may be sprayed on the photoresist 60 and the metal layer 50, and the etchant etches the metal layer 50 through the full exposed region 61 on the photoresist 60 until the The metal layer 50 is formed with a source and drain layer pattern, and finally the etching liquid is removed to complete the patterning process of the metal layer 52.

Preferably, the etching solution may be selected from H ₂ O ₂ , a metal chelating agent or an organic acid.

S005: removing the photoresist at the half-exposed area to expose the metal layer under the half-exposed area.

Please refer to Figure 6 in combination. Specifically, the photoresist 60 may be subjected to ashing treatment so that the photoresist at the half exposure region 62 is removed. It can be understood that the "ashing treatment" is to excite oxygen into a plasma, and then react the oxygen excited into the plasma with the photoresist, thereby thinning the photoresist 60 as a whole, and the photoresist 60 as a whole. After thinning, the photoresist at the half-exposure region 62 will first be completely removed, i.e., the half-exposed regions will be converted to the fully exposed regions 62. At this time, the metal layer 50 is partially exposed to the fully exposed region 62.

S006: dry etching the metal layer exposed under the half exposed region to expose the metal oxide semiconductor layer to form a channel.

Referring to FIG. 7, in this step, a channel 53 needs to be formed, and a source 51 and a drain 52 are formed on the metal layer 50. With a 50 body, a channel 53 can be etched on the metal layer 50 by dry etching, and the metal oxide semiconductor layer 40 is partially exposed to the channel 53. At the same time, the source 51 and the drain 52 are formed by the channel 53.

More specifically, in the dry etching process, the etching gas may be placed in a low pressure environment, and a voltage is applied to excite the etching gas into a plasma, and then the metal layer 50 is bombarded to etch the metal layer 50. Due to the presence of photoresist 60, metal layer 50 underlying fully exposed region 62 will be etched. Located below the photoresist 60 except for the area corresponding to the full exposure region 62, the metal layer 50 under the non-full exposure region of the photoresist 60 is protected from etching by the etching gas due to the presence of the photoresist 60. Further, the depth of the etching may be controlled by controlling the etching time of the etching gas on the metal layer 50 until the portion of the metal layer 50 directly under the full exposure region 62 is completely etched, thereby forming the channel 53, and The metal oxide semiconductor layer 40 partially exposes the channel 53. Wherein, the etching time is a preset value. At this time, the metal layer 50 is divided into the source 51 and the drain 52 through the channel 53.

Preferably, the etching gas may be appropriately selected according to the material selected for the metal layer 50. For example, one or a combination of SF ₆ , O ₂ , Cl ₂ , He, Ar (argon) may be selected.

In the present application, during the formation of the trench by dry etching, the photoresist 60 can function to protect other portions of the metal layer 50, thereby avoiding surface quality degradation of the metal layer 50 due to dry etching. And improve the performance of the array substrate.

S007: removing the photoresist.

Referring to FIG. 8, after the metal oxide semiconductor layer 40 partially exposes the channel 53, the dry etching may be stopped, the photoresist 60 may be removed, and the subsequent steps may be continued to complete the fabrication of the array substrate. The subsequent steps are not the focus of the protection of the present invention and will not be described here.

Removing the photoresist 60 may strip the photoresist using a wet etch process. The process can use the prior art photoresist stripping method, and details are not described herein again. Alternatively, the photoresist may be removed using the ashing process described above.

In the method for fabricating an array substrate of the present application, a photoresist is coated on the metal layer, and a half-exposure region is formed on the photoresist by a multi-gray mask, and the photoresist is used as a shielding layer. The metal layer is etched such that the metal layer has a source/drain layer pattern, and then the half exposed region of the photoresist is converted into a full exposed region, and the metal layer under the half exposed region is dry etched to The channel is formed and the metal oxide semiconductor layer is exposed, so that the metal layer is not damaged during dry etching to expose the metal oxide semiconductor layer, and the production yield of the array substrate is improved.

The embodiments of the present application have been described in detail above. The principles and implementations of the present application are described in the specific examples. The description of the above embodiments is only used to help understand the method and core ideas of the present application. A person skilled in the art will have a change in the specific embodiments and the scope of the application according to the idea of the present application. In summary, the content of the present specification should not be construed as limiting the present application.

Claims

A method of manufacturing an array substrate, the method comprising:

Forming a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, and a metal layer on the substrate;

Coating a photoresist on the metal layer;

Providing a multi-gray mask for patterning the photoresist with the multi-gray mask to form a half-exposure region on the photoresist;

The metal layer is etched by using the photoresist as a shielding layer, so that the etched metal layer has a source/drain layer pattern;

Removing the photoresist at the half-exposed area to expose the metal layer under the half-exposed area;

Dry etching the exposed metal layer under the half exposed region to expose the metal oxide semiconductor layer to form a channel;

The photoresist is removed.
The method of manufacturing an array substrate according to claim 1, wherein the step of exposing the metal layer exposed under the half-exposed region to expose the metal oxide semiconductor layer to form a channel is performed And irradiating a portion of the metal layer exposed to the fully exposed region with an etching gas to expose the metal oxide semiconductor layer to form a channel to expose the metal oxide semiconductor layer to form a channel.
The method of manufacturing an array substrate according to claim 2, wherein the metal oxide semiconductor layer is partially exposed to the channel by controlling an etching time of the etching gas in the metal layer, wherein The etching time is a preset value.
The method of manufacturing an array substrate according to claim 2, wherein the etching gas is a mixture of one or any of SF 6 , O 2 , Cl 2 , He, Ar.
The method of fabricating an array substrate according to claim 1, wherein the step of etching the metal layer with the photoresist as a shielding layer so that the etched metal layer has a source/drain layer pattern step The method further includes spraying an etchant on the metal layer for etching, and removing the etching solution after the metal layer is patterned.
The method of manufacturing an array substrate according to claim 5, wherein the etching solution comprises H 2 O 2 , a metal chelating agent or an organic acid.
The method of manufacturing an array substrate according to claim 1, wherein the removing the photoresist at the half-exposed region to expose the metal layer under the half-exposed region comprises The photoresist is subjected to ashing treatment so that the photoresist at the half-exposed area is removed.
The method of manufacturing an array substrate according to claim 7, wherein the ashing treatment comprises exciting oxygen gas into a plasma to react with the photoresist, so that the photoresist at the half exposure region is Remove.
The method of manufacturing an array substrate according to claim 1, wherein the removing the photoresist comprises: removing the photoresist by an ashing process or a wet etching process.
The method of manufacturing an array substrate according to claim 1, wherein the multi-gray mask is a halftone mask or a gray mask.
The method of manufacturing an array substrate according to claim 1, wherein the metal oxide semiconductor layer is made of an IGZO material.