WO2018094598A1

WO2018094598A1 - Method for manufacturing array substrate

Info

Publication number: WO2018094598A1
Application number: PCT/CN2016/106890
Authority: WO
Inventors: 尚琼
Original assignee: 深圳市柔宇科技有限公司
Priority date: 2016-11-23
Filing date: 2016-11-23
Publication date: 2018-05-31
Also published as: CN108064414A

Abstract

A method for manufacturing an array substrate, comprising: forming a gate electrode, a gate line, a gate insulating layer, a metal-oxide semiconductor layer, and an etch stopping layer on a substrate (S1); forming a photoresist on the etch stopping layer (S2); providing a multi-greyscale mask plate to form a semi-exposure region and a full-exposure region on the photoresist (S3); performing first etching on the etch stopping layer and the gate insulating layer to form a first via hole, leading to the gate line, on the etch stopping layer and the gate insulating layer (S4); removing the photoresist of the semi-exposure region (S5); performing second etching on the etch stopping layer to form a second via hole, leading to the metal-oxide semiconductor layer, below the semi-exposure region (S6); and removing the photoresist (S7). The manufacturing method would not damage the metal-oxide semiconductor layer when the first via hole is formed, thereby improving the yield rate of array substrates.

Description

Array substrate manufacturing method

Technical field

The present application relates to the field of display technologies, and in particular, to a method for fabricating an array substrate.

Background technique

In the prior art, in order to reduce the manufacturing cost of the array substrate. The gate insulating layer (GI) and the etch stop layer (ES) are typically processed using the same mask. However, since the thickness of the gate insulating layer is much larger than the thickness of the etch barrier layer, the metal oxide semiconductor layer under the etch barrier layer is exposed during the via hole formation by dry etching on the gate insulating layer. Since the etching time of the gate insulating layer is long, damage to the exposed metal oxide semiconductor layer is caused, and therefore it is necessary to increase the thickness of the metal oxide semiconductor layer. Increasing the thickness of the metal oxide semiconductor layer increases the manufacturing cost and reduces the productivity. On the other hand, an excessively thick metal oxide semiconductor layer deteriorates TFT characteristics, eventually resulting in a decrease in product yield.

In addition, when the metal oxide semiconductor layer is etched through, there is also a risk of short-circuiting the gate electrode layer and the source and drain layers.

Application content

The purpose of the present application is to provide a method for fabricating an array substrate, which can avoid damage to a metal oxide semiconductor layer during formation of via holes on a gate insulating layer, and improve production yield of the array substrate.

To achieve the above objective, the present application provides the following technical solutions:

The application provides a method for manufacturing an array substrate, comprising:

Forming a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor layer, and an etch barrier layer on the substrate;

Forming a photoresist on the etch barrier layer;

Providing a multi-gray mask for patterning the photoresist with the multi-gray mask to form a half-exposure region and a full-exposure region on the photoresist, wherein the a projection of the exposed region on the gate line at least partially coincides with the gate line, and a projection of the half-exposed region on the metal oxide semiconductor layer at least partially coincides with the metal oxide semiconductor layer;

Using the photoresist as a shielding layer, performing first etching on the etch barrier layer and the gate insulating layer under the entire exposed region of the photoresist to form an etch barrier directly under the full exposure region And forming a first via hole to the gate line on the gate insulating layer;

Removing the photoresist of the half exposed region;

Performing a second etching on the etch barrier layer by using the photoresist as a shielding layer to form a second via hole to the metal oxide semiconductor layer directly under the photoresist half exposure region;

The photoresist is removed.

Wherein, the method further comprises: ashing the semi-exposed area of the photoresist to remove the photoresist of the semi-exposed area.

Wherein, the method further comprises: performing dry etching on the etch barrier layer and the gate insulating layer to form the first via.

Wherein, the method further comprises: performing dry etching on the etching barrier layer to form the second via hole.

The etching gas used in the dry etching is a mixture of one or any of SF6, O2, Cl2, He, Ar.

Wherein, the method further comprises: after the step of removing the photoresist is completed, forming a source and a drain in the second via, and forming a metal layer in the first via to connect the signal circuit.

Wherein, the multi-gray mask is a halftone mask or a gray mask.

Wherein the step of removing the photoresist comprises: removing the photoresist by an ashing process or a wet etching process.

The projection of the full exposure region on the gate line is included in the gate line, and a projection of the half exposure region on the metal oxide semiconductor layer is included in the metal oxide semiconductor layer.

Wherein, the etching barrier layer is made of silicon oxide, silicon nitride or a mixture of the two.

Wherein, the gate insulating layer is made of silicon oxide, silicon nitride or a mixture of the two.

The embodiments of the present application have the following advantages or benefits:

In the method for fabricating an array substrate of the present application, a photoresist is coated on the etching stopper layer, and a half exposure region and a full exposure region are formed on the photoresist through a multi-gray mask, and formed under the entire exposure region. A first via hole leading to the gate line forms a second via hole leading to the metal oxide semiconductor layer under the half exposure region. Therefore, the metal oxide semiconductor layer is not damaged when the first via hole is formed, and the damage is improved. The production yield of the array substrate.

DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings to be used in the embodiments will be briefly described below. Obviously, the drawings in the following description are only some of the present application. For the embodiments, those skilled in the art can obtain other drawings according to the drawings without any creative work.

1 is a flow chart of a method for manufacturing an array substrate of the present application.

2 to 5 are schematic flow charts showing a method of manufacturing the array substrate shown in FIG. 1.

detailed description

The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.

The ordinal qualifiers used in the following embodiments of the present application, the first, second, etc. are merely for the purpose of clearly indicating the distinctive features of the similar features in the present application, and do not represent the order of the corresponding features or the order of use.

Please refer to FIG. 1. FIG. 1 is a flow chart of a method for fabricating an array substrate of the present application. In an embodiment of the present application, a method for manufacturing an array substrate includes the following steps:

Step S1: sequentially forming a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor layer, and an etch barrier layer on the substrate.

Specifically, referring to FIG. 2, the pattern of the gate electrode 21 and the gate line 22 may be formed on the substrate 10 by one patterning process. The gate electrode 21 and the gate line 22 are made of the same material, for example, a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal can also meet the needs. .

Then, a gate insulating layer 30 is deposited by the PECVD (Plasma Enhanced Chemical Vapor Deposition) method over the gate electrode 21 and the gate line 22. The gate insulating layer 30 covers the gate electrode 21 and the gate line 22. The gate insulating layer 30 may be selected from materials including, but not limited to, silicon oxide, silicon nitride, or a mixture of the two.

The metal oxide semiconductor layer 40 can also be deposited on the gate insulating layer 30 by sputtering or thermal evaporation. The metal oxide semiconductor layer 40 can be IGZO (indium gallium zinc oxide), HIZO. , IZO, a-InZnO, a-InZnO, ZnO: F, In2O3: Sn, In2O3: Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxide. Preferably, it can be made of IGZO material.

The etch stop layer 50 may be silicon oxide, silicon nitride, or a mixture of the two. The gate insulating layer 30 is deposited by chemical vapor deposition, and the etch barrier layer 50 completely covers the metal oxide semiconductor layer 40. The metal oxide semiconductor layer 40 functions to protect the underlying structure under the etching barrier layer 50 from the end of the wet etching of the source and drain layers when the source and drain layers (not shown) are wet etched. Etched.

Step S2: forming a photoresist on the etch barrier layer.

Step S3: providing a multi-gray mask, using the multi-gray mask to pattern the photoresist to form a half-exposure region and a full-exposure region on the photoresist, wherein a projection of the fully exposed region on the gate line at least partially coincides with the gate line, a projection of the half-exposed region on the metal oxide semiconductor layer and at least a portion of the metal oxide semiconductor layer coincide.

Optionally, the multi-gray mask 70 may be a half tone mask or a gray tone mask. The multi-gray mask 70 is overlaid over the photoresist 60. The photoresist 60 is exposed, developed (i.e., photolithographically) to complete patterning. After the photoresist 60 is subjected to a photolithography process, a full exposure region 61 and a half exposure region 62 are formed. Wherein the projection of the full exposure region 61 on the gate line 22 at least partially coincides with the gate line 22, the projection of the half exposure region 62 on the metal oxide semiconductor layer 40 and the The metal oxide semiconductor layer 40 at least partially overlaps. The reason for this arrangement is that the etching position is located directly under the full exposure region 61 when etching the gate insulating layer 30 and the etching stopper layer 50. Therefore, in order to enable the first via 81 formed by etching to pass to the gate line 22, it must be ensured that the projection of the full exposed region 61 on the gate line 22 at least partially coincides with the gate line 22. . Similarly, in order to ensure that the second via 82 formed under the half-exposure region 62 can pass to the metal oxide semiconductor layer 40, it is necessary to ensure that the half-exposed region 62 is on the metal oxide semiconductor layer 40. The projection at least partially coincides with the metal oxide semiconductor layer 40.

Preferably, in order to ensure good contact between the source drain layer (not shown) and the gate line 22 and the metal oxide semiconductor layer 40, the first via 81 and the gate line should be increased as much as possible. 22 The overlapping area and the overlapping area of the second via 82 and the metal oxide semiconductor layer 40. It is necessary to ensure that the projection of the full exposure region 61 on the gate line 22 is included in the gate line 22, and the projection of the half exposure region 62 on the metal oxide semiconductor layer 40 is included in the metal oxide. Semiconductor layer 40.

Step S4: performing a first etching on the etch stop layer and the gate insulating layer under the full exposed region of the photoresist with the photoresist as a shielding layer to block the etching directly under the full exposed region A first via hole leading to the gate line is formed on the layer and the gate insulating layer.

Referring to FIG. 3 in detail, in particular, an etching process of the gate insulating layer 30 and the etch barrier layer 50 is required in this step. Preferably, a dry etching process can be selected. During the dry etching process, the etch stop layer 50 and the gate insulating layer 30 under the full exposed region 61 are sequentially etched. Below the photoresist 60, except for the region corresponding to the fully exposed region 61, the gate insulating layer 30 and the etch stop layer 50 are protected from being etched by the etching gas due to the presence of the photoresist 60. In the present embodiment, the first via hole 81 leading to the gate line 22 can be formed in the gate insulating layer 30 and the etch barrier layer 50 by controlling the etching rate and etching time of the etching gas. That is, the gate line 22 is partially exposed to the first via 81.

Preferably, the etching gas may be appropriately selected, for example, one or a mixture of any one of SF ₆ , O ₂ , Cl ₂ , He, Ar (argon), or the like is selected.

Step S5: removing the photoresist of the half exposure region.

Please refer to Figure 4 in combination. Specifically, the photoresist 60 may be subjected to ashing treatment so that the photoresist at the half exposure region 62 is removed. It can be understood that the "ashing process" is performed by an oxygen photoresist, thereby thinning the photoresist 60 as a whole, and after the photoresist 60 is thinned as a whole, the photoresist is exposed in the half-exposure region 62. Will be completely removed first. At this time, the etch barrier layer 50 is partially exposed to the half exposed region 62.

Step S6: performing a second etching on the etch stop layer under the photoresist half exposure region with the photoresist as a shielding layer to form a metal oxide to be directly under the half exposure region a second via of the semiconductor layer.

Specifically, the second etching of the etching stopper layer 50 is required in this step. Preferably, a dry etching process can be selected. During the dry etching process of this step, the etch stop layer 50 under the half-exposure region 62 is exposed to the half-exposed region 62 and thus is etched. Located under the photoresist 60 except for the area corresponding to the half-exposure region 62, due to the presence of the photoresist 60, the etch barrier layer 50 free from etching by the etching gas. In the present embodiment, the second via hole 82 leading to the metal oxide semiconductor layer 40 can be formed by etching the barrier layer 50 by controlling the etching rate and etching time of the etching gas. That is, the metal oxide semiconductor layer 40 is partially exposed to the second via 82.

Alternatively, the etching gas in this step may be identical to the etching gas in step S4.

Step S7: removing the photoresist.

Specifically, please refer to Figure 5. The photoresist can be stripped by a wet etching process. The process can use the prior art photoresist stripping method, and details are not described herein again. Alternatively, the photoresist may be removed using the ashing process described above.

Further, after the photoresist is removed, a source and a drain are also formed in the second via, and a metal layer is formed in the first via to connect the signal circuit. The signal circuit can be a circuit on another array substrate or an external signal circuit.

In the method for fabricating an array substrate of the present application, a photoresist is coated on the etching stopper layer, and a half exposure region and a full exposure region are formed on the photoresist through a multi-gray mask, and formed under the entire exposure region. A first via hole leading to the gate line forms a second via hole leading to the metal oxide semiconductor layer under the half exposure region. Therefore, the metal oxide semiconductor layer is not damaged when the first via hole is formed, and the production yield of the array substrate is improved.

The embodiments of the present application have been described in detail above. The principles and implementations of the present application are described in the specific examples. The description of the above embodiments is only used to help understand the method and core ideas of the present application. A person skilled in the art will have a change in the specific embodiments and the scope of the application according to the idea of the present application. In summary, the content of the present specification should not be construed as limiting the present application.

Claims

A method for manufacturing an array substrate, comprising:

Forming a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor layer, and an etch barrier layer on the substrate;

Forming a photoresist on the etch barrier layer;

Providing a multi-gray mask for patterning the photoresist with the multi-gray mask to form a half-exposure region and a full-exposure region on the photoresist, wherein the a projection of the exposed region on the gate line at least partially coincides with the gate line, and a projection of the half-exposed region on the metal oxide semiconductor layer at least partially coincides with the metal oxide semiconductor layer;

Performing a first etching on the etch stop layer and the gate insulating layer under the full exposed region of the photoresist with the photoresist as a shielding layer to form an etch barrier layer and the gate directly under the full exposed region Forming a first via hole to the gate line on the insulating layer;

Removing the photoresist of the half exposed region;

Performing a second etching on the etch stop layer under the photoresist half exposure region with the photoresist as a shielding layer to form a metal oxide semiconductor layer directly under the half exposure region Second via;

The photoresist is removed.
The method of manufacturing an array substrate according to claim 1, further comprising: performing a ashing treatment on the half exposure region of the photoresist to remove the photoresist of the half exposure region.
The method of manufacturing an array substrate according to claim 1, further comprising: dry etching the etching stopper layer and the gate insulating layer to form the first via hole.
The method of fabricating an array substrate according to claim 1, further comprising: dry etching the etch stop layer to form the second via.
The method of manufacturing an array substrate according to claim 3 or 4, wherein the etching gas used in the dry etching is a mixture of one or any of SF 6 , O 2 , Cl 2 , He, Ar .
The method of manufacturing an array substrate according to claim 1, wherein the method further comprises: forming a source and a drain in the second via hole after the step of removing the photoresist is completed, and A metal layer is formed in the first via to connect the signal circuit.
The method of manufacturing an array substrate according to claim 1, wherein the multi-gray mask is a halftone mask or a gray mask.
The method of manufacturing an array substrate according to claim 1, wherein the removing the photoresist comprises: removing the photoresist by an ashing process or a wet etching process.
The method of fabricating an array substrate according to claim 1, wherein a projection of said fully exposed region on said gate line is included in said gate line, and said half exposed region is in said metal oxide A projection on the semiconductor layer is included in the metal oxide semiconductor layer.
The method of fabricating an array substrate according to claim 1, wherein the etching stopper layer is made of silicon oxide, silicon nitride or a mixture of the two.
The method of manufacturing an array substrate according to claim 1, wherein the gate insulating layer is made of silicon oxide, silicon nitride or a mixture of the two.