WO2018094598A1 - Method for manufacturing array substrate - Google Patents
Method for manufacturing array substrate Download PDFInfo
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- WO2018094598A1 WO2018094598A1 PCT/CN2016/106890 CN2016106890W WO2018094598A1 WO 2018094598 A1 WO2018094598 A1 WO 2018094598A1 CN 2016106890 W CN2016106890 W CN 2016106890W WO 2018094598 A1 WO2018094598 A1 WO 2018094598A1
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- photoresist
- layer
- array substrate
- etching
- metal oxide
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 62
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 46
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 39
- 230000004888 barrier function Effects 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 15
- 238000001312 dry etching Methods 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 9
- 238000004380 ashing Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Definitions
- the present application relates to the field of display technologies, and in particular, to a method for fabricating an array substrate.
- the gate insulating layer (GI) and the etch stop layer (ES) are typically processed using the same mask.
- the thickness of the gate insulating layer is much larger than the thickness of the etch barrier layer, the metal oxide semiconductor layer under the etch barrier layer is exposed during the via hole formation by dry etching on the gate insulating layer. Since the etching time of the gate insulating layer is long, damage to the exposed metal oxide semiconductor layer is caused, and therefore it is necessary to increase the thickness of the metal oxide semiconductor layer. Increasing the thickness of the metal oxide semiconductor layer increases the manufacturing cost and reduces the productivity. On the other hand, an excessively thick metal oxide semiconductor layer deteriorates TFT characteristics, eventually resulting in a decrease in product yield.
- the purpose of the present application is to provide a method for fabricating an array substrate, which can avoid damage to a metal oxide semiconductor layer during formation of via holes on a gate insulating layer, and improve production yield of the array substrate.
- the application provides a method for manufacturing an array substrate, comprising:
- a gate electrode and a gate line Forming a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor layer, and an etch barrier layer on the substrate;
- the photoresist is removed.
- the method further comprises: ashing the semi-exposed area of the photoresist to remove the photoresist of the semi-exposed area.
- the method further comprises: performing dry etching on the etch barrier layer and the gate insulating layer to form the first via.
- the method further comprises: performing dry etching on the etching barrier layer to form the second via hole.
- the etching gas used in the dry etching is a mixture of one or any of SF6, O2, Cl2, He, Ar.
- the method further comprises: after the step of removing the photoresist is completed, forming a source and a drain in the second via, and forming a metal layer in the first via to connect the signal circuit.
- the multi-gray mask is a halftone mask or a gray mask.
- the step of removing the photoresist comprises: removing the photoresist by an ashing process or a wet etching process.
- the projection of the full exposure region on the gate line is included in the gate line, and a projection of the half exposure region on the metal oxide semiconductor layer is included in the metal oxide semiconductor layer.
- the etching barrier layer is made of silicon oxide, silicon nitride or a mixture of the two.
- the gate insulating layer is made of silicon oxide, silicon nitride or a mixture of the two.
- a photoresist is coated on the etching stopper layer, and a half exposure region and a full exposure region are formed on the photoresist through a multi-gray mask, and formed under the entire exposure region.
- a first via hole leading to the gate line forms a second via hole leading to the metal oxide semiconductor layer under the half exposure region. Therefore, the metal oxide semiconductor layer is not damaged when the first via hole is formed, and the damage is improved.
- the production yield of the array substrate is possible.
- 1 is a flow chart of a method for manufacturing an array substrate of the present application.
- FIG. 2 to 5 are schematic flow charts showing a method of manufacturing the array substrate shown in FIG. 1.
- FIG. 1 is a flow chart of a method for fabricating an array substrate of the present application.
- a method for manufacturing an array substrate includes the following steps:
- Step S1 sequentially forming a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor layer, and an etch barrier layer on the substrate.
- the pattern of the gate electrode 21 and the gate line 22 may be formed on the substrate 10 by one patterning process.
- the gate electrode 21 and the gate line 22 are made of the same material, for example, a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal can also meet the needs. .
- a gate insulating layer 30 is deposited by the PECVD (Plasma Enhanced Chemical Vapor Deposition) method over the gate electrode 21 and the gate line 22.
- the gate insulating layer 30 covers the gate electrode 21 and the gate line 22.
- the gate insulating layer 30 may be selected from materials including, but not limited to, silicon oxide, silicon nitride, or a mixture of the two.
- the metal oxide semiconductor layer 40 can also be deposited on the gate insulating layer 30 by sputtering or thermal evaporation.
- the metal oxide semiconductor layer 40 can be IGZO (indium gallium zinc oxide), HIZO. , IZO, a-InZnO, a-InZnO, ZnO: F, In2O3: Sn, In2O3: Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxide.
- IGZO indium gallium zinc oxide
- HIZO. IZO
- a-InZnO a-InZnO
- ZnO F
- In2O3 Sn
- In2O3 Mo
- Cd2SnO4 ZnO
- Al TiO2: Nb, Cd-Sn-O or other metal oxide.
- TiO2 Nb, Cd-Sn-O or other metal oxide.
- it can be made of IG
- the etch stop layer 50 may be silicon oxide, silicon nitride, or a mixture of the two.
- the gate insulating layer 30 is deposited by chemical vapor deposition, and the etch barrier layer 50 completely covers the metal oxide semiconductor layer 40.
- the metal oxide semiconductor layer 40 functions to protect the underlying structure under the etching barrier layer 50 from the end of the wet etching of the source and drain layers when the source and drain layers (not shown) are wet etched. Etched.
- Step S2 forming a photoresist on the etch barrier layer.
- Step S3 providing a multi-gray mask, using the multi-gray mask to pattern the photoresist to form a half-exposure region and a full-exposure region on the photoresist, wherein a projection of the fully exposed region on the gate line at least partially coincides with the gate line, a projection of the half-exposed region on the metal oxide semiconductor layer and at least a portion of the metal oxide semiconductor layer coincide.
- the multi-gray mask 70 may be a half tone mask or a gray tone mask.
- the multi-gray mask 70 is overlaid over the photoresist 60.
- the photoresist 60 is exposed, developed (i.e., photolithographically) to complete patterning.
- a full exposure region 61 and a half exposure region 62 are formed. Wherein the projection of the full exposure region 61 on the gate line 22 at least partially coincides with the gate line 22, the projection of the half exposure region 62 on the metal oxide semiconductor layer 40 and the The metal oxide semiconductor layer 40 at least partially overlaps.
- the etching position is located directly under the full exposure region 61 when etching the gate insulating layer 30 and the etching stopper layer 50. Therefore, in order to enable the first via 81 formed by etching to pass to the gate line 22, it must be ensured that the projection of the full exposed region 61 on the gate line 22 at least partially coincides with the gate line 22. . Similarly, in order to ensure that the second via 82 formed under the half-exposure region 62 can pass to the metal oxide semiconductor layer 40, it is necessary to ensure that the half-exposed region 62 is on the metal oxide semiconductor layer 40. The projection at least partially coincides with the metal oxide semiconductor layer 40.
- the first via 81 and the gate line should be increased as much as possible. 22
- the overlapping area and the overlapping area of the second via 82 and the metal oxide semiconductor layer 40 It is necessary to ensure that the projection of the full exposure region 61 on the gate line 22 is included in the gate line 22, and the projection of the half exposure region 62 on the metal oxide semiconductor layer 40 is included in the metal oxide. Semiconductor layer 40.
- Step S4 performing a first etching on the etch stop layer and the gate insulating layer under the full exposed region of the photoresist with the photoresist as a shielding layer to block the etching directly under the full exposed region A first via hole leading to the gate line is formed on the layer and the gate insulating layer.
- an etching process of the gate insulating layer 30 and the etch barrier layer 50 is required in this step.
- a dry etching process can be selected.
- the etch stop layer 50 and the gate insulating layer 30 under the full exposed region 61 are sequentially etched.
- the gate insulating layer 30 and the etch stop layer 50 are protected from being etched by the etching gas due to the presence of the photoresist 60.
- the first via hole 81 leading to the gate line 22 can be formed in the gate insulating layer 30 and the etch barrier layer 50 by controlling the etching rate and etching time of the etching gas. That is, the gate line 22 is partially exposed to the first via 81.
- the etching gas may be appropriately selected, for example, one or a mixture of any one of SF 6 , O 2 , Cl 2 , He, Ar (argon), or the like is selected.
- Step S5 removing the photoresist of the half exposure region.
- the photoresist 60 may be subjected to ashing treatment so that the photoresist at the half exposure region 62 is removed.
- ashing process is performed by an oxygen photoresist, thereby thinning the photoresist 60 as a whole, and after the photoresist 60 is thinned as a whole, the photoresist is exposed in the half-exposure region 62. Will be completely removed first. At this time, the etch barrier layer 50 is partially exposed to the half exposed region 62.
- Step S6 performing a second etching on the etch stop layer under the photoresist half exposure region with the photoresist as a shielding layer to form a metal oxide to be directly under the half exposure region a second via of the semiconductor layer.
- the second etching of the etching stopper layer 50 is required in this step.
- a dry etching process can be selected.
- the etch stop layer 50 under the half-exposure region 62 is exposed to the half-exposed region 62 and thus is etched.
- the etch barrier layer 50 free from etching by the etching gas.
- the second via hole 82 leading to the metal oxide semiconductor layer 40 can be formed by etching the barrier layer 50 by controlling the etching rate and etching time of the etching gas. That is, the metal oxide semiconductor layer 40 is partially exposed to the second via 82.
- the etching gas in this step may be identical to the etching gas in step S4.
- Step S7 removing the photoresist.
- the photoresist can be stripped by a wet etching process.
- the process can use the prior art photoresist stripping method, and details are not described herein again.
- the photoresist may be removed using the ashing process described above.
- the signal circuit can be a circuit on another array substrate or an external signal circuit.
- a photoresist is coated on the etching stopper layer, and a half exposure region and a full exposure region are formed on the photoresist through a multi-gray mask, and formed under the entire exposure region.
- a first via hole leading to the gate line forms a second via hole leading to the metal oxide semiconductor layer under the half exposure region. Therefore, the metal oxide semiconductor layer is not damaged when the first via hole is formed, and the production yield of the array substrate is improved.
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Abstract
A method for manufacturing an array substrate, comprising: forming a gate electrode, a gate line, a gate insulating layer, a metal-oxide semiconductor layer, and an etch stopping layer on a substrate (S1); forming a photoresist on the etch stopping layer (S2); providing a multi-greyscale mask plate to form a semi-exposure region and a full-exposure region on the photoresist (S3); performing first etching on the etch stopping layer and the gate insulating layer to form a first via hole, leading to the gate line, on the etch stopping layer and the gate insulating layer (S4); removing the photoresist of the semi-exposure region (S5); performing second etching on the etch stopping layer to form a second via hole, leading to the metal-oxide semiconductor layer, below the semi-exposure region (S6); and removing the photoresist (S7). The manufacturing method would not damage the metal-oxide semiconductor layer when the first via hole is formed, thereby improving the yield rate of array substrates.
Description
本申请涉及显示技术领域,尤其涉及一种阵列基板的制造方法。The present application relates to the field of display technologies, and in particular, to a method for fabricating an array substrate.
现有技术中,为了降低阵列基板的制造成本。栅绝缘层(GI)和蚀刻阻挡层(ES)通常采用同一道掩膜版(mask)进行加工。但是,由于栅绝缘层的厚度远大于蚀刻阻挡层的厚度,栅绝缘层上通过干法蚀刻形成过孔过程中,会将蚀刻阻挡层下方的金属氧化物半导体层暴露出来。由于栅绝缘层的蚀刻时间较长,会对已经暴露出来的金属氧化物半导体层造成损伤,因此需要增加金属氧化物半导体层的厚度。而增加金属氧化物半导体层的厚度一方面会增加制造成本,使产能降低。另一方面,过厚的金属氧化物半导体层会使TFT特性变差,最终导致产品良率降低。In the prior art, in order to reduce the manufacturing cost of the array substrate. The gate insulating layer (GI) and the etch stop layer (ES) are typically processed using the same mask. However, since the thickness of the gate insulating layer is much larger than the thickness of the etch barrier layer, the metal oxide semiconductor layer under the etch barrier layer is exposed during the via hole formation by dry etching on the gate insulating layer. Since the etching time of the gate insulating layer is long, damage to the exposed metal oxide semiconductor layer is caused, and therefore it is necessary to increase the thickness of the metal oxide semiconductor layer. Increasing the thickness of the metal oxide semiconductor layer increases the manufacturing cost and reduces the productivity. On the other hand, an excessively thick metal oxide semiconductor layer deteriorates TFT characteristics, eventually resulting in a decrease in product yield.
此外,当金属氧化物半导体层被蚀刻穿透时,还会造成栅电极层和源漏极层短路的风险。In addition, when the metal oxide semiconductor layer is etched through, there is also a risk of short-circuiting the gate electrode layer and the source and drain layers.
申请内容Application content
本申请的目的在于提供一种阵列基板的制造方法,该方法可以避免在栅绝缘层上形成过孔过程中对金属氧化物半导体层造成的损伤,提高阵列基板的生产良率。The purpose of the present application is to provide a method for fabricating an array substrate, which can avoid damage to a metal oxide semiconductor layer during formation of via holes on a gate insulating layer, and improve production yield of the array substrate.
为实现上述目的,本申请提供如下技术方案:To achieve the above objective, the present application provides the following technical solutions:
本申请提供一种阵列基板的制造方法,包括:The application provides a method for manufacturing an array substrate, comprising:
在基板上形成栅电极和栅极线、栅绝缘层、金属氧化物半导体层和蚀刻阻挡层;Forming a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor layer, and an etch barrier layer on the substrate;
在所述蚀刻阻挡层上形成光刻胶;Forming a photoresist on the etch barrier layer;
提供一多灰阶掩膜版,利用所述多灰阶掩膜版对所述光刻胶进行图案化,以在所述光刻胶上形成半曝光区域和全曝光区域,其中,所述全曝光区域在所述栅极线上的投影与所述栅极线至少部分重合,所述半曝光区域在所述金属氧化物半导体层上的投影与所述金属氧化物半导体层至少部分重合;
Providing a multi-gray mask for patterning the photoresist with the multi-gray mask to form a half-exposure region and a full-exposure region on the photoresist, wherein the a projection of the exposed region on the gate line at least partially coincides with the gate line, and a projection of the half-exposed region on the metal oxide semiconductor layer at least partially coincides with the metal oxide semiconductor layer;
以所述光刻胶为遮蔽层,对所述光刻胶全曝光区域下方的所述蚀刻阻挡层和所述栅绝缘层进行第一蚀刻,以在所述全曝光区域正下方的蚀刻阻挡层和所述栅绝缘层上形成通向所述栅极线的第一过孔;Using the photoresist as a shielding layer, performing first etching on the etch barrier layer and the gate insulating layer under the entire exposed region of the photoresist to form an etch barrier directly under the full exposure region And forming a first via hole to the gate line on the gate insulating layer;
将所述半曝光区域的光刻胶去除;Removing the photoresist of the half exposed region;
以所述光刻胶为遮蔽层,对所述蚀刻阻挡层进行第二蚀刻,以在所述光刻胶半曝光区域正下方形成通向所述金属氧化物半导体层的第二过孔;Performing a second etching on the etch barrier layer by using the photoresist as a shielding layer to form a second via hole to the metal oxide semiconductor layer directly under the photoresist half exposure region;
去除所述光刻胶。The photoresist is removed.
其中,所述方法还包括:对所述光刻胶的半曝光区域进行灰化处理,以去除所述半曝光区域的光刻胶。Wherein, the method further comprises: ashing the semi-exposed area of the photoresist to remove the photoresist of the semi-exposed area.
其中,所述方法还包括:对所述蚀刻阻挡层和所述栅绝缘层进行干法蚀刻,以形成所述第一过孔。Wherein, the method further comprises: performing dry etching on the etch barrier layer and the gate insulating layer to form the first via.
其中,所述方法还包括:对所述蚀刻阻挡层进行干法蚀刻,以形成所述第二过孔。Wherein, the method further comprises: performing dry etching on the etching barrier layer to form the second via hole.
其中,所述干法蚀刻采用的蚀刻气体为SF6、O2、Cl2、He、Ar中一种或任意几种的混合。The etching gas used in the dry etching is a mixture of one or any of SF6, O2, Cl2, He, Ar.
其中,所述方法还包括:在去除所述光刻胶步骤完成后,在所述第二过孔中形成源极和漏极,以及在第一过孔中形成金属层以连接信号电路。Wherein, the method further comprises: after the step of removing the photoresist is completed, forming a source and a drain in the second via, and forming a metal layer in the first via to connect the signal circuit.
其中,所述多灰阶掩膜版为半色调掩膜版或灰色调掩膜版。Wherein, the multi-gray mask is a halftone mask or a gray mask.
其中,所述去除所述光刻胶步骤中包括:采用灰化工艺或湿法蚀刻工艺将所述光刻胶去除。Wherein the step of removing the photoresist comprises: removing the photoresist by an ashing process or a wet etching process.
其中,所述全曝光区域在所述栅极线上的投影包含于所述栅极线,所述半曝光区域在所述金属氧化物半导体层上的投影包含于所述金属氧化物半导体层。The projection of the full exposure region on the gate line is included in the gate line, and a projection of the half exposure region on the metal oxide semiconductor layer is included in the metal oxide semiconductor layer.
其中,所述蚀刻阻挡层采用氧化硅、氮化硅或者二者的混合物。Wherein, the etching barrier layer is made of silicon oxide, silicon nitride or a mixture of the two.
其中,所述栅绝缘层采用氧化硅、氮化硅或者二者的混合物。Wherein, the gate insulating layer is made of silicon oxide, silicon nitride or a mixture of the two.
本申请实施例具有如下优点或有益效果:The embodiments of the present application have the following advantages or benefits:
本申请的阵列基板的制造方法中,在蚀刻阻挡层上涂覆光刻胶,通过多灰阶掩膜版在所述光刻胶上形成半曝光区域和全曝光区域,在全曝光区域下方形成通向栅极线的第一过孔,在半曝光区域下方形成通向金属氧化物半导体层的第二通孔。从而在形成第一过孔时不会对金属氧化物半导体层造成损伤,提高
了阵列基板的生产良率。In the method for fabricating an array substrate of the present application, a photoresist is coated on the etching stopper layer, and a half exposure region and a full exposure region are formed on the photoresist through a multi-gray mask, and formed under the entire exposure region. A first via hole leading to the gate line forms a second via hole leading to the metal oxide semiconductor layer under the half exposure region. Therefore, the metal oxide semiconductor layer is not damaged when the first via hole is formed, and the damage is improved.
The production yield of the array substrate.
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings to be used in the embodiments will be briefly described below. Obviously, the drawings in the following description are only some of the present application. For the embodiments, those skilled in the art can obtain other drawings according to the drawings without any creative work.
图1为本申请阵列基板的制造方法流程框图。1 is a flow chart of a method for manufacturing an array substrate of the present application.
图2-图5是图1所示阵列基板的制造方法流程示意图。2 to 5 are schematic flow charts showing a method of manufacturing the array substrate shown in FIG. 1.
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.
本申请以下实施例中所采用的序数限定词,第一、第二等仅是为了清楚地说明本申请中相似的特征的区别性的用语,不代表相应的特征的排列顺序或者使用顺序。The ordinal qualifiers used in the following embodiments of the present application, the first, second, etc. are merely for the purpose of clearly indicating the distinctive features of the similar features in the present application, and do not represent the order of the corresponding features or the order of use.
请参阅图1,图1为本申请阵列基板的制造方法的流程框图。本申请的一种实施方式中,阵列基板的制造方法包括如下步骤:Please refer to FIG. 1. FIG. 1 is a flow chart of a method for fabricating an array substrate of the present application. In an embodiment of the present application, a method for manufacturing an array substrate includes the following steps:
步骤S1:在基板上依次形成栅电极和栅极线、栅绝缘层、金属氧化物半导体层和蚀刻阻挡层。Step S1: sequentially forming a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor layer, and an etch barrier layer on the substrate.
具体的,请结合参阅图2,可以通过一次构图工艺在所述基板10上形成所述栅电极21和所述栅极线22的图案。所述栅电极21和所述栅极线22采用相同材料制成,例如可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金,由多层金属组成的栅金属层也能满足需要。Specifically, referring to FIG. 2, the pattern of the gate electrode 21 and the gate line 22 may be formed on the substrate 10 by one patterning process. The gate electrode 21 and the gate line 22 are made of the same material, for example, a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal can also meet the needs. .
然后,在所述栅电极21和所述栅极线22之上通过PECVD(等离子体增强化学气相沉积法)方法沉积栅绝缘层30。所述栅绝缘层30覆盖所述栅电极21和所述栅极线22。栅绝缘层30可以选用包括但不限于氧化硅、氮化硅或二者的混合物等材料。
Then, a gate insulating layer 30 is deposited by the PECVD (Plasma Enhanced Chemical Vapor Deposition) method over the gate electrode 21 and the gate line 22. The gate insulating layer 30 covers the gate electrode 21 and the gate line 22. The gate insulating layer 30 may be selected from materials including, but not limited to, silicon oxide, silicon nitride, or a mixture of the two.
所述金属氧化物半导体层40同样可以通过溅射或热蒸发的方法沉积在栅绝缘层30上,金属氧化物半导体层40可以是采用IGZO(indium gallium zinc oxide,铟镓锌氧化物)、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或其他金属氧化物制成。优选的,可以选用IGZO材料制成。The metal oxide semiconductor layer 40 can also be deposited on the gate insulating layer 30 by sputtering or thermal evaporation. The metal oxide semiconductor layer 40 can be IGZO (indium gallium zinc oxide), HIZO. , IZO, a-InZnO, a-InZnO, ZnO: F, In2O3: Sn, In2O3: Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxide. Preferably, it can be made of IGZO material.
蚀刻阻挡层50可以采用氧化硅、氮化硅或者二者的混合物。通过化学气相沉积法沉积在所述栅绝缘层30上,蚀刻阻挡层50完全覆盖所述金属氧化物半导体层40。所述金属氧化物半导体层40的作用于:在源漏极层(图未示出)进行湿法蚀刻时,作为源漏极层湿法蚀刻的终点,保护蚀刻阻挡层50下方的层叠结构不受蚀刻。The etch stop layer 50 may be silicon oxide, silicon nitride, or a mixture of the two. The gate insulating layer 30 is deposited by chemical vapor deposition, and the etch barrier layer 50 completely covers the metal oxide semiconductor layer 40. The metal oxide semiconductor layer 40 functions to protect the underlying structure under the etching barrier layer 50 from the end of the wet etching of the source and drain layers when the source and drain layers (not shown) are wet etched. Etched.
步骤S2:在所述蚀刻阻挡层上形成光刻胶。Step S2: forming a photoresist on the etch barrier layer.
步骤S3:提供一多灰阶掩膜版,利用所述多灰阶掩膜版对所述光刻胶进行图案化,以在所述光刻胶上形成半曝光区域和全曝光区域,其中,所述全曝光区域在所述栅极线上的投影与所述栅极线至少部分重合,所述半曝光区域在所述金属氧化物半导体层上的投影与所述金属氧化物半导体层至少部分重合。Step S3: providing a multi-gray mask, using the multi-gray mask to pattern the photoresist to form a half-exposure region and a full-exposure region on the photoresist, wherein a projection of the fully exposed region on the gate line at least partially coincides with the gate line, a projection of the half-exposed region on the metal oxide semiconductor layer and at least a portion of the metal oxide semiconductor layer coincide.
可选的,所述多灰阶掩膜版70可以为半色调掩膜版(Half tone mask)或灰色调掩膜版(Gray tone mask)。将所述多灰阶掩膜版70遮盖在所述光刻胶60上方。对所述光刻胶60进行曝光、显影(即光刻)以完成图案化。所述光刻胶60经过光刻工艺后,形成全曝光区域61和半曝光区域62。其中,所述全曝光区域61在所述栅极线22上的投影与所述栅极线22至少部分重合,所述半曝光区域62在所述金属氧化物半导体层40上的投影与所述金属氧化物半导体层40至少部分重合。这样设置的原因在于:在对栅绝缘层30和蚀刻阻挡层50进行蚀刻时,蚀刻的位置位于所述全曝光区域61的正下方。因此,为了使得蚀刻形成的第一过孔81能够通向所述栅极线22,必须保证所述全曝光区域61在所述栅极线22上的投影与所述栅极线22至少部分重合。同理,为了保证形成于半曝光区域62下方的第二过孔82能够通向所述金属氧化物半导体层40,就必须保证所述半曝光区域62在所述金属氧化物半导体层40上的投影与所述金属氧化物半导体层40至少部分重合。Optionally, the multi-gray mask 70 may be a half tone mask or a gray tone mask. The multi-gray mask 70 is overlaid over the photoresist 60. The photoresist 60 is exposed, developed (i.e., photolithographically) to complete patterning. After the photoresist 60 is subjected to a photolithography process, a full exposure region 61 and a half exposure region 62 are formed. Wherein the projection of the full exposure region 61 on the gate line 22 at least partially coincides with the gate line 22, the projection of the half exposure region 62 on the metal oxide semiconductor layer 40 and the The metal oxide semiconductor layer 40 at least partially overlaps. The reason for this arrangement is that the etching position is located directly under the full exposure region 61 when etching the gate insulating layer 30 and the etching stopper layer 50. Therefore, in order to enable the first via 81 formed by etching to pass to the gate line 22, it must be ensured that the projection of the full exposed region 61 on the gate line 22 at least partially coincides with the gate line 22. . Similarly, in order to ensure that the second via 82 formed under the half-exposure region 62 can pass to the metal oxide semiconductor layer 40, it is necessary to ensure that the half-exposed region 62 is on the metal oxide semiconductor layer 40. The projection at least partially coincides with the metal oxide semiconductor layer 40.
优选的,为了保证源漏极层(图未示出)与所述栅极线22及所述金属氧化物半导体层40的良好接触,应当尽量增大第一过孔81与所述栅极线22的
重合面积、及所述第二过孔82与所述金属氧化物半导体层40的重合面积。则需要保证全曝光区域61在所述栅极线22上的投影包含于所述栅极线22,所述半曝光区域62在所述金属氧化物半导体层40上的投影包含于所述金属氧化物半导体层40。Preferably, in order to ensure good contact between the source drain layer (not shown) and the gate line 22 and the metal oxide semiconductor layer 40, the first via 81 and the gate line should be increased as much as possible. 22
The overlapping area and the overlapping area of the second via 82 and the metal oxide semiconductor layer 40. It is necessary to ensure that the projection of the full exposure region 61 on the gate line 22 is included in the gate line 22, and the projection of the half exposure region 62 on the metal oxide semiconductor layer 40 is included in the metal oxide. Semiconductor layer 40.
步骤S4:以所述光刻胶为遮蔽层,对所述光刻胶全曝光区域下方的蚀刻阻挡层和所述栅绝缘层进行第一蚀刻,以在所述全曝光区域正下方的蚀刻阻挡层和所述栅绝缘层上形成通向所述栅极线的第一过孔。Step S4: performing a first etching on the etch stop layer and the gate insulating layer under the full exposed region of the photoresist with the photoresist as a shielding layer to block the etching directly under the full exposed region A first via hole leading to the gate line is formed on the layer and the gate insulating layer.
请结合参阅图3,具体的,在该步骤中需要对栅绝缘层30和蚀刻阻挡层50进行蚀刻工艺。优选的,可以选用干法蚀刻工艺。在干法蚀刻过程中,位于全曝光区域61下方的蚀刻阻挡层50和栅绝缘层30会被依次蚀刻。位于光刻胶60下方除与全曝光区域61对应以外区域,由于有光刻胶60的存在,栅绝缘层30和蚀刻阻挡层50免于被蚀刻气体蚀刻。本实施方式中通过控制蚀刻气体的蚀刻速率和蚀刻时间,可以在栅绝缘层30和蚀刻阻挡层50形成通向所述栅极线22的第一过孔81。也就是说,所述栅极线22部分露出于所述第一过孔81。Referring to FIG. 3 in detail, in particular, an etching process of the gate insulating layer 30 and the etch barrier layer 50 is required in this step. Preferably, a dry etching process can be selected. During the dry etching process, the etch stop layer 50 and the gate insulating layer 30 under the full exposed region 61 are sequentially etched. Below the photoresist 60, except for the region corresponding to the fully exposed region 61, the gate insulating layer 30 and the etch stop layer 50 are protected from being etched by the etching gas due to the presence of the photoresist 60. In the present embodiment, the first via hole 81 leading to the gate line 22 can be formed in the gate insulating layer 30 and the etch barrier layer 50 by controlling the etching rate and etching time of the etching gas. That is, the gate line 22 is partially exposed to the first via 81.
优选的,所述蚀刻气体可以适当的选用,例如选择SF6、O2、Cl2、He、Ar(氩气)中一种或任意几种的混合等。Preferably, the etching gas may be appropriately selected, for example, one or a mixture of any one of SF 6 , O 2 , Cl 2 , He, Ar (argon), or the like is selected.
步骤S5:将所述半曝光区域的光刻胶去除。Step S5: removing the photoresist of the half exposure region.
请结合参阅图4。具体的,可以对所述光刻胶60进行灰化处理,使得所述半曝光区域62处的光刻胶被去除。可以理解的是,所述“灰化处理”即通过氧气光刻胶反应,从而将所述光刻胶60整体打薄,光刻胶60整体打薄后,半曝光区域62出的光刻胶会首先被完全去除。此时,所述蚀刻阻挡层50部分暴露于所述半曝光区域62。Please refer to Figure 4 in combination. Specifically, the photoresist 60 may be subjected to ashing treatment so that the photoresist at the half exposure region 62 is removed. It can be understood that the "ashing process" is performed by an oxygen photoresist, thereby thinning the photoresist 60 as a whole, and after the photoresist 60 is thinned as a whole, the photoresist is exposed in the half-exposure region 62. Will be completely removed first. At this time, the etch barrier layer 50 is partially exposed to the half exposed region 62.
步骤S6:以所述光刻胶为遮蔽层,对所述光刻胶半曝光区域下方的所述蚀刻阻挡层进行第二蚀刻,以在所述半曝光区域正下方形成通向所述金属氧化物半导体层的第二过孔。Step S6: performing a second etching on the etch stop layer under the photoresist half exposure region with the photoresist as a shielding layer to form a metal oxide to be directly under the half exposure region a second via of the semiconductor layer.
具体的,在该步骤中需要对蚀刻阻挡层50进行第二蚀刻。优选的,可以选用干法蚀刻工艺。在本步骤的干法蚀刻过程中,位于半曝光区域62下方的蚀刻阻挡层50外露于所述半曝光区域62,因此会被蚀刻。位于光刻胶60下方除与半曝光区域62对应以外区域,由于有光刻胶60的存在,蚀刻阻挡层
50免于被蚀刻气体蚀刻。本实施方式中通过控制蚀刻气体的蚀刻速率和蚀刻时间,可以蚀刻阻挡层50形成通向所述金属氧化物半导体层40的第二过孔82。也就是说,所述金属氧化物半导体层40部分露出于所述第二过孔82。Specifically, the second etching of the etching stopper layer 50 is required in this step. Preferably, a dry etching process can be selected. During the dry etching process of this step, the etch stop layer 50 under the half-exposure region 62 is exposed to the half-exposed region 62 and thus is etched. Located under the photoresist 60 except for the area corresponding to the half-exposure region 62, due to the presence of the photoresist 60, the etch barrier layer
50 free from etching by the etching gas. In the present embodiment, the second via hole 82 leading to the metal oxide semiconductor layer 40 can be formed by etching the barrier layer 50 by controlling the etching rate and etching time of the etching gas. That is, the metal oxide semiconductor layer 40 is partially exposed to the second via 82.
可选的,本步骤中的蚀刻气体可以与步骤S4中的蚀刻气体一致。Alternatively, the etching gas in this step may be identical to the etching gas in step S4.
步骤S7:去除所述光刻胶。Step S7: removing the photoresist.
具体的,请参阅图5。可以通过湿法蚀刻工艺剥离所述光刻胶。该过程可以采用现有技术的光刻胶剥离方法,在此不再赘述。或者,还可以采用上述的灰化工艺去除所述光刻胶。Specifically, please refer to Figure 5. The photoresist can be stripped by a wet etching process. The process can use the prior art photoresist stripping method, and details are not described herein again. Alternatively, the photoresist may be removed using the ashing process described above.
进一步的,在所述光刻胶被去除后,还需要在所述第二过孔中形成源极和漏极,以及在第一过孔中形成金属层以连接信号电路。该信号电路可以为另一阵列基板上的电路,也可以为外部的信号电路。Further, after the photoresist is removed, a source and a drain are also formed in the second via, and a metal layer is formed in the first via to connect the signal circuit. The signal circuit can be a circuit on another array substrate or an external signal circuit.
本申请的阵列基板的制造方法中,在蚀刻阻挡层上涂覆光刻胶,通过多灰阶掩膜版在所述光刻胶上形成半曝光区域和全曝光区域,在全曝光区域下方形成通向栅极线的第一过孔,在半曝光区域下方形成通向金属氧化物半导体层的第二通孔。从而在形成第一过孔时不会对金属氧化物半导体层造成损伤,提高了阵列基板的生产良率。In the method for fabricating an array substrate of the present application, a photoresist is coated on the etching stopper layer, and a half exposure region and a full exposure region are formed on the photoresist through a multi-gray mask, and formed under the entire exposure region. A first via hole leading to the gate line forms a second via hole leading to the metal oxide semiconductor layer under the half exposure region. Therefore, the metal oxide semiconductor layer is not damaged when the first via hole is formed, and the production yield of the array substrate is improved.
以上对本申请实施例进行了详细介绍,本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的方法及其核心思想;同时,对于本领域的一般技术人员,依据本申请的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本申请的限制。
The embodiments of the present application have been described in detail above. The principles and implementations of the present application are described in the specific examples. The description of the above embodiments is only used to help understand the method and core ideas of the present application. A person skilled in the art will have a change in the specific embodiments and the scope of the application according to the idea of the present application. In summary, the content of the present specification should not be construed as limiting the present application.
Claims (11)
- 一种阵列基板的制造方法,其特征在于,包括:A method for manufacturing an array substrate, comprising:在基板上形成栅电极和栅极线、栅绝缘层、金属氧化物半导体层和蚀刻阻挡层;Forming a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor layer, and an etch barrier layer on the substrate;在所述蚀刻阻挡层上形成光刻胶;Forming a photoresist on the etch barrier layer;提供一多灰阶掩膜版,利用所述多灰阶掩膜版对所述光刻胶进行图案化,以在所述光刻胶上形成半曝光区域和全曝光区域,其中,所述全曝光区域在所述栅极线上的投影与所述栅极线至少部分重合,所述半曝光区域在所述金属氧化物半导体层上的投影与所述金属氧化物半导体层至少部分重合;Providing a multi-gray mask for patterning the photoresist with the multi-gray mask to form a half-exposure region and a full-exposure region on the photoresist, wherein the a projection of the exposed region on the gate line at least partially coincides with the gate line, and a projection of the half-exposed region on the metal oxide semiconductor layer at least partially coincides with the metal oxide semiconductor layer;以所述光刻胶为遮蔽层,对所述光刻胶全曝光区域下方的蚀刻阻挡层和栅绝缘层进行第一蚀刻,以在所述全曝光区域正下方的蚀刻阻挡层和所述栅绝缘层上形成通向所述栅极线的第一过孔;Performing a first etching on the etch stop layer and the gate insulating layer under the full exposed region of the photoresist with the photoresist as a shielding layer to form an etch barrier layer and the gate directly under the full exposed region Forming a first via hole to the gate line on the insulating layer;将所述半曝光区域的光刻胶去除;Removing the photoresist of the half exposed region;以所述光刻胶为遮蔽层,对所述光刻胶半曝光区域下方的所述蚀刻阻挡层进行第二蚀刻,以在所述半曝光区域正下方形成通向所述金属氧化物半导体层的第二过孔;Performing a second etching on the etch stop layer under the photoresist half exposure region with the photoresist as a shielding layer to form a metal oxide semiconductor layer directly under the half exposure region Second via;去除所述光刻胶。The photoresist is removed.
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述方法还包括:对所述光刻胶的半曝光区域进行灰化处理,以去除所述半曝光区域的光刻胶。The method of manufacturing an array substrate according to claim 1, further comprising: performing a ashing treatment on the half exposure region of the photoresist to remove the photoresist of the half exposure region.
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述方法还包括:对所述蚀刻阻挡层和所述栅绝缘层进行干法蚀刻,以形成所述第一过孔。The method of manufacturing an array substrate according to claim 1, further comprising: dry etching the etching stopper layer and the gate insulating layer to form the first via hole.
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述方法还包括:对所述蚀刻阻挡层进行干法蚀刻,以形成所述第二过孔。The method of fabricating an array substrate according to claim 1, further comprising: dry etching the etch stop layer to form the second via.
- 如权利要求3或4所述的阵列基板的制造方法,其特征在于,所述干法蚀刻采用的蚀刻气体为SF6、O2、Cl2、He、Ar中一种或任意几种的混合。The method of manufacturing an array substrate according to claim 3 or 4, wherein the etching gas used in the dry etching is a mixture of one or any of SF 6 , O 2 , Cl 2 , He, Ar .
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述方法还包括:在去除所述光刻胶步骤完成后,在所述第二过孔中形成源极和漏极,以及在第一过孔中形成金属层以连接信号电路。 The method of manufacturing an array substrate according to claim 1, wherein the method further comprises: forming a source and a drain in the second via hole after the step of removing the photoresist is completed, and A metal layer is formed in the first via to connect the signal circuit.
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述多灰阶掩膜版为半色调掩膜版或灰色调掩膜版。The method of manufacturing an array substrate according to claim 1, wherein the multi-gray mask is a halftone mask or a gray mask.
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述去除所述光刻胶步骤中包括:采用灰化工艺或湿法蚀刻工艺将所述光刻胶去除。The method of manufacturing an array substrate according to claim 1, wherein the removing the photoresist comprises: removing the photoresist by an ashing process or a wet etching process.
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述全曝光区域在所述栅极线上的投影包含于所述栅极线,所述半曝光区域在所述金属氧化物半导体层上的投影包含于所述金属氧化物半导体层。The method of fabricating an array substrate according to claim 1, wherein a projection of said fully exposed region on said gate line is included in said gate line, and said half exposed region is in said metal oxide A projection on the semiconductor layer is included in the metal oxide semiconductor layer.
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述蚀刻阻挡层采用氧化硅、氮化硅或者二者的混合物。The method of fabricating an array substrate according to claim 1, wherein the etching stopper layer is made of silicon oxide, silicon nitride or a mixture of the two.
- 如权利要求1所述的阵列基板的制造方法,其特征在于,所述栅绝缘层采用氧化硅、氮化硅或者二者的混合物。 The method of manufacturing an array substrate according to claim 1, wherein the gate insulating layer is made of silicon oxide, silicon nitride or a mixture of the two.
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