CN109166868B - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
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- CN109166868B CN109166868B CN201811019726.4A CN201811019726A CN109166868B CN 109166868 B CN109166868 B CN 109166868B CN 201811019726 A CN201811019726 A CN 201811019726A CN 109166868 B CN109166868 B CN 109166868B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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Abstract
The invention provides an array substrate, a preparation method thereof and a display panel, wherein the method comprises the following steps: preparing a layer of photoresist on a substrate with a grid electrode, a grid insulating layer, a source drain electrode and a passivation layer; exposing the photoresist to form a photoresist completely removed area and a photoresist partially reserved area which are spaced, wherein the photoresist partially reserved area corresponds to an area for forming a first via hole, and the photoresist completely removed area corresponds to an area for forming a second via hole; and etching the passivation layer and the gate insulating layer in an alternative manner of wet etching and dry etching in sequence to form a first via hole corresponding to the source and drain electrode and a second via hole corresponding to the gate electrode respectively, wherein the depth of the first via hole is smaller than that of the second via hole.
Description
Technical Field
The invention relates to the technical field of display panel manufacturing, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
In the design of a TFT-LCD panel, a grid electrode insulating layer, an active layer, a source electrode, a drain electrode, a passivation layer and a pixel electrode are required for manufacturing a thin film transistor TFT device. The gate lines and the source and drain lines are generally formed using copper metal wires, the pixel electrodes are connected to signals using an oxide semiconductor, and a contact hole opening design is required for a gate insulating layer and a passivation layer for signal connection.
In a thin film transistor adopting a metal oxide as a semiconductor layer, a thin film used by a grid insulation layer and a passivation layer is a composite film structure of silicon oxide SiOx and silicon nitride SiNx, the film structure is complex and the difference of film quality is large, in the process of etching deep holes and shallow holes by using a dry etching process, the etching time is long, so that after the dry etching is finished, byproducts which cannot be removed and contact angle (tap) abnormity are generated, the contact impedance between metal copper and a pixel electrode is abnormal, the display abnormity in a panel is influenced, and the yield and the reliability of products are caused.
Therefore, the prior art has defects and needs to be improved urgently.
Disclosure of Invention
The invention provides an array substrate, a preparation method thereof and a display panel, which can avoid generating by-products in a contact hole etching process, improve contact angle abnormity, improve contact impedance and further improve the yield of products.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides a preparation method of an array substrate, which comprises the following steps:
step S10, preparing a layer of photoresist on the substrate with the grid, the grid insulating layer, the source and the drain and the passivation layer;
step S20, exposing the photoresist to form a photoresist complete removal area and a photoresist partial retention area which are spaced, wherein the photoresist partial retention area corresponds to an area for forming the first via hole, and the photoresist complete removal area corresponds to an area for forming the second via hole;
and step S30, etching the passivation layer and the gate insulating layer in an alternating manner of wet etching and dry etching to respectively form a first via hole corresponding to the source and drain electrode and a second via hole corresponding to the gate electrode, wherein the depth of the first via hole is smaller than that of the second via hole.
According to a preferred embodiment of the present invention, in the mask used in the exposure process of step S20, a portion of the mask corresponding to the photoresist completely removed region is a completely transparent region, a portion of the mask corresponding to the photoresist partially remaining region is a partially transparent region, and the rest of the mask is a non-transparent region.
According to a preferred embodiment of the present invention, the step S20 is followed by the following steps:
step S201, after the exposure process is completed, performing a developing process on the photoresist, removing the photoresist corresponding to the completely removed region of the photoresist, and partially retaining the photoresist corresponding to the partially retained region of the photoresist.
According to a preferred embodiment of the present invention, the step S30 includes the following steps:
step S301, performing first wet etching to etch away the passivation layer corresponding to the region where the second via hole is formed;
step S302, carrying out first dry etching, and etching away the photoresist corresponding to the partial reserved area of the photoresist;
step S303, performing a second wet etching to partially or completely etch away the gate insulating layer corresponding to the region where the second via hole is formed, and to etch away the passivation layer corresponding to the region where the first via hole is formed, so as to form the first via hole.
According to a preferred embodiment of the present invention, the gate insulating layer at least includes a first gate insulating layer and a second gate insulating layer, the second gate insulating layer is prepared on the first gate insulating layer, and the step S303 includes the following steps:
etching away the second gate insulating layer corresponding to a region where the second via hole is formed, and etching away the passivation layer corresponding to a region where the first via hole is formed.
According to a preferred embodiment of the present invention, the step S303 further includes the following steps:
step S304, performing a second dry etching to etch away the first gate insulating layer corresponding to the region where the second via hole is formed, so as to form the second via hole.
According to a preferred embodiment of the present invention, the passivation layer includes at least a first passivation layer and a second passivation layer, and the second passivation layer is formed on the first passivation layer.
According to a preferred embodiment of the present invention, after forming the first via and the second via, the method further comprises the steps of:
and step S40, removing the residual photoresist on the passivation layer.
The invention also provides an array substrate prepared by the preparation method.
The invention also provides a display panel comprising the array substrate.
The invention has the beneficial effects that: compared with the contact hole forming mode of the existing array substrate, the preparation method thereof and the display panel provided by the invention adopt a semi-permeable membrane mode, adopt all exposure modes at deep holes, adopt a semi-permeable membrane exposure mode at shallow holes, respectively etch the deep holes and the shallow holes, and adopt a wet etching and dry etching composite mode to etch; therefore, byproducts generated in the dry etching process are avoided, and the contact angle abnormity of the contact hole can be improved; in addition, because the semi-permeable membrane exposure mode is adopted at the shallow hole, the damage of dry etching gas to the source and drain electrode copper metal in the etching process is reduced, and therefore the contact impedance is improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art dry etching process for forming a contact hole;
fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 3A to 3E are schematic flow charts illustrating a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
Aiming at the technical problems that in the process of etching deep holes and shallow holes by using a dry etching process of an array substrate in the prior art, the etching time is long, byproducts which cannot be removed are generated, and the contact angle of a contact hole is abnormal, so that the contact impedance of metal copper and a pixel electrode is abnormal, and the display of a panel is influenced, the defect can be solved by the embodiment.
Fig. 1 is a schematic diagram illustrating a contact hole formed by dry etching in the prior art. In the thin film transistor with metal oxide as a semiconductor layer, a deep contact hole 10 and a shallow contact hole 11 are etched in a common exposure mode; wherein, the thin film used by the gate insulating layer 13 and the passivation layer 12 is a composite film structure of silicon oxide and silicon nitride, and a dry etching process is adopted to etch the shallow contact hole 11 and the deep contact hole 10 on the passivation layer 12 and the gate insulating layer 13; due to the long dry etching process time, by-products and the abnormal contact angle between the shallow contact hole 11 and the deep contact hole 10, such as the recessed area 14, may occur, which may cause the abnormal contact resistance between the metal signal line (such as the gate 15 and the source/drain 16) and the signal electrode, thereby affecting the display of the panel.
Fig. 2 is a flowchart of a method for manufacturing an array substrate according to a first embodiment of the present invention, and fig. 3A to 3E are schematic flowcharts of a method for manufacturing an array substrate according to a first embodiment of the present invention; the method comprises the following steps:
step S10, preparing a layer of photoresist on the substrate with the grid, the grid insulating layer, the source and the drain and the passivation layer;
specifically, as shown in fig. 3A, an array substrate is provided, where the array substrate includes a gate electrode 30, a gate insulating layer 31, a source/drain electrode 32, and a passivation layer 33 sequentially formed on a substrate (not shown), and a layer of photoresist 34 is formed on a surface of the passivation layer 33; the gate insulating layer 31 includes a first gate insulating layer 310 formed on a surface of the gate electrode 30, and a second gate insulating layer 311 formed on a surface of the first gate insulating layer 310; the passivation layer 33 includes a first passivation layer 330 formed on the surface of the source/drain electrode 32, and a second passivation layer 331 formed on the surface of the first passivation layer 330. The thin films used for the gate insulating layer 31 and the passivation layer 33 are both composite films of silicon oxide and silicon nitride.
Step S20, exposing the photoresist to form a photoresist complete removal area and a photoresist partial retention area which are spaced, wherein the photoresist partial retention area corresponds to an area for forming the first via hole, and the photoresist complete removal area corresponds to an area for forming the second via hole;
specifically, as shown in fig. 3A, in the mask 35 used in the exposure process of step S20, a portion of the mask 35 corresponding to the photoresist completely removed region 340 is a completely transparent region 350, a portion of the mask 35 corresponding to the photoresist partially remaining region 341 is a partially transparent region 351, and the rest of the mask 35 is a non-transparent region. Preferably, the light transmission amount of the partial light transmission region 351 of the mask 35 is between 30% and 70%.
The step S20 is followed by the following steps:
step S201, after the exposure process is completed, performing a developing process on the photoresist, removing the photoresist corresponding to the completely removed region of the photoresist, and partially retaining the photoresist corresponding to the partially retained region of the photoresist.
And step S30, etching the passivation layer and the gate insulating layer in an alternating manner of wet etching and dry etching to respectively form a first via hole corresponding to the source and drain electrode and a second via hole corresponding to the gate electrode, wherein the depth of the first via hole is smaller than that of the second via hole.
Specifically, the step S30 includes the steps of:
step S301, performing first wet etching to etch away the passivation layer corresponding to the region where the second via hole is formed;
as shown in fig. 3B, after exposure, a hydrofluoric acid etching solution is first used to perform a first wet etching process, so as to completely etch the passivation layer 33 corresponding to the region where the second via hole is formed, and no by-product is generated in this process.
Step S302, carrying out first dry etching, and etching away the photoresist corresponding to the partial reserved area of the photoresist;
as shown in fig. 3C, the photoresist 34 corresponding to the photoresist portion remaining region 341 is completely etched by a dry etching process.
Step S303, performing a second wet etching to partially or completely etch away the gate insulating layer corresponding to the region where the second via hole is formed, and to etch away the passivation layer corresponding to the region where the first via hole is formed, so as to form the first via hole.
As shown in fig. 3D, performing a second wet etching with a hydrofluoric acid etching solution to etch away the second gate insulating layer 311 corresponding to the region where the second via is formed, and simultaneously completely etching the passivation layer 33 (including the first passivation layer 330 and the second passivation layer 331) corresponding to the region where the first via is formed, so as to form a first via 36 communicating with the source and drain electrodes 32; this step does not produce by-products.
The step S303 is followed by the following steps:
step S304, performing a second dry etching to etch away the first gate insulating layer corresponding to the region where the second via hole is formed, so as to form the second via hole.
As shown in fig. 3E, the first gate insulating layer 310 corresponding to the region where the second via hole is formed is completely etched by a dry etching process to form a second via hole 37 communicating with the gate electrode 30. By-products are not generated in the step, and the source and drain electrodes 32 at the first via hole 36 are not damaged due to short etching time; the first via hole 36 and the second via hole 37 formed by the method have no abnormality.
After forming the first and second vias 36, 37, the method further comprises the steps of:
and step S40, removing the residual photoresist on the passivation layer.
Fig. 4 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention. The present embodiment is different from the first embodiment in that: the array substrate provided by this embodiment includes a gate 40, a gate insulating layer 41, a source/drain 42, and a passivation layer 43, which are sequentially stacked, where the gate insulating layer 41 includes a first gate insulating layer 410, and a second gate insulating layer 411 prepared on a surface of the first gate insulating layer 410; that is, the passivation layer 43 of this embodiment is a thin film made of silicon oxide or silicon nitride, and the gate insulating layer 41 is a composite film including silicon oxide and silicon nitride. The photo-masking process and the etching process of the array substrate of this embodiment for preparing the first via hole communicated with the source/drain 42 and the second via hole communicated with the gate 40 are the same as those of the etching process of the first embodiment, and specific reference is made to the description of the first embodiment, and details are not repeated here.
The preparation method of the array substrate provided by the third embodiment of the invention is characterized in that: the gate insulating layer of the array substrate provided by this embodiment is a thin film made of silicon oxide or silicon nitride; in the preparation method for forming the first via hole corresponding to the source/drain and the second via hole corresponding to the gate, the steps before the step S303 in the first embodiment are the same as those in the present embodiment, in the second wet etching of the step S303, the gate insulating layer corresponding to the region where the second via hole is formed is completely etched, the passivation layer corresponding to the region where the first via hole is formed is completely etched, the first via hole and the second via hole are formed at the same time, no by-product is generated, and the formed first via hole and the formed second via hole are free of abnormality, so that impedance abnormality is not caused.
Of course, the materials of the passivation layer and the gate insulating layer in the above embodiments are not limited to silicon oxide and silicon nitride, and may be other materials.
The preparation method of the array substrate provided by the above embodiment further includes, but is not limited to, the following steps: and preparing pixel electrodes and first signal electrodes which are distributed at intervals on the passivation layer, wherein the pixel electrodes are connected with the drain electrode through the first via hole, and the first signal electrodes are connected with the grid electrode through the second via hole.
Of course, the preparation method of the array substrate provided by the invention is not limited to the preparation of the via holes corresponding to the source and drain electrodes and the gate electrode, and can also be used for the preparation of other deep contact holes and shallow contact holes.
The invention also provides an array substrate prepared by the preparation method, which comprises a metal oxide semiconductor layer, a grid electrode, a grid insulating layer, a source drain electrode, a passivation layer, a pixel electrode, a first signal electrode and the like which are sequentially prepared on the substrate.
The invention also provides a display panel comprising the array substrate.
According to the array substrate, the preparation method thereof and the display panel, all exposure modes are adopted at the deep holes in a semi-permeable membrane mode, the semi-permeable membrane exposure mode is adopted at the shallow holes, the deep holes and the shallow holes are etched respectively, and the etching mode is a wet etching and dry etching composite mode; therefore, byproducts generated in the dry etching process are avoided, and the contact angle abnormity of the contact hole can be improved; in addition, because the semi-permeable membrane exposure mode is adopted at the shallow hole, the damage of dry etching gas to the source and drain electrode copper metal in the etching process is reduced, and therefore the contact impedance is improved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (9)
1. A preparation method of an array substrate is characterized by comprising the following steps:
step S10, preparing a layer of photoresist on the substrate with the grid, the grid insulating layer, the source and the drain and the passivation layer;
step S20, exposing the photoresist to form a photoresist complete removal area and a photoresist partial retention area which are spaced, wherein the photoresist partial retention area corresponds to an area for forming the first via hole, and the photoresist complete removal area corresponds to an area for forming the second via hole;
step S30, performing a first wet etching to etch away the passivation layer corresponding to the second via hole region;
carrying out first dry etching to etch away the photoresist corresponding to the part of the photoresist reserved area;
and carrying out second wet etching, etching away the part of the gate insulating layer corresponding to the formed second via hole region or completely, etching away the passivation layer corresponding to the formed first via hole region, and forming a first via hole corresponding to the source and drain electrode and a second via hole corresponding to the gate electrode, wherein the depth of the first via hole is smaller than that of the second via hole.
2. The method as claimed in claim 1, wherein in the mask used in the exposure process of step S20, a portion of the mask corresponding to the completely removed photoresist region is a completely transparent region, a portion of the mask corresponding to the partially remained photoresist region is a partially transparent region, and the rest of the mask is a non-transparent region.
3. The method for preparing a composite material according to claim 1, wherein the step S20 is further followed by the steps of:
step S201, after the exposure process is completed, performing a developing process on the photoresist, removing the photoresist corresponding to the completely removed region of the photoresist, and partially retaining the photoresist corresponding to the partially retained region of the photoresist.
4. The method as claimed in claim 1, wherein the gate insulating layer comprises at least a first gate insulating layer and a second gate insulating layer, the second gate insulating layer is formed on the first gate insulating layer, and the second wet etching comprises:
etching away the second gate insulating layer corresponding to a region where the second via hole is formed, and etching away the passivation layer corresponding to a region where the first via hole is formed.
5. The method of claim 4, wherein the second wet etching is followed by the steps of:
step S304, performing a second dry etching to etch away the first gate insulating layer corresponding to the region where the second via hole is formed, so as to form the second via hole.
6. The method of claim 1, wherein the passivation layers comprise at least a first passivation layer and a second passivation layer, and the second passivation layer is formed on the first passivation layer.
7. The method of manufacturing of claim 1, wherein after forming the first and second vias, the method further comprises:
and step S40, removing the residual photoresist on the passivation layer.
8. An array substrate prepared by the method of any one of claims 1 to 7.
9. A display panel comprising the array substrate of claim 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811019726.4A CN109166868B (en) | 2018-09-03 | 2018-09-03 | Array substrate, preparation method thereof and display panel |
| PCT/CN2018/105042 WO2020047882A1 (en) | 2018-09-03 | 2018-09-11 | Array substrate and manufacturing method therefor, and display panel |
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| CN201811019726.4A CN109166868B (en) | 2018-09-03 | 2018-09-03 | Array substrate, preparation method thereof and display panel |
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| CN109166868B true CN109166868B (en) | 2020-08-11 |
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| CN111399342A (en) * | 2020-03-26 | 2020-07-10 | 京东方科技集团股份有限公司 | Exposure device and etching method |
| CN111897168A (en) * | 2020-08-21 | 2020-11-06 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
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| CN104167365A (en) * | 2014-08-06 | 2014-11-26 | 京东方科技集团股份有限公司 | Metal oxide thin-film transistor, array substrate, manufacturing method of metal oxide thin-film transistor and display device |
| CN104505368A (en) * | 2014-12-24 | 2015-04-08 | 昆山国显光电有限公司 | Contact hole etching process, organic light-emitting display device and display device |
| CN104733384A (en) * | 2013-08-22 | 2015-06-24 | 合肥京东方光电科技有限公司 | Display substrate, display substrate manufacturing method and display device |
| CN107818945A (en) * | 2017-10-25 | 2018-03-20 | 武汉华星光电半导体显示技术有限公司 | A kind of method, array base palte and the display device of functional layer perforate |
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| TWI435152B (en) * | 2011-08-16 | 2014-04-21 | Chunghwa Picture Tubes Ltd | Method for forming contact hole |
| CN108064414A (en) * | 2016-11-23 | 2018-05-22 | 深圳市柔宇科技有限公司 | The manufacturing method of array substrate |
| CN108140646A (en) * | 2016-12-24 | 2018-06-08 | 深圳市柔宇科技有限公司 | Manufacturing method of array base plate |
| CN106684039B (en) * | 2017-02-07 | 2019-12-24 | 京东方科技集团股份有限公司 | Array substrate manufacturing method and array substrate |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733384A (en) * | 2013-08-22 | 2015-06-24 | 合肥京东方光电科技有限公司 | Display substrate, display substrate manufacturing method and display device |
| CN104167365A (en) * | 2014-08-06 | 2014-11-26 | 京东方科技集团股份有限公司 | Metal oxide thin-film transistor, array substrate, manufacturing method of metal oxide thin-film transistor and display device |
| CN104505368A (en) * | 2014-12-24 | 2015-04-08 | 昆山国显光电有限公司 | Contact hole etching process, organic light-emitting display device and display device |
| CN107818945A (en) * | 2017-10-25 | 2018-03-20 | 武汉华星光电半导体显示技术有限公司 | A kind of method, array base palte and the display device of functional layer perforate |
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| WO2020047882A1 (en) | 2020-03-12 |
| CN109166868A (en) | 2019-01-08 |
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