CN108064414A - The manufacturing method of array substrate - Google Patents
The manufacturing method of array substrate Download PDFInfo
- Publication number
- CN108064414A CN108064414A CN201680036284.7A CN201680036284A CN108064414A CN 108064414 A CN108064414 A CN 108064414A CN 201680036284 A CN201680036284 A CN 201680036284A CN 108064414 A CN108064414 A CN 108064414A
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- Prior art keywords
- photoresist
- layer
- array substrate
- manufacturing
- oxide semiconductor
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Abstract
The application provides a kind of manufacturing method of array substrate, including：Gate electrode and gate line, gate insulation layer, metal oxide semiconductor layer and etch stop layer are formed on substrate；Photoresist is formed on the etch stop layer；Gray level mask plate more than one is provided, to form half-exposure region and full exposure area on the photoresist；First etching is carried out to the etch stop layer and the gate insulation layer, to form the first via for leading to the gate line on the etch stop layer and the gate insulation layer；The photoresist in the half-exposure region is removed；The second etching is carried out to the etch stop layer, to be formed immediately below the second via for leading to the metal oxide semiconductor layer in the half-exposure region；Remove the photoresist.The manufacturing method of the application will not cause to damage when forming the first via to metal oxide semiconductor layer, improve the production yield of array substrate.
Description
Technical field
This application involves display technology field more particularly to a kind of manufacturing methods of array substrate.
Background technology
In the prior art, in order to reduce the manufacture cost of array substrate.Gate insulation layer (GI) and etch stop layer (ES) are logical
Frequently with along with mask plate (mask) be processed.But since the thickness of gate insulation layer is much larger than the thickness of etch stop layer
It spends, it, can be by the metal-oxide semiconductor (MOS) below etch stop layer during forming via by dry etching on gate insulation layer
Layer is exposed.Since the etching period of gate insulation layer is longer, the metal oxide semiconductor layer being exposed can be made
Into damage, it is therefore desirable to increase the thickness of metal oxide semiconductor layer.And increase the thickness one of metal oxide semiconductor layer
Aspect can increase manufacture cost, reduce production capacity.On the other hand, blocked up metal oxide semiconductor layer can become TFT characteristics
Difference ultimately results in product yield reduction.
In addition, when metal oxide semiconductor layer is etched and penetrates, gate electrode layer and the short circuit of source-drain electrode layer can be also caused
Risk.
Apply for content
The application's is designed to provide a kind of manufacturing method of array substrate, and this method can be to avoid on gate insulation layer
The damage caused by metal oxide semiconductor layer during via is formed, improves the production yield of array substrate.
To achieve the above object, the application provides following technical solution：
The application provides a kind of manufacturing method of array substrate, including：
Gate electrode and gate line, gate insulation layer, metal oxide semiconductor layer and etch stop layer are formed on substrate；
Photoresist is formed on the etch stop layer；
Gray level mask plate more than one is provided, the photoresist is patterned using more gray level mask plates, in institute
It states and half-exposure region and full exposure area is formed on photoresist, wherein, projection of the full exposure area on the gate line
With the gate line at least partly overlap, projection of the half-exposure region on the metal oxide semiconductor layer with it is described
Metal oxide semiconductor layer at least partly overlaps；
Using the photoresist as shielding layer, the etch stop layer below the full exposure area of the photoresist and described
Gate insulation layer carries out the first etching, to be formed on the etch stop layer immediately below the full exposure area and the gate insulation layer
Lead to the first via of the gate line；
The photoresist in the half-exposure region is removed；
Using the photoresist as shielding layer, the second etching is carried out to the etch stop layer, to be exposed in the photoresist half
Light region is formed immediately below the second via for leading to the metal oxide semiconductor layer；
Remove the photoresist.
Wherein, the method further includes：Ashing processing is carried out to the half-exposure region of the photoresist, to remove described half
The photoresist of exposure area.
Wherein, the method further includes：Dry etching is carried out to the etch stop layer and the gate insulation layer, to be formed
First via.
Wherein, the method further includes：Dry etching is carried out to the etch stop layer, to form second via.
Wherein, the etching gas that the dry etching uses for SF6, O2, Cl2, He, Ar in it is a kind of or arbitrary several mixed
It closes.
Wherein, the method further includes：After the completion of the photoresist step is removed, source is formed in second via
Pole and drain electrode and metal layer is formed in the first via to connect signal circuit.
Wherein, more gray level mask plates are intermediate tone mask version or gray tone mask plate.
Wherein, the removal photoresist step includes：Using cineration technics or wet etching process by the light
Photoresist removes.
Wherein, projection of the full exposure area on the gate line is contained in the gate line, the half-exposure area
Projection of the domain on the metal oxide semiconductor layer is contained in the metal oxide semiconductor layer.
Wherein, the etch stop layer uses the mixture of silica, silicon nitride or the two.
Wherein, the gate insulation layer uses the mixture of silica, silicon nitride or the two.
The embodiment of the present application has the following advantages that or advantageous effect：
In the manufacturing method of the array substrate of the application, photoresist is coated on etch stop layer, passes through more gray level masks
Version forms half-exposure region and full exposure area on the photoresist, leads to the of gate line full exposure area is formed below
One via, in half-exposure region the second through hole formed below for leading to metal oxide semiconductor layer.So as to form the first mistake
Metal oxide semiconductor layer will not be caused to damage during hole, improve the production yield of array substrate.
Description of the drawings
It in order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, below will be to institute in embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the application
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the manufacturing method FB(flow block) of the application array substrate.
Fig. 2-Fig. 5 is the manufacturing method flow diagram of array substrate shown in Fig. 1.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, the technical solution in the embodiment of the present application is carried out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment shall fall in the protection scope of this application.
Ordinal determinative employed in the application following embodiment, first, second grade is merely to clearly demonstrate this
The distinctive term of similar feature in application does not represent putting in order or using order for corresponding feature.
Referring to Fig. 1, Fig. 1 is the FB(flow block) of the manufacturing method of the application array substrate.A kind of embodiment party of the application
In formula, the manufacturing method of array substrate includes the following steps：
Step S1：Gate electrode and gate line, gate insulation layer, metal oxide semiconductor layer and erosion are sequentially formed on substrate
Carve barrier layer.
Specifically, please referring to Fig. 2, the gate electrode can be formed on the substrate 10 by a patterning processes
21 and the pattern of the gate line 22.The gate electrode 21 and the gate line 22 are made of identical material, such as can be selected
With metal or alloy such as Cr, W, Cu, Ti, Ta, Mo, the barrier metal layer being made of multiple layer metal can also meet needs.
Then, by PECVD, (plasma enhanced chemical vapor is sunk on the gate electrode 21 and the gate line 22
Area method) method deposition gate insulation layer 30.The gate insulation layer 30 covers the gate electrode 21 and the gate line 22.Gate insulation layer
30 can select the including but not limited to materials such as mixture of silica, silicon nitride or the two.
The metal oxide semiconductor layer 40 again may be by sputtering or the method for thermal evaporation is deposited on gate insulation layer
On 30, metal oxide semiconductor layer 40 can use IGZO (indium gal l ium zinc oxide, indium gallium zinc oxygen
Compound), HIZO, IZO, a-InZnO, a-InZnO, ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:
Nb, Cd-Sn-O or other metal oxides are made.Preferably, IGZO materials can be selected to be made.
The mixture of silica, silicon nitride or the two may be employed in etch stop layer 50.Pass through chemical vapour deposition technique
It is deposited on the gate insulation layer 30, the metal oxide semiconductor layer 40 is completely covered in etch stop layer 50.The metal
Oxide semiconductor layer 40 acts on：In (not shown) the progress wet etching of source-drain electrode layer, as source-drain electrode layer wet method
The terminal of etching, the stepped construction of 50 lower section of protection etch stop layer is from etching.
Step S2：Photoresist is formed on the etch stop layer.
Step S3：Gray level mask plate more than one is provided, the photoresist is patterned using more gray level mask plates,
To form half-exposure region and full exposure area on the photoresist, wherein, the full exposure area is on the gate line
Projection and the gate line at least partly overlap, projection of the half-exposure region on the metal oxide semiconductor layer
It is at least partly overlapped with the metal oxide semiconductor layer.
Optionally, more gray level mask plates 70 can be that intermediate tone mask version (Half tonemask) or gray tone are covered
Film version (Gray tone mask).More gray level mask plates 70 are covered above the photoresist 60.To the photoresist
60 are exposed, develop (i.e. photoetching) with finishing patterns.The photoresist 60 forms full exposure area after photoetching process
61 and half-exposure region 62.Wherein, projection of the full exposure area 61 on the gate line 22 and the gate line 22 to
Small part overlaps, projection of the half-exposure region 62 on the metal oxide semiconductor layer 40 and the metal oxide
Semiconductor layer 40 at least partly overlaps.The reason for so setting is：It is lost to gate insulation layer 30 and etch stop layer 50
During quarter, the position of etching is located at the underface of the full exposure area 61.Therefore, in order to enable the first via 81 that etching is formed
The gate line 22 can be led to, it is necessary to assure projection of the full exposure area 61 on the gate line 22 and the grid
Line 22 at least partly overlaps.Similarly, in order to ensure to be formed at the second via 82 of 62 lower section of half-exposure region can lead to it is described
Metal oxide semiconductor layer 40, it is necessary that the half-exposure region 62 is on the metal oxide semiconductor layer 40
Projection is at least partly overlapped with the metal oxide semiconductor layer 40.
Preferably, in order to ensure source-drain electrode layer (not shown) and the gate line 22 and the metal-oxide semiconductor (MOS)
The good contact of layer 40 should increase overlapping area and second via of first via 81 with the gate line 22 as far as possible
82 with the overlapping area of the metal oxide semiconductor layer 40.It then needs to ensure full exposure area 61 on the gate line 22
Projection be contained in the gate line 22, projection bag of the half-exposure region 62 on the metal oxide semiconductor layer 40
It is contained in the metal oxide semiconductor layer 40.
Step S4：Using the photoresist as shielding layer, etch stop layer below the full exposure area of the photoresist and
The gate insulation layer carries out the first etching, on the etch stop layer and the gate insulation layer immediately below the full exposure area
Form the first via for leading to the gate line.
Fig. 3 is please referred to, specifically, needing to be etched gate insulation layer 30 and etch stop layer 50 in this step
Technique.Preferably, dry method etch technology can be selected.In dry etch process, the etching positioned at complete 61 lower section of exposure area
Barrier layer 50 and gate insulation layer 30 can be etched successively.Positioned at 60 lower section of photoresist except corresponding with outskirt with full exposure area 61
Domain, due to there is the presence of photoresist 60, gate insulation layer 30 and etch stop layer 50 are from being etched gas etch.Present embodiment
In by controlling the etch-rate and etching period of etching gas, can lead in gate insulation layer 30 and the formation of etch stop layer 50
First via 81 of the gate line 22.That is, 22 part of gate line is exposed to first via 81.
Preferably, the selection that the etching gas can be appropriate, such as select SF6、O2、Cl2, it is a kind of in He, Ar (argon gas)
Or arbitrary several mixing etc..
Step S5：The photoresist in the half-exposure region is removed.
Please refer to Fig. 4.Specifically, ashing processing can be carried out to the photoresist 60 so that the half-exposure area
Photoresist at domain 62 is removed.It is understood that " the ashing processing " is reacted by oxygen photoresist, so as to by institute
It states 60 entirety of photoresist to thin, after 60 entirety of photoresist thins, the photoresist that half-exposure region 62 goes out can be completely removed first.
At this point, 50 part of etch stop layer is exposed to the half-exposure region 62.
Step S6：Using the photoresist as shielding layer, the etching below the photoresist half-exposure region stops
Layer carries out the second etching, to be formed immediately below the second mistake for leading to the metal oxide semiconductor layer in the half-exposure region
Hole.
Specifically, it needs to carry out etch stop layer 50 second etching in this step.Preferably, dry method can be selected to lose
Carving technology.In the dry etch process of this step, the etch stop layer 50 positioned at 62 lower section of half-exposure region exposes to described
Half-exposure region 62, therefore can be etched.Positioned at the lower section of photoresist 60 except corresponding with half-exposure region 62 with exterior domain, due to having
The presence of photoresist 60, etch stop layer 50 is from being etched gas etch.By controlling etching gas in present embodiment
Etch-rate and etching period can form the second via for leading to the metal oxide semiconductor layer 40 with etch stop layer 50
82.That is, 40 part of metal oxide semiconductor layer is exposed to second via 82.
Optionally, the etching gas in this step can be consistent with the etching gas in step S4.
Step S7：Remove the photoresist.
Specifically, refer to Fig. 5.The photoresist can be removed by wet etching process.The process may be employed existing
There is the photoresist lift off method of technology, details are not described herein.Alternatively, above-mentioned cineration technics can also be used to remove the photoetching
Glue.
Further, after the photoresist is removed, it is also necessary to source electrode and drain electrode are formed in second via, with
And metal layer is formed in the first via to connect signal circuit.The signal circuit can be the circuit on another array substrate,
Or external signal circuit.
In the manufacturing method of the array substrate of the application, photoresist is coated on etch stop layer, passes through more gray level masks
Version forms half-exposure region and full exposure area on the photoresist, leads to the of gate line full exposure area is formed below
One via, in half-exposure region the second through hole formed below for leading to metal oxide semiconductor layer.So as to form the first mistake
Metal oxide semiconductor layer will not be caused to damage during hole, improve the production yield of array substrate.
The embodiment of the present application is described in detail above, specific case used herein to the principle of the application and
Embodiment is set forth, and the explanation of above example is only intended to help to understand the present processes and its core concept；
Meanwhile for those of ordinary skill in the art, according to the thought of the application, can in specific embodiments and applications
There is change part, in conclusion this specification content should not be construed as the limitation to the application.
Claims (11)
1. a kind of manufacturing method of array substrate, which is characterized in that including：
Gate electrode and gate line, gate insulation layer, metal oxide semiconductor layer and etch stop layer are formed on substrate；
Photoresist is formed on the etch stop layer；
Gray level mask plate more than one is provided, the photoresist is patterned using more gray level mask plates, in the light
Half-exposure region and full exposure area are formed in photoresist, wherein, projection and institute of the full exposure area on the gate line
It states gate line at least partly to overlap, projection of the half-exposure region on the metal oxide semiconductor layer and the metal
Oxide semiconductor layer at least partly overlaps；
Using the photoresist as shielding layer, etch stop layer and gate insulation layer below the full exposure area of the photoresist carry out
First etching leads to the grid to be formed on the etch stop layer immediately below the full exposure area and the gate insulation layer
First via of line；
The photoresist in the half-exposure region is removed；
Using the photoresist as shielding layer, the etch stop layer below the photoresist half-exposure region carries out the second erosion
It carves, to be formed immediately below the second via for leading to the metal oxide semiconductor layer in the half-exposure region；
Remove the photoresist.
2. the manufacturing method of array substrate as described in claim 1, which is characterized in that the method further includes：To the light
The half-exposure region of photoresist carries out ashing processing, to remove the photoresist in the half-exposure region.
3. the manufacturing method of array substrate as described in claim 1, which is characterized in that the method further includes：To the erosion
It carves barrier layer and the gate insulation layer carries out dry etching, to form first via.
4. the manufacturing method of array substrate as described in claim 1, which is characterized in that the method further includes：To the erosion
It carves barrier layer and carries out dry etching, to form second via.
5. the manufacturing method of the array substrate as described in claim 3 or 4, which is characterized in that the erosion that the dry etching uses
Quarter gas be SF6、O2、Cl2, a kind of in He, Ar or arbitrary several mixing.
6. the manufacturing method of array substrate as described in claim 1, which is characterized in that the method further includes：In removal institute
After the completion of stating photoresist step, source electrode and drain electrode are formed in second via and forms metal layer in the first via
To connect signal circuit.
7. the manufacturing method of array substrate as described in claim 1, which is characterized in that more gray level mask plates are halftoning
Mask plate or gray tone mask plate.
8. the manufacturing method of array substrate as described in claim 1, which is characterized in that in the removal photoresist step
Including：The photoresist is removed using cineration technics or wet etching process.
9. the manufacturing method of array substrate as described in claim 1, which is characterized in that the full exposure area is in the grid
Projection on line is contained in the gate line, and projection of the half-exposure region on the metal oxide semiconductor layer includes
In the metal oxide semiconductor layer.
10. the manufacturing method of array substrate as described in claim 1, which is characterized in that the etch stop layer is using oxidation
The mixture of silicon, silicon nitride or the two.
11. the manufacturing method of array substrate as described in claim 1, which is characterized in that the gate insulation layer using silica,
The mixture of silicon nitride or the two.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2016/106890 WO2018094598A1 (en) | 2016-11-23 | 2016-11-23 | Method for manufacturing array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108064414A true CN108064414A (en) | 2018-05-22 |
Family
ID=62138112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680036284.7A Pending CN108064414A (en) | 2016-11-23 | 2016-11-23 | The manufacturing method of array substrate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108064414A (en) |
| WO (1) | WO2018094598A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020047882A1 (en) * | 2018-09-03 | 2020-03-12 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and manufacturing method therefor, and display panel |
| CN113161375A (en) * | 2021-04-09 | 2021-07-23 | 京东方科技集团股份有限公司 | Array substrate, display device and preparation method thereof |
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| CN105161504B (en) * | 2015-09-22 | 2019-01-04 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
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- 2016-11-23 WO PCT/CN2016/106890 patent/WO2018094598A1/en active Application Filing
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| CN103000628A (en) * | 2012-12-14 | 2013-03-27 | 京东方科技集团股份有限公司 | Display device, array substrate and manufacture method of array substrate |
| CN104576542A (en) * | 2015-01-26 | 2015-04-29 | 合肥鑫晟光电科技有限公司 | Array substrate, manufacturing method of array substrate and display device |
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| Publication number | Publication date |
|---|---|
| WO2018094598A1 (en) | 2018-05-31 |
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Application publication date: 20180522 |