JP2002184999A - Manufacturing method of array substrate for display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of required patterning processes, and the number of mask patterns in the manufacturing method of an etching stopper type TFT array substrate used for a liquid crystal display or the like. SOLUTION: A raster 11, a gate electrode 11a, and a raster pad section 11b are formed, and a gate insulating film 15, a semiconductor film 36, and an insulating protection covering 2 are deposited. After resist 6 is applied onto it, and a kind of half-tone exposure is achieved by exposure from a front side that uses a mask pattern 65 and has large intensity, and a back side that uses the raster 11 or the like as the mask and has small intensity. A contact hole 25 is formed under a resist pattern 61 with a step obtained in this manner. By appropriate ashing, the resist pattern is left merely at a place on the raster 11 with large film thickness or the like, Under a reduced resist pattern 62, a channel protection film (an etching stopper) 21 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an array substrate used for a flat panel display such as a liquid crystal display.

[0002]

2. Description of the Related Art In recent years, flat-panel display devices replacing CRT displays have been actively developed. Among them, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, low power consumption, and low eye fatigue. I am collecting.

[0003] For example, a light-transmitting active-matrix liquid crystal display device in which a switch element is arranged for each display pixel will be described as an example. The active matrix type liquid crystal display device has a configuration in which a liquid crystal layer is held between an array substrate and a counter substrate via an alignment film. In the array substrate, a plurality of signal lines and scanning lines are arranged in a lattice on a transparent insulating substrate such as glass or quartz, and a semiconductor thin film such as amorphous silicon (a-Si: H) is used at each intersection. A thin film transistor (hereinafter abbreviated as TFT) is connected. The gate electrode of the TFT is electrically connected to a scanning line, the drain electrode is electrically connected to a signal line, and the source electrode is a transparent conductive material constituting a pixel electrode, for example, IT.
It is electrically connected to O (Indium-Tin-Oxide).

[0004] The opposing substrate is configured such that an opposing electrode made of ITO is disposed on a transparent insulating substrate such as glass, and a color filter layer is disposed for realizing color display.

In arranging a TFT for each display pixel as described above, there are a type in which a channel protective film is provided at a position covering a channel portion of the TFT (etching stopper type) and a type in which a channel protective film is not provided (back channel cut type). ,
Each has advantages and disadvantages, and all are widely manufactured.

[0006] Conventionally, an etching stopper type TFT array substrate is formed by, for example, the following seven patterning processes (Photo Engraving Process), and requires a mask pattern (array mask) for each patterning process.

(1) Step of forming a first wiring layer pattern including a scanning line and a gate electrode → (2) Step of forming a channel protective film → (3) Step of forming a pattern of a semiconductor active layer of a TFT → ( 4) Step of forming conductive layer pattern including pixel electrode → (5) Step of forming through hole (contact hole) in gate insulating film covering first wiring layer pattern →
(6) a step of forming a second wiring layer pattern including a signal line, a source electrode and a drain electrode → (7) a step of providing an interlayer insulating film (passivation film) covering the second wiring layer pattern to expose a pad portion.

However, in order to reduce the manufacturing cost of the active matrix liquid crystal display device, there is a problem that the number of steps for manufacturing the array substrate is large and the cost ratio of the array substrate is high.

Therefore, in Japanese Patent Application No. 8-260572, a pixel electrode is arranged on the uppermost layer, and accordingly, a signal line,
After collectively patterning the semiconductor film and the like together with the source and drain electrodes based on the same mask pattern, a contact hole for the source electrode connecting the source electrode and the pixel electrode is formed, and a signal line and a scanning line are formed. It has been proposed to simultaneously form an outer peripheral contact hole for exposing a connection end.

According to the method proposed in Japanese Patent Application No. 8-260572, an array substrate can be manufactured by five patterning steps using five mask patterns as follows.

(1) a step of forming a first wiring layer pattern including a scanning line and a gate electrode → (2) a step of forming a channel protective film → (3) a pattern of a semiconductor active layer of a TFT and the second wiring layer Step of forming pattern and pattern at once → (4) Step of forming contact hole after depositing interlayer insulating film →
(5) A step of forming a conductive layer pattern including a pixel electrode.

[0012]

The demand for lowering the cost of the entire device has recently led to a demand for improvements in array substrate manufacturing efficiency and a reduction in manufacturing cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing an array substrate having an etching stopper type TFT, in which a step operation for patterning or the number of mask patterns is further reduced. Accordingly, it is an object of the present invention to provide a manufacturing method capable of improving manufacturing efficiency and reducing manufacturing cost.

[0014]

According to a first aspect of the present invention, there is provided a method of manufacturing an array substrate, comprising: forming a first wiring layer pattern including a plurality of scanning lines, gate electrodes, and scanning line pads on an insulating substrate; Depositing or coating a gate insulating film, a semiconductor film, and a protective insulating film covering the first conductive layer pattern, and then patterning the protective insulating film to form a channel protective film at a location covering the gate electrode; Forming a second wiring layer pattern including a signal line substantially perpendicular to a scanning line, a source electrode, and a drain electrode; forming a contact hole exposing the scanning line pad portion through the gate insulating film; Forming a conductive layer pattern including a pixel electrode electrically connected to a source electrode. The step of forming a hole includes a stepped portion at a location of the scanning line pad portion, and a thickness of a location covering the gate electrode is larger than a thickness of a location sandwiching the location from the source electrode side and the drain electrode side. A step of forming a resist pattern and a step of performing etching under the stepped resist pattern. The step of forming the channel protective film is performed only at a portion having a large thickness among the stepped resist pattern. And a step of forming the channel protective film by etching under the reduced resist pattern.

According to the above configuration, the number of steps for patterning or the number of mask patterns can be reduced, thereby improving manufacturing efficiency and reducing manufacturing costs.

According to a second aspect of the present invention, there is provided a method of manufacturing an array substrate.
The insulating substrate is light-transmissive, and the exposure for forming the stepped resist pattern is performed at a different intensity from the exposure from the front side for forming the cutout portion and the exposure from the front side. And back surface exposure in which exposure is performed from the back side using the first wiring layer as a mask.

With this configuration, it is not necessary to use a relatively expensive mask pattern provided with a screen pattern or the like in forming the stepped resist pattern.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
8 will be described.

FIG. 1 is a plan view schematically showing the configuration of each pixel on the array substrate and the peripheral portion for connection. FIG.
Shows the laminated structure of the main part of the completed array substrate.

As shown in FIG. 1, near the intersection of the lower scanning line 11 and the upper signal line 31, the signal from the signal line 31 to the pixel electrode 42 according to the scanning pulse sequentially applied to the scanning line 11. A TFT 7 for switching an input is provided. The gate electrode 11a of the TFT 7 is formed by an extending part integral with the scanning line 11, and the drain electrode 32 of the TFT 7 is formed by an extending part integral with the signal line 31. Then, the source electrode 33 of the TFT 7
Are electrically connected to the pixel electrode 42 by being directly covered with the pixel electrode 42 partially. In each pixel electrode 42, a pixel electrode extension portion 42 a that covers the scanning line 11 is provided at an edge opposite to the connection point with the source electrode 33.
To form an auxiliary capacitance (Cs) with the scanning line 11.

From one end of each scanning line 11, a lead-out wiring 11c is drawn out to a connection peripheral portion 10a of the array substrate 10, and a scanning line pad portion 11b is formed at the leading end. A contact hole penetrating the gate insulating film 15 is provided at the location of the scanning line pad portion 11b.

Next, the manufacturing process of the array substrate of the embodiment will be described in detail with reference to FIGS.

In each of the partial longitudinal sectional views of the array substrate shown in FIGS. 2 to 8, a TFT portion (section AA in FIG. 1) and a storage capacitor (Cs) forming portion (section BB in FIG. 1) in each step are shown. ),
1 schematically shows a layered structure of a scanning line connection pad (a cross section taken along line CC in FIG. 1).

(1) First Patterning (FIG. 1) A metal or alloy such as a molybdenum-tungsten alloy film (MoW film) is deposited on the glass substrate 18 by a sputtering method to a thickness of 230 nm. Then, after applying a resist, exposure and development are performed using the first mask pattern, and then etching is performed using an etching solution including phosphoric acid, acetic acid, nitric acid, and water.

By patterning such an alloy film,
756 scanning lines 11 and lead-out lines 11c and pad portions 11b at the ends thereof, which are drawn out to one end side of the array substrate 10, are formed. In the pixel region, a gate electrode 11 composed of an extension of the scanning line 11 corresponds to each pixel.
a is created.

(2) Second patterning (2-1) Deposition of a multilayer film and formation of a stepped resist pattern (FIG. 3) The first gate insulating film 16 made of a silicon oxide film having a thickness of 350 nm by a plasma CVD method. And depositing a second gate insulating film 17 made of a 50 nm thick silicon nitride film, and further forming a semiconductor active layer of the TFT 9.
A semiconductor film 36 made of amorphous silicon (a-Si: H) having a thickness of 50 nm and a protective insulating film 2 made of silicon nitride having a thickness of 200 nm are successively deposited.

On the thus obtained multilayer film, 1
After applying a negative type resist (a type through which a light irradiating portion passes) with a thickness of not less than 2 μm, for example, about 2 μm, the second mask pattern 65 is used to apply a resist from above the substrate, that is, from the side where the multilayer film is formed. For example, exposure is performed using light having relatively high intensity. The second mask pattern 65 is
It has a blank pattern 66 corresponding to the scanning line pad portion 11b.

Simultaneously with or before or after the exposure from the front side, from under the substrate, that is, from the back surface of the glass substrate 18,
For example, light having relatively low intensity is applied. By such irradiation from the back side of the substrate, back side exposure using the pattern of the scanning lines 11 and the gate electrodes 11a as a mask is performed.

By performing development and removal of the uncured resist after such an exposure operation, a portion 63 of the resist is formed at the portion of the scanning line pad portion 11b that has received intense light, and no light is received. On the gate electrode 11a
On the scanning lines 11, a resist layer having a large thickness is formed. On the other hand, a resist layer having a small thickness is formed in other regions, that is, regions where weak light from the back surface is received. Therefore, a stepped resist pattern 61 as schematically shown in FIG. 3 is formed.

This is exactly the same as in the case of halftone exposure in which an exposure operation is performed by providing a screen pattern region or a semi-transmissive region in a mask pattern.

(2-2) Formation of Contact Hole by Etching (FIG. 4) By performing an etching operation under the stepped resist pattern 61, the upper surface of the scanning line pad portion 11b penetrates through the gate insulating film 15. A contact hole 25 to be exposed is formed.

(2-3) Reduction of resist pattern by ashing (FIG. 5) Next, ashing is performed by controlling the time so that only a portion having a large film thickness in the stepped resist pattern 61 remains, which is appropriate ashing. . That is, the gate electrode 1
A reduced resist pattern 62 covering only portions such as on 1a and on the scanning line 11 is obtained.

(2-4) Formation of Channel Protecting Film (FIG. 6) By etching under the reduced resist pattern 62, the channel protecting film 21 is formed on the gate electrode 11a.
To form At this time, the linear protective film 22 is formed with the insulating protective film 2 remaining linearly on the scanning line 11. The linear protective film 22 plays a role in preventing a short circuit between the scanning line 11 and the conductive layer overlapping the scanning line 11 when the gate insulating film 15 has a defect.

(3) Third patterning Low-resistance semiconductor film 3 made of phosphorus-doped amorphous silicon (n + a-Si: H) having a thickness of 50 nm by a plasma CVD method.
7 is deposited. Then, after treatment with hydrofluoric acid to obtain a good ohmic contact, a 25-nm thick Mo layer, a 250-nm aluminum (Al) layer, and a 50-nm thick Mo layer are deposited in this order by sputtering. The three-layer metal film and the semiconductor layers 36 and 37 thus obtained are collectively patterned under a resist pattern obtained by exposing and developing using a third mask pattern. First, the three-layer metal film is etched with an etchant composed of phosphoric acid, acetic acid, nitric acid and water, and then the semiconductor films 36 and 37 are patterned by plasma etching (Plasma Etching).

As described above, the signal line 31, the drain electrode 32 composed of the extension, and the source electrode 33 are formed.

(4) Fourth patterning (FIG. 8) After depositing a 40 nm thick ITO as a transparent conductive layer,
A pad part ITO film 41 covering the pad part 11b, a pixel electrode 42, and a pixel electrode extension part 42a for forming a storage capacitor (Cs) are formed. FIG. 8 schematically shows the layered structure of the array substrate of the embodiment completed as described above.

In this embodiment, since the linear protective film 22 formed simultaneously with the channel protective film 21 exists between the pixel electrode extending portion 42a and the scanning line 11, the conductor 42a forming the auxiliary capacitance is provided. , 11 are increased. But,
Normally, an appropriate size of the storage capacitor can be realized by appropriately increasing the size of the pixel electrode extension portion 42a along the scanning line 11.

Although not shown in the drawing, an organic or inorganic protective film and an alignment film for a liquid crystal display device are usually formed on the uppermost layer of the array substrate.

According to the above embodiment, an array substrate of a type having a channel protective film at a TFT position can be manufactured by a patterning operation using four mask patterns. Compared to the conventional case using five mask patterns, the number of mask patterns can be reduced.
In the patterning step for forming the channel protective film and the patterning step for forming the contact hole, the steps of separately applying the resist, exposing and developing, removing the resist, and washing can be performed once. Therefore, it is possible to improve the manufacturing efficiency of the array substrate and reduce the cost.

In particular, in forming the stepped resist pattern 61, the illuminance or irradiation time for backside exposure and the illuminance or irradiation time for exposure from the front side are properly controlled without using a special mask pattern. Enables the formation of special resist patterns,
An increase in cost for manufacturing a mask pattern can be prevented. In order to make the intensity of the backside exposure different from the intensity of the exposure from the front side, the wavelength or the wavelength configuration may be changed in addition to simply adjusting the integrated light amount by changing the irradiation time or the illuminance.

However, needless to say, in forming the stepped resist pattern 61, a screen pattern or a mesh pattern is provided in a specific region of the mask pattern, or a semi-transmissive material is formed, as in a general halftone technique. It is also possible to adopt a method such as coating. In this case, the insulating protective film 2 is applied to the gate electrode 11a.
It is possible to leave only the upper portion, that is, the portion forming the channel protective film 21.

The light mentioned here includes not only visible light but also ultraviolet light.

According to the manufacturing method of the above embodiment, an interlayer insulating film (passivation film) for covering an upper metal wiring layer pattern such as a signal line is formed before forming an ITO film pattern such as a pixel electrode. Can not. But IT
By providing an appropriate protective film on the O film pattern,
It is possible to prevent adverse effects such as elution of a metal into the liquid crystal from a signal line or the like. Further, as a material for the signal line and the like, molybdenum (Mo) or aluminum (A) used in the above-described embodiment is used.
If copper (Cu), silver (Ag), palladium (Pd), or the like is used instead of l), the adverse effect on the liquid crystal layer can be effectively suppressed.

In the above embodiment, the description has been made assuming that the insulating protective film 2 does not remain at all outside the pattern of the scanning line 11 and the gate electrode 11a. However, in some cases, the source electrode 33 and the drain electrode 32 are formed of a semiconductor. Layer 3
The pattern of the insulating protective film 2 may be arranged in an arbitrary region other than the portion where the insulating protective film 6 comes into contact. However, for this purpose, it is necessary to use a mask pattern having a screen pattern or the like.

Next, a method of manufacturing an array substrate according to a modification will be described with reference to the lamination diagram of FIG.

In a modified example, in the same manufacturing method as in the above-described embodiment, another film is formed after the completion of the third patterning and before the fourth patterning (patterning of the ITO film). A step of forming a pattern of the organic protective film 5 having a much larger thickness is performed. The thickness of the organic protective film 5 is generally 1 μm or more, typically 1.5 to 4 μm, and more preferably 2 to 3 μm. With the arrangement of the pattern of the organic protective film 5, the pixel electrode 42
It is possible to omit the black matrix at this location by superimposing the four peripheral edges with the scanning line 11 and the signal line 31, thereby improving the pixel aperture ratio. The pattern of the organic protective film 5 includes a portion of the source electrode 33 and a pixel electrode extension 4 for forming a storage capacitor.
A blank portion exposing the portion 2a is provided.

In the illustrated example, the organic protective film 5 is a flat film having the same upper surface height, and plays a role of a flattening film for absorbing irregularities on the upper surface of the array substrate. The organic protective film 5 also functions as an interlayer insulating film that prevents the metal of the upper wiring layer such as the signal line 31 from seeping into the liquid crystal.

The organic protective film 5 is made of, for example, a transparent resin which is photocurable, and a pattern is directly formed by exposure using a mask pattern and removal of the uncured resin. That is, a pattern is formed without an etching operation. The organic protective film 5 can also serve as a color filter by dyeing using an inkjet technique or the like.

As described above, in the method of manufacturing an array substrate according to the modified example, although the number of mask patterns and the number of patterning are increased by one, the pixel aperture ratio can be increased, A color filter layer can be formed in the protective film 5, and it can also serve as an interlayer insulating film.

In the above embodiments and modifications, the pixel electrode is formed of an ITO film. However, other transparent conductive materials can be used. Materials can also be used.

Although the array substrate has been described as being used for a liquid crystal display device, an organic EL (Electro Luminecen
It can be used for other flat display devices such as ce).

It goes without saying that the same is true even if the semiconductor active layer in the TFT on the array substrate is a polycrystalline silicon film instead of the amorphous silicon layer.

[0053]

As described above, in the method of manufacturing an array substrate having an etching stopper type TFT, the number of steps for patterning or the number of mask patterns can be reduced, thereby improving manufacturing efficiency and reducing manufacturing costs. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a configuration of each pixel and a connection peripheral portion on an array substrate according to an embodiment.

FIG. 2 is a view showing a first step in a manufacturing process of the array substrate of the embodiment.
FIG. 4 is a cross-sectional perspective view of main parts showing a state after patterning of FIG.

FIG. 3 is a view showing a second step in the manufacturing process of the array substrate of the embodiment.
FIG. 3 is a cross-sectional perspective view of main parts corresponding to FIG. 2 for describing formation of a stepped resist pattern for patterning.

FIG. 4 shows a state after a first etching in a second patterning step according to the embodiment, that is, after forming a contact hole under a stepped resist pattern.
FIG. 3 is a sectional perspective view of a main part corresponding to FIG. 2.

FIG. 5 is a cross-sectional perspective view of a main part corresponding to FIG. 2, showing a state where only a thick film portion is left by ashing the resist pattern in a second patterning step according to the embodiment.

FIG. 6 illustrates a second example of the manufacturing process of the array substrate according to the embodiment.
FIG. 3 is a cross-sectional perspective view of a main part corresponding to FIG. 2, showing a state at the time of completion of patterning, that is, a state after formation of a channel protective film.

FIG. 7 shows a third step in the process of manufacturing the array substrate of the example.
FIG. 3 is a cross-sectional perspective view of a main part corresponding to FIG. 2 and showing a state after patterning of FIG.

FIG. 8 is a view showing a fourth step in the manufacturing process of the array substrate according to the embodiment;
FIG. 3 is a cross-sectional perspective view of a main part corresponding to FIG. 2, showing a state after patterning, that is, a state when an array substrate is completed.

FIG. 9 is a cross-sectional perspective view of a main part corresponding to FIG. 8, for describing a manufacturing process of an array substrate according to a modified example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Array substrate 11 Scan line 11a Gate electrode 11b Scan line pad part 15 Two-layer gate insulating film 16 First gate insulating film 17 Second gate insulating film 2 Protective insulating film 21 Channel protective film 22 Simultaneously formed with channel protective film Linear protective film 25 contact hole for exposing scanning line pad portion 11b 31 signal line 41 pad portion ITO film 42 pixel electrode 61 stepped resist pattern 62 reduced resist pattern after ashing

Continued on the front page F-term (reference) 2H092 GA33 JA26 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB53 JB57 JB63 JB69 KA05 KA07 KB14 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA28 MA35 MA37 MA41 NA27 5C094 AA43 A19 AA23 BA14 DA14 EA04 EA07 EB02 FB01 FB12 FB14 FB15 GB10 5F110 AA16 BB01 CC07 DD02 EE06 EE44 FF02 FF03 FF09 FF30 GG02 GG15 GG25 GG45 HK02 HK03 HK04 HK09 HK16 HK22 HK25 HK33 NN24 NN35 NN04 NN

Claims (5)

[Claims] A step of forming a first wiring layer pattern including a plurality of scanning lines, a gate electrode and a scanning line pad on an insulating substrate; a gate insulating film covering the first conductive layer pattern; a semiconductor film; After depositing or coating a protective insulating coating,
Patterning the protective insulating film to form a channel protective film at a position covering the gate electrode; and forming a second wiring layer pattern including a signal line, a source electrode, and a drain electrode substantially orthogonal to the scanning line. A display device, comprising: forming a contact hole exposing the scanning line pad portion through the gate insulating film; and forming a conductive layer pattern including a pixel electrode electrically connected to the source electrode. In the method for manufacturing an array substrate for use, the contact hole forming step has a cutout portion at the scan line pad portion, and the thickness of the portion covering the gate electrode is changed to the source electrode side and the drain electrode side. Forming a resist pattern with a step larger than the thickness of the portion sandwiched from Forming the channel protective film, the step of forming a reduced resist pattern from the stepped resist pattern in which only a portion having a large thickness remains, and the step of forming the channel protective film. Forming the channel protective film by etching under a pattern. 2. The method according to claim 2, wherein the insulating substrate is light-transmissive, and the exposure for forming the stepped resist pattern is performed from the front side for forming the blank portion.
2. The method for manufacturing an array substrate according to claim 1, wherein the back surface exposure is performed by using the first wiring layer as a mask from the back surface side of the insulating substrate at a different intensity from the exposure from the front side. 3. The method according to claim 1, wherein the step of forming the second wiring layer pattern is performed by collectively patterning a metal layer and the semiconductor film under one resist pattern. Method for manufacturing an array substrate. 4. The method according to claim 1, wherein a step of forming a conductive layer pattern including the pixel electrode is performed subsequent to the step of forming the second wiring layer pattern. 5. A step of forming a pattern of an organic protective film having a thickness of 1 μm or more after the step of forming the second wiring layer pattern and before the step of forming a conductive layer pattern including the pixel electrode. The method for manufacturing an array substrate according to claim 1, further comprising: