CN101087004A - TFT array substrate, manufacturing method thereof and display device - Google Patents
TFT array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN101087004A CN101087004A CNA2007101102680A CN200710110268A CN101087004A CN 101087004 A CN101087004 A CN 101087004A CN A2007101102680 A CNA2007101102680 A CN A2007101102680A CN 200710110268 A CN200710110268 A CN 200710110268A CN 101087004 A CN101087004 A CN 101087004A
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- nesa coating
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- 229910002651 NO3 Inorganic materials 0.000 description 2
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 2
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Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
The invention provides an excellent TFT array substrate, its preparation method, and display device of the substrate. The TFT array substrate of the invention is in channel area (43) between source cathode region (41) and drain electrode region (42), and comprises: gate electrode (2) forming on the substrate (1), gate electrode insulation membrane (3) forming by the type of covering the gate electrode (2), semiconductor layer (30) located on the gate electrode (2) separated by the gate electrode insulation membrane (3), source cathode (6) with metal membrane located on the source cathode region (41) of the semiconductor layer (30), drain electrode (7) with metal membrane located on the drain electrode region (42) of the semiconductor layer (30), transparent conductive films (10) located between the source cathode (6) and the source cathode region (41) and between the drain electrode (7) and the drain electrode region (42). The section plane of transparent conductive films (10) extending part from the semiconductor layer (30) is cone shape.
Description
Technical field
The display unit that the present invention relates to tft array substrate, its manufacture method and use this substrate.
Background technology
In tft active matrix array (active matrix array) substrate that display unit is used (below be designated as the tft array substrate), existence will be used the situation of the thin-film transistor (below be designated as TFT:Thin Filmed Transistor) of amorphous silicon (Amorphous Silicon below is designated as a-Si) as switch (switching) element.General five lithography steps (photomechanical process step) that use are made this tft array substrate.One example of conventional example is disclosed in patent documentation 1.Fig. 6 is the TFT figure partly of the tft array substrate of expression patent documentation 1, is the profile of the general TFT cross-section structure of expression.
In tft array substrate shown in Figure 6, dispose dielectric substrate 21, gate electrode 22, gate insulating film 23, the active film 24 of semiconductor, ohmic contact (ohmic contact) film 25, source electrode 26, drain electrode 27, passivating film 28 and pixel electrode 29.Dielectric substrate 21 is formed by glass (glass) substrate etc.Gate electrode 22 is for example formed by Cr film etc.Gate insulating film 23 is for example formed by silicon nitride (Silicon Nitride: below be designated as SiN).The active film 24 of semiconductor is a-Si films.Ohmic contact film 25 is to be doped with the n type a-Si film that (doping) obtains the phosphorus (phosphorus) that the active film of semiconductor 24 and the ohmic contact of upper metal use.Form semiconductor regions by active film 24 of this semiconductor and ohmic contact film 25, also these two is generically and collectively referred to as semiconductor layer sometimes.Source electrode 26 and drain electrode 27 are for example formed by Cr film etc.Pixel electrode 29 is for example by ITO (the Indium Tin Oxide: indium tin oxide) form as the oxide of indium (indium) and tin (tin).Following technology is disclosed in patent documentation 1: in order to improve the productivity ratio of display unit, carry out five tft array substrates photoetching (photolithography: photoetching) step, thus, reduce number of manufacture steps.
In addition, the technology that relates to the tft array substrate is disclosed in patent documentation 2.In patent documentation 2, show prevent that electrical characteristics from disperseing structure (not shown).Since cover source electrode and drain electrode passivating film adhere to (hang) shape, cause applying load to TFT.In patent documentation 2, prevent the dispersion of the electrical characteristics of the TFT that causes by this load.In patent documentation 2, behind the figure (pattern) that forms semiconductor layer, forming the metal film that ITO film, source electrode and drain electrode are used in one deck (layer) step down.The ITO film is arranged between source electrode and drain electrode and the semiconductor layer.And, with semiconductor layer on the source electrode extremely compare the mode that is exposed to the channel region side with electric leakage, dispose the ITO film with staggering.Thus, relaxed from source electrode and drain electrode, obtained the non-effect of adhering to of passivating film to the step difference of semiconductor layer.
No. 3234168 communique of patent documentation 1 special permission
But the inventor finds to exist in the prior art following technical problem.Usually, the composition of the metal film used of gate electrode, source electrode and drain electrode uses the wet etching that utilizes etching liquid.In recent years, along with the miniaturization of dimension of picture, utilize the composition (patterning) of the dry etching that uses etching gas increasing.But,, can produce following problem in that source electrode and drain electrode are used under the situation of the metal film that is carried out etching by the halogen gas that contains chlorine atom or fluorine atom (halogen gas).When carrying out the etching of source electrode and drain electrode, in the halogen gas that contains chlorine atom or fluorine atom, with the selection of the etching of the semiconductor layer of substrate than very poor.Therefore, with semiconductor layer over etching (over etching) to the part that forms raceway groove.Therefore, the raceway groove in the semiconductor layer digs quantitative change and gets inhomogeneously, produces the electrical characteristics problem of unstable of TFT.Therefore, can not hold ground and easily use dry etching, hinder the miniaturization of dimension of picture.
In order to address this problem, the situation that the etching stopping film that utilizes oxide-film is set is arranged also on the semiconductor layer as channel region.But, in this case, can increase lithography step one time, produce the not good problem of production efficiency once more.
Summary of the invention
The present invention is conceived to the problems referred to above, and its purpose is to provide a kind of have tft array substrate, its manufacture method of good characteristic and the display unit of using this substrate.
The tft array substrate of first execution mode of the present invention is the tft array substrate with the channel region that is configured between source region and the drain region, it comprises the gate electrode that is formed on the substrate, the gate insulating film that forms in the mode that covers described gate electrode, be arranged on semiconductor layer on the described gate electrode across described gate insulating film, source electrode with the metal film on the source region that is arranged on described semiconductor layer, drain electrode with the metal film on the drain region that is arranged on described semiconductor layer, and being configured between described source electrode and the source region and the nesa coating between described drain electrode and the drain region, the section of the part of exposing from the described nesa coating of described semiconductor layer is positive conical in shape.
The manufacture method of the tft array substrate of second execution mode of the present invention is the manufacture method with tft array substrate of the channel region that is configured between source region and the drain region, and this method comprises the steps: to form gate electrode on substrate; On described gate electrode, form gate insulating film, semiconductor layer and nesa coating continuously; Use the first photoresist figure that is formed on the described nesa coating that this nesa coating etching is island; Use the lamination mask of described first photoresist figure and described nesa coating, the described semiconductor layer of etching; Remove the described first photoresist figure and comprising form metal film on the substrate of described nesa coating after, use the second photoresist figure that this metal film is carried out dry etching, on this nesa coating, form source electrode and drain electrode; Described nesa coating on the channel region that is formed on described semiconductor layer is carried out etching; Form channel region.
According to the present invention,, can provide a kind of have tft array substrate, its manufacture method of good characteristic and the display unit of using this substrate according to aforesaid structure.
Description of drawings
Fig. 1 is the plane graph of structure of the tft array substrate of expression execution mode 1.
Fig. 2 is the manufacturing step profile of the tft array substrate of execution mode 1.
Fig. 3 is the profile of the conical in shape of expression semiconductor layer of the present invention.
Fig. 4 is the manufacturing step profile of the tft array substrate of execution mode 2.
Fig. 5 is the manufacturing step profile of the tft array substrate of execution mode 3.
Fig. 6 is the profile of the tft array substrate of prior art.
Embodiment
Below preferred implementation of the present invention will be described.In order to make the explanation clear, suitably following record and accompanying drawing are omitted and simplify.In addition, in order to make the explanation clear, omitted repeat specification as required.
Execution mode 1
At first, use Fig. 1 that the display unit of using tft array substrate of the present invention is described.Fig. 1 is the front elevation that is illustrated in the structure of employed tft array substrate in the display unit.(flat panel display) is that example illustrates display unit of the present invention with flat displays such as liquid crystal indicator or organic EL display (flat-panel monitor).The overall structure of this tft array substrate is identical in the execution mode 1～3 of the following stated.
Liquid crystal indicator of the present invention has substrate 1.Substrate 1 for example is the tft array substrate.The frame area 110 that in substrate 1, is provided with viewing area 111 and is provided with in mode around viewing area 111.In this viewing area 111, be formed with a plurality of grid wirings (scan signal line) 113 and a plurality of source wiring (display signal line) 114.A plurality of grid wirings 113 are set abreast.Similarly, a plurality of source wiring 114 also are set abreast.Form grid wiring 113 and source wiring 114 in mode intersected with each other.Grid wiring 113 and source wiring 114 quadratures.And, become pixel 117 by the grid wiring 113 and source wiring 114 area surrounded of adjacency.Therefore, in substrate 1, pixel 117 is arranged in rectangular.
And, in the frame area 110 of substrate 1, scan signal drive circuit 115 and shows signal drive circuit 116 are set.111 extensions are set to frame area 110 to grid wiring 113 from the viewing area.And grid wiring 113 is connected with scan signal drive circuit 115 in the end of substrate 1.Similarly, also 111 extensions are set to frame area 110 to source wiring 114 from the viewing area.And source wiring 114 is connected with shows signal drive circuit 116 in the end of substrate 1.Near scan signal drive circuit 115, connect outside wiring 118.In addition, near shows signal drive circuit 116, connect outside wiring 119.Outside wiring 118,119 for example is FPC (Flexible Printed Circuit: flexible printed circuit) wait the substrate that connects up.
Provide various signals by outside wiring 118,119 to scan signal drive circuit 115 and shows signal drive circuit 116 from the outside.Scan signal drive circuit 115 offers grid wiring 113 according to the control signal from the outside with signal (sweep signal).Select grid wiring 113 successively according to this signal.Shows signal drive circuit 116 offers source wiring 114 according to control signal or the video data from the outside with shows signal.Thus, the display voltage corresponding with video data can be offered each pixel 117.And scan signal drive circuit 115 and shows signal drive circuit 116 are not limited to be configured in the structure on the substrate 1.For example, also can connect drive circuit by TCP (Tape Carrier Package: band carries encapsulation).
In pixel 117, form a TFT120 at least.TFT120 is configured near the crosspoint of source wiring 114 and grid wiring 113.TFT120 has the channel region that is configured between source region and the drain region.For example, this TFT120 provides display voltage to pixel electrode.That is, according to signal, as the TFT120 conducting (ON) of switch element from grid wiring 113.Thus, apply display voltage from 114 pairs of pixel electrodes that are connected with the drain electrode of TFT120 of source wiring.And, between pixel electrode and opposite electrode, produce the electric field corresponding with display voltage.And, form alignment films (not shown) on the surface of substrate 1.
And, in substrate 1, dispose opposed substrate opposed to each other.For example, opposed substrate is the colour filter substrate, is configured in visible side.On opposed substrate, form colour filter (color filter), black matrix (black matrix) (BM), opposite electrode and alignment films etc.And, also exist opposite electrode to be configured in the situation of substrate 1 side.And, clamping liquid crystal layer between substrate 1 and opposed substrate.That is, between substrate 1 and opposed substrate, inject liquid crystal.And, on the face in the outside of substrate 1 and opposed substrate, Polarizer and polarizer etc. are set.In addition, the opposition side in the visible side of display panels (panel) is provided with back light unit (back light unit) etc.
By the electric field driven liquid crystal between pixel electrode and the opposite electrode.That is, the direction of orientation of the liquid crystal between substrate changes.Thus, the polarized state of light by liquid crystal layer changes.That is, for the light that becomes rectilinearly polarized light by Polarizer, polarization state changes because of liquid crystal layer.Specifically, become rectilinearly polarized light from the light of back light unit by the Polarizer of array substrate side.And this rectilinearly polarized light is by liquid crystal layer, and thus, polarization state changes.
Therefore, the light quantity of the Polarizer by the opposed substrate side changes according to polarization state.That is, see through the light quantity change of the light of Polarizer the transmitted light of display panels, that pass through visible side from back light unit.The direction of orientation of liquid crystal changes according to the display voltage that is applied.Therefore, the control display voltage thus, makes the light quantity change by the Polarizer of visible side.That is, change display voltage, thus, can show desirable image according to each pixel.
In the present invention, the tft array substrate of described substrate 1 as the bottom gate type structure of using in liquid crystal indicator is illustrated.And, use the display unit of tft array substrate to be not limited to liquid crystal indicator, also can be OLED display etc.Describe with reference to the tft array substrate of accompanying drawing execution mode 1.Fig. 2 (a)～(e) is the profile of step of manufacturing of the tft array substrate of expression execution mode 1.
At first, on substrate 1, form the Cr film as thickness with 200nm by sputter (sputtering) rule.And, on the Cr film, form resist film.In first lithography step, form gate electrode figure, use ammonium ceric nitrate (cerium ammonium) aqueous solution to carry out etching.Form gate electrode 2 by above step.And this gate electrode 2 for example extends from as shown in Figure 1 grid wiring 113.Substrate 1 is formed by insulating material such as glass.Gate electrode 2 is not limited to the Cr film, can use other metals that can be used for the tft array substrate.In addition, the thickness of gate electrode 2 also is not limited to 200nm.Equally, be under the situation of Cr film at gate electrode 2, in the ammonium ceric nitrate aqueous solution, carry out etching, still, under the situation of using Cr metal in addition, use and the corresponding etching liquid of this metal.
Secondly, by plasma (plasma) CVD method, form the thick gate insulating film of 400nm 3, the active film 4 of semiconductor that 200nm is thick, the ohmic contact film 5 that 50nm is thick continuously in the mode of covering grid electrode 2.Gate insulating film 3 is for example formed by the SiN film.The active film 4 of semiconductor is by the film formed raceway groove film of a-Si.In order to obtain the ohmic contact of active film 4 of semiconductor and upper metal, ohmic contact film 5 is the n type a-Si films that are doped with phosphorus.Form semiconductor regions by active film 4 of this semiconductor and ohmic contact film 5, these two is called semiconductor layer altogether.After forming gate insulating film 3, the active film 4 of semiconductor and ohmic contact film 5 continuously, form first nesa coating 10 with the thickness of 100nm by sputtering method.
Like this, first nesa coating 10 is formed continuously with gate insulating film 3, the active film 4 of semiconductor and ohmic contact film 5, this is one of feature of execution mode 1.Its effect is described later on.In addition, it is important that first nesa coating 10 uses following material, is difficult to etch material in the halogen gas that contains chlorine atom or fluorine atom that is:.For example, preferred ITO (the Indium Tin Oxide: film indium tin oxide) that uses as the oxide of indium and tin.Its effect is also described later on.And described various thickness are exemplary thickness, can certainly use other thickness.
Secondly, on first nesa coating 10, apply resist film, and expose, develop.Thus, form the first photoresist figure 11, become the structure shown in Fig. 2 (a).As described below, because the active film 4 of semiconductor, ohmic contact film 5 and first nesa coating 10 are carried out composition, so, the first photoresist figure 11 is formed island.In addition, form the first photoresist figure 11 in the mode of exposing from a side of the figure of gate electrode 2.
In second lithography step, carry out etching across 11 pairs first nesa coatings of the first photoresist figure 10.For example utilize the wet etching that has used oxalic acid herein.Thus, first nesa coating 10 is carried out composition.Therefore, become the structure shown in Fig. 2 (b).Herein, the laminated construction of first nesa coating 10 and the first photoresist figure 11 becomes the mask when the active film 4 of semiconductor and ohmic contact film 5 carried out etching.That is, on active film 4 of semiconductor and ohmic contact film 5, form the island figure of the lamination mask that constitutes by first nesa coating 10 and the first photoresist figure 11.At this moment, the end of first nesa coating 10 is etched in the end that retreats into the first photoresist figure 11.Therefore, form the first photoresist figure 11 in the mode that becomes the eaves shape with respect to first nesa coating.That is,, the end of first nesa coating 10 is formed on the inboard of the end of the first photoresist figure 11 by side etching (side etching).In other words, the figure of first nesa coating 10 is than the little corresponding side of the figure etch amount of the first photoresist figure 11.Therefore, the figure of first nesa coating 10 forms the structure in the figure that is included in the first photoresist figure 11.
Secondly, utilize the lamination mask pattern of first nesa coating 10 and the first photoresist figure 11, ohmic contact film 5 and the active film 4 of semiconductor are carried out etching.Thus, the structure of formation shown in Fig. 2 (c).Then, remove the first photoresist figure 11.Implementing to use for example SF herein,
6Under the situation of the dry etching of the mist of HCl, can form the island figure of active film 4 of the semiconductor with the positive conical in shape that more relaxes than first nesa coating 10 and ohmic contact film 5.Use Fig. 3 that the reason of the island figure that can form positive taper is described.
Fig. 3 is the amplification profile of the end of the active film 4 of the semiconductor shown in Fig. 2 (c), ohmic contact film 5, first nesa coating 10 and the first photoresist figure 11.Herein, with the laminated construction of active film 4 of semiconductor and ohmic contact film 5 as semiconductor layer 30.For the first photoresist figure 11 is carried out the end of first nesa coating 10 after the etching as mask, forming width by the side etching is the space of X.Herein, X is the side etch amount of expression apart from the amount of retreating of the end of the first photoresist figure 11.Like this, the eaves of the first photoresist figure 11 parts under be the space.
Under the situation of using the lamination mask pattern etching semiconductor layer 30 that is made of the first photoresist figure 11 and first nesa coating 10, etching gas enters this space.By entering etching gas in the space when laterally etching being carried out successively in the side of semiconductor layer 30, also carry out etching at film thickness direction in the exterior lateral area of side.Therefore, forming the island figure of semiconductor layer 30, and, according to side etch amount X the side of semiconductor layer 30 is formed positive taper.And, be under the situation of Y in the gross thickness of active film 4 of semiconductor as shown in Figure 3 and ohmic contact film 5, by adjusting the side etch amount X of first nesa coating 10, can be by formula 1 control taper angle theta.Formula 1 below is shown.Herein, feature is that the section shape of the semiconductor layer 30 that is made of ohmic contact film 5 and the active film 4 of semiconductor is positive taper.
X=Y/tan θ ... (formula 1)
Like this, because use the lamination mask comprise first nesa coating 10, so, semiconductor layer 30 is patterned into the shape roughly the same with first nesa coating 10.That is, the profile end of the figure of semiconductor layer 30 is roughly consistent with first nesa coating 10.But,, form the figure of semiconductor layer 30 in the mode of exposing slightly from first nesa coating 10 owing on first nesa coating 10, form the first photoresist figure 11 of eaves shape.And in this part of exposing, the section of semiconductor layer 30 becomes positive cone shape shape because of the etching gas that enters eaves space partly.In addition, the amount of exposing of semiconductor layer 30 is based on the amount of the eaves shape of the first photoresist figure 11.Herein, the position consistency of the following figure end of the figure end above the semiconductor layer 30 and first nesa coating 10.
Turn back to the explanation of Fig. 2 herein.In Fig. 2 (d), behind the etching semiconductor layer 30, on first nesa coating 10, form source electrode 6 and drain electrode 7.Herein, the material of source electrode 6 and drain electrode 7 for example uses Mo.And this source electrode 6 is for example extended by source wiring shown in Figure 1 114.At first, on the substrate 1 after removing the first photoresist figure 11,, form the thick Mo film of 200nm by sputtering method.And, in the 3rd lithography step, be formed for forming the second photoresist figure 12 of source electrode 6 and drain electrode 7.That is, on metal film, the coating resist film, and expose, develop.Herein, shown in Fig. 2 (d), the second photoresist figure 12 is formed on the source region 41 and drain region 42 of the active film 4 of semiconductor.That is, the mode of exposing with first nesa coating 10 on the channel region 43 forms the second photoresist figure 12.And source region 41 and drain region 42 are parts of the active film 4 of semiconductor, and expression is formed on the diffusion zone at the two ends of channel region 43.Source region 41 is formed on the bottom of source electrode 6, and drain region 42 is formed on the bottom of drain electrode 7.
And, for example use SF
6Mist, with dry etching the Mo film is carried out etching.As first nesa coating 10, use halogen gas to be difficult to etch material as mentioned above to contain fluorine class atom.Therefore, first nesa coating 10 becomes at SF
6The etching stopping film of mist.Therefore, can protect etching at channel region 43 and ohmic contact film 5.Thus, form the structure shown in Fig. 2 (d).Then, remove first nesa coating 10 on the top that is formed on channel region 43.Can utilize the wet etching that has used oxalic acid herein.And,, remove the ohmic contact film 5 on the top that is formed on channel region 43 by using the dry etching of HCl gas.Like this, can remove first nesa coating 10 and ohmic contact film 5 between source electrode 6 and drain electrode 7.Thus, the active film 4 of semiconductor exposes, and forms channel region 43 between source region 41 and drain region 42.Source electrode 6 is connected with source region 41 by first nesa coating 10.In addition, drain electrode 7 is connected with source region 42 by first nesa coating 10.
And employed material is not limited to Mo in source electrode 6 and the drain electrode 7, also can use the alloy as main component with Mo.Equally, also can use Ti and Ta or with they alloys as main component.And, also can use Al or with the alloy of Al as main component.So long as can then be not limited to above-mentioned metal by the metal of the etching gas etching that contains chlorine atom or fluorine class atom.Therefore, so long as to contain Al, Ti, Ta, Mo be that the metal film of main component gets final product.Thus, can carry out etching processing at an easy rate.Source electrode 6 and drain electrode 7 also can be the laminated construction of metal film.In addition, about etching gas,, be not limited to SF so long as contain the etching gas of chlorine atom or fluorine class atom at source electrode 6 and drain electrode 7
6Mist, can use other etching gas.
Then, form SiN film 8 by the CVD method with the thickness of 300nm as passivating film.Afterwards, in the 4th lithography step, form contact hole graph.For example, by having used CF
4The dry etching of mist SiN film 8 is carried out etching, form contact hole 13.The formation method and the etching gas of the material of passivating film and thickness, contact hole 13 are exemplary, can certainly be employed additive method, material and structures in the tft array substrate.
At last,, form second nesa coating 9, form pixel electrode with the thickness of 100nm by sputtering method.For example, form second nesa coating 9 by ITO as the oxide of indium and tin.And second nesa coating 9 also can use and first nesa coating, 10 identical materials.By the 5th lithography step, on second nesa coating 9, form the pixel electrode figure, form pixel electrode by the etching of having used oxalic acid (oxalic acid).Thus, form the structure shown in Fig. 2 (e).By above-mentioned method, finish the tft array substrate of execution mode 1.
As mentioned above, as first nesa coating 10, use to be difficult to etch material by the halogen gas that contains chlorine atom or fluorine atom.Therefore, when source electrode 6 and drain electrode 7 were carried out dry etching, first nesa coating 10 became etching stopping (etch stopper) film at active film 4 of semiconductor and ohmic contact film 5.That is, the metal film that need carry out etching by the halogen gas that contains chlorine atom or fluorine atom can keep the etching selection ratio with active film 4 of semiconductor and ohmic contact film 5 during as source electrode 6 and drain electrode 7.Therefore, can seek the stabilisation of the raceway groove amount of digging.Consequently, can form the tft array substrate of characteristic good.Can form trickle figure by dry etching to processing by source electrode 6 and drain electrode 7 that the halogen gas that contains chlorine atom or fluorine atom carries out etching.
In addition, first nesa coating 10 forms continuously with active film 4 of semiconductor and ohmic contact film 5, and forms figure in identical lithography step.Therefore, be not required to be to form and increased lithography step as first nesa coating 10 of etching stopping film.For the manufacture method of the tft array substrate of the manner, lithography step is five times, and is identical with prior art (patent documentation 1).Therefore, do not increase number of manufacture steps and just can form the etching stopping film.Thus, productivity ratio is descended, and can make tft array substrate with stability characteristic (quality).
In addition, first nesa coating 10 also becomes the stopper film that is used for preventing source electrode 6 and drain electrode 7 active films 4 of employed metallic pollution (contamination) semiconductor and ohmic contact film 5.Therefore, can make tft array substrate with good TFT characteristic and higher reliability.
In addition, in execution mode 1, in the formed tft array substrate, can form the active film 4 of semiconductor and the ohmic contact film 5 of positive conical in shape with desirable angle.Consequently, can carry out the covering (coverage) of source electrode 6 and drain electrode 7 well, and can improve connectivity.In addition, as source electrode 6 and drain electrode 7, also can use Al or with the alloy of Al as main component.Consequently, except the low resistanceization of contact, also can realize the low resistance wiring.
And, in execution mode 1, after active film 4 and ohmic contact film 5 form continuously with semiconductor, carry out composition at first nesa coating 10.Afterwards, form metal film conduct one deck down, form the figure of source electrode 6 and drain electrode 7.That is, because first nesa coating 10 is different period with the formation of source electrode 6 and drain electrode 7, so, can change the formation zone of first nesa coating 10 and source electrode 6 and drain electrode 7.That is, in different lithography steps, first nesa coating 10 and source electrode 6 and drain electrode 7 are carried out composition.This is and the different feature of the present invention of prior art (patent documentation 2).Thus, first nesa coating 10 can be made different graphics shapes with source electrode 6 and drain electrode 7.
Describe with reference to the tft array substrate of accompanying drawing execution mode 2.For execution mode 2, the technology that relates to tft array substrate and manufacture method thereof is identical with first execution mode.And, the explanation of omitting structural element, function and the manufacturing step identical with first execution mode.
Use Fig. 4 that the tft array substrate of execution mode 2 is described.Fig. 4 is the profile of a part of manufacturing step of the tft array substrate of expression execution mode 2.For the manufacturing step of the tft array substrate of execution mode 2, identical with execution mode 1 before to Fig. 2 (a)～(d).In execution mode 2, the Fig. 2 (e) shown in the step alternate embodiments 1 of use Fig. 4.In execution mode 2, feature is the cross-section structure of tft array substrate shown in Figure 4.
In Fig. 4, pixel electrode directly is connected with first nesa coating 10 under the drain electrode 7.Because identical with Fig. 2 (a)～(d) to formation source electrode 6 with drain electrode 7 step before, so, its explanation omitted.At Fig. 2 (d) afterwards, form SiN film 8 by the CVD method with 300nm thickness as passivating film.So far, identical with execution mode 1.Afterwards, in the 4th lithography step, form contact hole graph.For example, utilize the dry etching of the mist used CF4, the Mo film that becomes drain electrode 7 of SiN film 8 and lower floor thereof is carried out etching.Thus, form contact hole 15.And, about the number of times of lithography step, be the number of times that begins to calculate from the beginning step that forms gate electrode 2 at the substrate shown in Fig. 2 (a) 1.
Herein, the feature of execution mode 2 is, not only makes contact hole 15 connect SiN films 8, and connects the drain electrode 7 that is made of the Mo film of its lower floor, arrives first nesa coating 10.That is, formation has after the SiN film 8 of contact hole 15, and the through hole that arrives first nesa coating 10 is set on drain electrode 7.In order to form through hole by contact hole 15, the position of through hole is consistent with the contact hole 15 of SiN film 8.And, be exemplary as the formation method and the etching gas of the material of the SiN film 8 of passivating film and thickness, contact hole 13, can certainly adopt additive method, material and the structure in TFT, used.
At last,, form second nesa coating 14, form pixel electrode with the thickness of 100nm by sputtering method.Second nesa coating 14 is for example formed by the ITO as the oxide of indium and tin.Second nesa coating 14 is embedded in the contact hole 15.Thus, second nesa coating 14 that becomes pixel electrode contacts with first nesa coating 10.And in execution mode 2, employed second nesa coating 14 of preferred pixel electrode and first nesa coating 10 use identical materials.And,, on second nesa coating 14, form the pixel electrode figure by the 5th lithography step.Utilize the etching of having used oxalic acid to form pixel electrode herein.By said method, finish the tft array substrate of execution mode 2.
As mentioned above, in execution mode 2, directly be connected with first nesa coating 10 as second nesa coating 14 of pixel electrode.Herein, second nesa coating 14 as the material of pixel electrode is identical with the material of first nesa coating 10.Therefore, can seek the low resistanceization that contacts.That is, on the side of small contact hole 15 and bottom surface, second nesa coating 14 as pixel electrode is connected with drain electrode 7.Thus, a side resistance value step-down that directly contacts with first nesa coating 10.And first nesa coating 10 is connected in wide region with upper strata drain electrode 7.Therefore, consequently, the contact resistance of second nesa coating 14 and drain electrode 7 improves.In addition, in the bottom of contact hole 15, bury second nesa coating 14 in the through hole on being arranged on drain electrode 7 underground.Therefore, in through hole, the contacts side surfaces of second nesa coating 14 and drain electrode 7.
As mentioned above, for the tft array substrate that has used execution mode 2, the effect in execution mode 1, can also utilize the raising of the low resistance realization electrical characteristics of contact.And the number of times of the lithography step of execution mode 2 is identical with the number of steps of execution mode 1.That is, do not increase lithography step and just can realize the low resistanceization that contacts.
Herein, identical with execution mode 1, with the resist pattern different source electrode 6 and drain electrode 7 are carried out etching with first nesa coating 10.Therefore, first nesa coating 10 is different with the formation zone of source electrode 6 and drain electrode 7, and the part of source electrode 6 is to form with mode that gate insulating film 3 directly contacts.This is because first nesa coating 10 is different period with the formation of source electrode 6 and drain electrode 7.In addition, source electrode 6 and drain electrode 7 also can use Al or with the alloy of Al as main component.Consequently, except the low resistanceization of contact, can also realize the low resistance wiring.
Execution mode 3
Describe with reference to the tft array substrate of accompanying drawing execution mode 3.For execution mode 3, the technology that relates to tft array substrate and manufacture method thereof is also identical with first execution mode.And, the explanation of omitting structural element, function and the manufacturing step identical with first execution mode.
Use Fig. 5 that execution mode 3 is described.Fig. 5 is the profile of a part of manufacturing step of the tft array substrate of expression execution mode 3.For the manufacturing step of the tft array substrate of execution mode 3, identical with execution mode 1 before to Fig. 2 (a)～(c).In execution mode 3, use step alternate figures 2 (d) step afterwards of Fig. 5.In execution mode 3, feature is the manufacturing step and the cross-section structure of tft array substrate shown in Figure 5.
Use Fig. 5 that the manufacture method that forms source electrode 6 and drain electrode 7 tft array substrate is afterwards described.Step before this is because identical with Fig. 2 (a)～(c), so, omit its explanation.From the state of Fig. 2 (c), form the Mo film by sputtering method thickness with 200nm on the substrate 1 of removing the first photoresist figure 11.And, in the 3rd lithography step, be formed for forming the second photoresist figure 12 of source electrode 6 and drain electrode 7.About the number of times of lithography step, be the number of times that begins to calculate from the beginning step that forms gate electrode 2 at the substrate shown in Fig. 2 (a) 1.All identical before this with execution mode 1.
Herein, technology (for example to use two stages exposures (2 Duan Bands exposure), intermediate tone mask (half-tone mask) or gray tone mask (gray-tone mask) etc.) carry out composition, so that other zones of the Film Thickness Ratio second photoresist figure 12 of the part of the second photoresist figure 12 on the drain electrode 7 (being called photoresist figure 121) are thin.That is, by the exposure of two stages, the thickness that makes the second photoresist figure 12 is two steps.And for example using, the mist of SF6 carries out etching by dry etching to the Mo film.10 uses are difficult to etch material as mentioned above in the halogen gas that contains fluorine class atom for first nesa coating.Therefore, first nesa coating 10 becomes the etching stopping film.Therefore, in channel region, can protect etching at active film 4 of semiconductor and ohmic contact film 5.Thus, form the structure shown in Fig. 5 (a).
Then, first nesa coating 10 on the top that is formed on the active film 4 of semiconductor is carried out etching, remove photoresist figure 121.At first, use oxalic acid to remove first nesa coating 10 that is formed on as the top of the active film 4 of the semiconductor of channel region.And, by having used the dry etching of HCl gas, removed the ohmic contact film 5 on the top that is formed on the active film 4 of semiconductor, and, the TFT channel region formed.Afterwards, remove photoresist figure 121 by ashing (ashing).That is, by half ashing, with 12 attenuation of the second photoresist figure.Thus, the second thin photoresist figure 121 is fully removed, and exposes the Mo film.On the other hand, in the thicker part of the second photoresist figure 12, the second photoresist figure 12 is not removed fully, but attenuation.For example, the second photoresist figure 12 on the source electrode 6 is residual with the state after the attenuation.Thus, form the structure shown in Fig. 5 (b).
Then, drain electrode 7 is carried out removing the second photoresist figure 12 after the etching.At first, by etching, remove the drain electrode 7 in the zone after photoresist figure 121 is removed.Thus, remove the part of drain electrode 7.Therefore, on a part of drain region 42, remove drain electrode 7, the first nesa coatings 10 and expose.In etching, utilize the wet etching of the mixed liquor that has for example used phosphoric acid and nitric acid.Afterwards, remove the second photoresist figure 12.Thus, form the structure shown in Fig. 5 (c).As mentioned above, by forming the thin photoresist figure 121 of thickness, the part that can remove drain electrode 7.And, can not increase lithography step by using said method.
Herein, with execution mode 1 in the same manner, with the resist pattern different source electrode 6 and drain electrode 7 are carried out etching with first nesa coating 10.Therefore, first nesa coating 10 is different with the formation zone of source electrode 6 and drain electrode 7, and the part of source electrode 6 is to form with mode that gate insulating film 3 directly contacts.This is because first nesa coating 10 is different period with the formation of source electrode 6 and drain electrode 7.
Then, form SiN film 8, drain electrode 7 is connected with pixel electrode with contact hole.This step below is described in detail in detail.In execution mode 3, contact hole 16 is formed on the zone of removing behind the drain electrode 7.That is, execution mode 3 has following feature: pixel electrode directly is not connected with drain electrode 7, but connects by nesa coating 10.
At first, form SiN film 8 by the CVD method with the thickness of 300nm as passivating film.Afterwards, in the 4th lithography step, form contact hole graph.For example, by having used CF
4The dry etching of mist SiN film 8 is carried out etching, form contact hole 16.Contact hole 16 is formed on the zone of removing behind the drain electrode 7.That is, around contact hole 16, locate, remove drain electrode 7.Herein, in execution mode 3, as enforcement mode 2, not by contact hole etching Mo film.Therefore, has the effect that is easy to fine form contact hole 16.That is,, also can connect reliably making under the less situation of contact hole 16.The formation method and the etching gas of the material of passivating film and film thickness, contact hole 16 are exemplary, can certainly be additive method, material and the structures of using in the tft array substrate.
At last,, form second nesa coating 17, form pixel electrode with the thickness of 100nm by sputtering method.Second nesa coating 17 is for example formed by the ITO as the oxide of indium and tin.And identical with execution mode 2 in execution mode 3, second nesa coating 17 and first nesa coating 10 that are preferred for pixel electrode use identical materials.On second nesa coating 17, form the pixel electrode figure by the 5th lithography step, form pixel electrode by the etching of having used oxalic acid.By above-mentioned method, finish the tft array substrate of execution mode 3.
Like this, in execution mode 3, on the Mo film, form the second photoresist figure 12 by the exposure of two stages.Herein, for the second photoresist figure 12, in the contact hole portion thickness attenuation of the contact hole 16 that forms SiN film 8.That is, compare, form the second thin photoresist figure 121 of thickness in contact hole portion than its elsewhere.And, carry out dry etching across 12 pairs of Mo films of the second photoresist figure.Form the figure of source electrode 6 herein.After the dry etching, the part of the second photoresist figure 12 is carried out ashing.Thus, remove the second thin photoresist figure 121 of thickness.Therefore, the Mo film after dry etching exposes in contact hole portion.And, the Mo film is carried out etching, first nesa coating 10 is exposed.Thus, the part on drain region 42 is carried out etching to the Mo film, forms the figure of drain electrode 7.
As mentioned above, in execution mode 3, drain electrode 7 directly is not connected with second nesa coating 17 as pixel electrode, but connects by first nesa coating 10.But second nesa coating 17 is identical with the material of first nesa coating 10, and first nesa coating 10 is connected with the drain electrode 7 that is formed on the upper strata on wide region.Therefore, identical with execution mode 2, even second nesa coating 17 directly is not connected with drain electrode 7, also can seek the low resistanceization that contacts.
And, in execution mode 3, when forming contact hole 16, do not need etching drain electrode 7.Therefore, can access the effect that can form contact hole imperceptibly.That is, have in formation before the SiN film 8 of contact hole 16, the part of etching drain electrode 7 is exposed first nesa coating 10.The number of times of the lithography step of execution mode 3 is identical with the number of steps of first and second execution mode.That is, do not increase lithography step and just can realize the low resistanceization that contacts, and can carry out microfabrication contact hole.
Herein, first nesa coating 10 is different with the formation zone of source electrode 6 and drain electrode 7.These are different with described prior art (patent documentation 2), and this is because the formation of source electrode 6 and drain electrode 7 is different with first nesa coating 10 period.Therefore, first nesa coating 10 is different with the formation zone of source electrode 6 and drain electrode 7, and the part of source electrode 6 is to form with mode that gate insulating film 3 directly contacts.
And source electrode 6 and drain electrode 7 also can use Al and with the alloy of Al as main component.Consequently, except the low resistanceization of contact, can also realize the low resistance wiring.
And, the invention is not restricted to described each execution mode.Within the scope of the invention, each key element of described execution mode can be changed, append, be transformed in the content that those skilled in the art expect easily.
Claims (16)
1. a tft array substrate has the channel region that is configured between source region and the drain region, it is characterized in that:
Comprise: be formed on the gate electrode on the substrate; The gate insulating film that forms in the mode that covers described gate electrode; Be arranged on semiconductor layer on the described gate electrode across described gate insulating film; Source electrode with the metal film on the source region that is arranged on described semiconductor layer; Drain electrode with the metal film on the drain region that is arranged on described semiconductor layer; Be configured between described source electrode and the source region and the nesa coating between described drain electrode and the drain region,
The section of the part of exposing from described nesa coating of described semiconductor layer is positive conical in shape.
2. tft array substrate as claimed in claim 1 is characterized in that:
On the passivating film that forms in the mode that covers on the described substrate, also has the pixel electrode that is connected with described drain electrode.
3. tft array substrate as claimed in claim 2 is characterized in that:
By the part that the contact hole that is arranged on the described passivating film is removed described drain electrode, described pixel electrode directly is connected with described nesa coating.
4. as the tft array substrate of claim 2 or 3, it is characterized in that,
Described pixel electrode and described nesa coating are identical materials.
5. as claim 1,2 or 3 tft array substrate, it is characterized in that,
Described semiconductor layer is an amorphous silicon.
6. as claim 1,2 or 3 tft array substrate, it is characterized in that:
Described source electrode and drain electrode contain Ti, Ta, Mo, Al and are alloy at least a of main component with these metals.
7. display unit is characterized in that:
Use as claim 1,2 or 3 tft array substrate.
8. the manufacture method of a tft array substrate, this tft array substrate has the channel region that is configured between source region and the drain region, and this method comprises the steps:
On substrate, form gate electrode;
On described gate electrode, form gate insulating film, semiconductor layer and nesa coating continuously;
Use the first photoresist figure that is formed on the described nesa coating that this nesa coating etching is island;
Use the lamination mask of described first photoresist figure and described nesa coating that described semiconductor layer is carried out etching;
Remove the described first photoresist figure and comprising form metal film on the substrate of described nesa coating after, use the second photoresist figure that this metal film is carried out dry etching, on this nesa coating, form source electrode and drain electrode;
Described nesa coating on the channel region that is formed on described semiconductor layer is carried out etching;
Form channel region.
9. the manufacture method of tft array substrate as claimed in claim 8 is characterized in that, also comprises the steps:
Form after the described channel region, on described substrate, form passivating film with contact hole;
Have on the passivating film of described contact hole, forming by this contact hole and the direct-connected pixel electrode of described nesa coating.
10. the manufacture method of tft array substrate as claimed in claim 9 is characterized in that:
When forming contact hole by dry etching, the metal film that formation is exposed to the drain electrode of described contact hole portion carries out etching and forms in the lump.
11. the manufacture method as the tft array substrate of claim 8 or 9 is characterized in that,
In the step that forms described source electrode and described drain electrode, comprise the steps:
On described metal film, form the second resist figure by the exposure of two stages, this second resist figure is in the thickness attenuation of contact hole portion, and this contact hole portion is the part that forms contact hole on described passivating film;
Across the described metal film of the described second photoresist pattern etching;
The described nesa coating that is formed on the channel region is carried out etching;
Part to the described second photoresist figure is carried out ashing, and described metal film is exposed in described contact hole portion;
The described metal film that exposes of etching exposes the described nesa coating of described contact hole portion;
Form channel region.
12. the manufacture method of tft array substrate as claimed in claim 9 is characterized in that:
Described pixel electrode and described nesa coating use identical materials.
13. the manufacture method as claim 8,9 or 10 tft array substrate is characterized in that:
Described semiconductor layer is an amorphous silicon,
The dry etching of the gas by having chloride or fluorine or use the wet etching of etching liquid to carry out etching with hydrofluoric acid.
14. the manufacture method as claim 8,9 or 10 tft array substrate is characterized in that:
Described source electrode and drain electrode contain Ti, Ta, Mo, Al and with at least a as in the alloy of main component of these metals.
15. the manufacture method as claim 8,9 or 10 tft array substrate is characterized in that:
Described nesa coating is being carried out in the step of etching, is comparing the mode that retreats with the end of the described first photoresist figure with the end of described nesa coating and carry out the side etching,
Described semiconductor layer being carried out in the step of etching, is that the mode of positive taper is carried out etching with the section of described semiconductor layer.
16. the manufacture method as claim 8,9 or 10 tft array substrate is characterized in that:
Described metal film is being carried out in the etching gas of dry etching, using the gas that contains chlorine or fluorine.
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| JP2006159306 | 2006-06-08 | ||
| JP2006159306A JP5063936B2 (en) | 2006-06-08 | 2006-06-08 | Manufacturing method of TFT array substrate |
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| CN100539193C CN100539193C (en) | 2009-09-09 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194831A (en) * | 2010-03-16 | 2011-09-21 | 三星电子株式会社 | Oxide thin-film transistor (TFT) substrate |
| CN103309101A (en) * | 2012-03-12 | 2013-09-18 | 三菱电机株式会社 | Wiring structure, thin film transistor array substrate including the same, and display device |
| CN104716166A (en) * | 2015-03-18 | 2015-06-17 | 上海天马微电子有限公司 | Organic lighting display device and manufacturing method thereof |
| CN105895639A (en) * | 2016-06-29 | 2016-08-24 | 京东方科技集团股份有限公司 | Array substrate, fabrication method thereof and display device |
| WO2018094595A1 (en) * | 2016-11-23 | 2018-05-31 | 深圳市柔宇科技有限公司 | Manufacturing method of array substrate |
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| CN101685229B (en) * | 2008-09-25 | 2012-02-29 | 北京京东方光电科技有限公司 | Method for manufacturing array substrate of liquid crystal display device |
| US8664097B2 (en) | 2010-09-13 | 2014-03-04 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
| CN103341692A (en) * | 2013-06-26 | 2013-10-09 | 京东方科技集团股份有限公司 | Method for cutting irregular figure substrate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100233151B1 (en) * | 1997-04-03 | 1999-12-01 | 윤종용 | Fabrication method of thin film transistor panel |
| JP2968252B2 (en) * | 1998-04-06 | 1999-10-25 | 株式会社日立製作所 | Liquid crystal display |
| JP2000101091A (en) * | 1998-09-28 | 2000-04-07 | Sharp Corp | Thin film transistor |
| JP2005301255A (en) * | 2000-01-26 | 2005-10-27 | Sharp Corp | Liquid crystal display, wiring board and method for manufacturing these |
| KR100656910B1 (en) * | 2000-10-10 | 2006-12-12 | 삼성전자주식회사 | Thin film transistor and fabricating method thereof |
| KR100663294B1 (en) * | 2000-12-30 | 2007-01-02 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing thin film transistor liquid crystal display |
| JP4267242B2 (en) * | 2001-03-06 | 2009-05-27 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| US20040224241A1 (en) * | 2003-02-03 | 2004-11-11 | Samsung Electronics Co., Ltd. | Thin film transistor array panel, manufacturing method thereof, and mask therefor |
| JP2005302808A (en) * | 2004-04-07 | 2005-10-27 | Sharp Corp | Manufacturing method of thin film transistor array substrate |
-
2006
- 2006-06-08 JP JP2006159306A patent/JP5063936B2/en active Active
-
2007
- 2007-05-02 TW TW096115568A patent/TW200802892A/en unknown
- 2007-06-07 KR KR1020070055454A patent/KR100857481B1/en not_active IP Right Cessation
- 2007-06-08 CN CNB2007101102680A patent/CN100539193C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194831A (en) * | 2010-03-16 | 2011-09-21 | 三星电子株式会社 | Oxide thin-film transistor (TFT) substrate |
| CN102194831B (en) * | 2010-03-16 | 2015-09-09 | 三星显示有限公司 | Oxide thin film transistor substrate |
| CN103309101A (en) * | 2012-03-12 | 2013-09-18 | 三菱电机株式会社 | Wiring structure, thin film transistor array substrate including the same, and display device |
| CN103309101B (en) * | 2012-03-12 | 2016-08-10 | 三菱电机株式会社 | Wiring structure and possess its thin-film transistor array base-plate and display device |
| US9627585B2 (en) | 2012-03-12 | 2017-04-18 | Mitsubishi Electric Corporation | Wiring structure, thin film transistor array substrate including the same, and display device |
| CN104716166A (en) * | 2015-03-18 | 2015-06-17 | 上海天马微电子有限公司 | Organic lighting display device and manufacturing method thereof |
| CN105895639A (en) * | 2016-06-29 | 2016-08-24 | 京东方科技集团股份有限公司 | Array substrate, fabrication method thereof and display device |
| US10109653B2 (en) | 2016-06-29 | 2018-10-23 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method thereof and display device |
| WO2018094595A1 (en) * | 2016-11-23 | 2018-05-31 | 深圳市柔宇科技有限公司 | Manufacturing method of array substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007329298A (en) | 2007-12-20 |
| KR20070117485A (en) | 2007-12-12 |
| CN100539193C (en) | 2009-09-09 |
| KR100857481B1 (en) | 2008-09-08 |
| TW200802892A (en) | 2008-01-01 |
| JP5063936B2 (en) | 2012-10-31 |
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