JP2005302808A - Manufacturing method of thin film transistor array substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the manufacturing process of a TFT array substrate and reduce a manufacturing cost by more decreasing the number of times of a photolithography process than that of a conventional manufacturing method. <P>SOLUTION: A gate electrode 2c is formed in a first process. In a second process, a conductive film including a gate insulating film 3, a semiconductor film 4, and a transparent conductive film 5 is laminated on the gate electrode. After a resist layer is formed on the resulting laminate, a first opening 7c for exposing the conductive film to the resist layer at a predetermined position, and a second opening 7d having a predetermined thickness bottom at a position above the gate electrode 2c, are formed respectively to form a resist pattern. Further, the conductive film exposed from the first opening 7c and the semiconductor film located below the former are etched, and the bottom of the second opening 7d is removed to expose the conductive film, and further the conductive film is etched to form a TFT 8. In a third process, a protective layer 8 and a pixel electrode 5a are formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a thin film transistor array substrate constituting a liquid crystal display device.

  Liquid crystal display devices have advantages such as small size, thinness, low power consumption, and light weight, and are widely used in various electronic devices. In particular, an active matrix liquid crystal display device including a thin film transistor (TFT) as a switching element for each pixel has a display performance equivalent to that of a CRT. Therefore, it is suitable for OA equipment such as a personal computer, AV equipment such as a television, and a mobile phone. Widely applied. In particular, in recent years, quality improvements such as an increase in size, high definition, and high aperture ratio are rapidly progressing.

  As described above, in an active matrix liquid crystal display device in which the field of use is expanding, it is desired to reduce the price. In particular, various methods for reducing the manufacturing cost and reducing the cost by increasing the productivity of the TFT array substrate constituting the active matrix type liquid crystal display device have been studied, and among them, one step of the manufacturing process of the TFT array substrate. However, a method for reducing the number of photolithography processes using a photolithography method has been widely studied.

  Here, the photolithography step includes (1) a step of applying a resist on a substrate on which a thin film is formed, (2) a step of performing light exposure using a photomask to form a mask pattern latent image on the resist, This is a manufacturing process that is indispensable in the manufacturing process of the TFT array substrate, and includes a series of steps of 3) developing and patterning the resist and etching the thin film, and (4) removing the resist.

  For example, Patent Documents 1, 2, 3, and 4 disclose a method of manufacturing a transmissive TFT array substrate in which the number of photolithography processes is reduced to four.

  Patent Documents 5, 6, 7 and 8 disclose a method of manufacturing a transmissive TFT array substrate in which the number of photolithography processes is reduced to three.

  However, in Patent Documents 5, 6 and 8, there is no detailed explanation about the formation of the pixel electrode constituting the pixel or the external extraction electrode, and in consideration of the formation, at least one photolithography process is required. Therefore, the photolithography process is four times or more.

  Furthermore, Patent Document 7 discloses a method of manufacturing a top gate type TFT array, but the structure is such that the channel portion of the semiconductor layer constituting the TFT is shielded against light from the insulating substrate side. Therefore, there is a problem that the photo-induced leakage current flows and the on / off ratio (ratio of the on-state current to the off-state leakage current when the drain current is switched with the gate voltage) is deteriorated. .

  Further, in a conventional liquid crystal display device, a light shielding region called a black matrix made of chromium, black resin, or the like so as to overlap a TFT, a gate line, and a source line on a TFT array substrate on a counter substrate disposed to face the TFT array substrate. It is known that the TFT array substrate and the counter substrate are bonded together to prevent light from entering the TFT and suppress the generation of light-induced leakage current.

  However, in consideration of the overlapping margin when the TFT array substrate and the counter substrate are bonded, it is necessary to form a large light-shielding region, and there is a problem that the aperture ratio of the pixel is lowered.

  Therefore, in order to suppress a decrease in the aperture ratio of the pixel, a black matrix of the counter substrate is formed on the TFT array substrate by forming a light shielding film such as a black resist so as to cover the TFT, the gate line, and the source line. Attempts have been made to facilitate the superposition when the TFT array substrate and the counter substrate are bonded together.

  As a result, the number of photolithography processes required for the TFT array substrate manufacturing process is further increased by one in order to form the above-described light shielding film.

  As described above, in manufacturing the TFT array substrate constituting the transmissive liquid crystal display device, at least four photolithography processes are required.

  By the way, the transmissive liquid crystal display device is equipped with a backlight, and its power consumption accounts for 50% or more of the total power consumption. By providing the backlight, the total power consumption increases. End up. Therefore, a reflective liquid crystal display device that uses reflected light of ambient light and consumes less power has been developed. However, the reflection type liquid crystal display device also has a defect that the visibility is extremely low in an environment where the ambient light is dark, so that the function of displaying in both the transmission type and the reflection type is provided. A transflective liquid crystal display device is also widely used.

  As for the method of manufacturing the transflective liquid crystal display device, a method of reducing the number of times of the photolithography process has been studied, and disclosed in, for example, Patent Documents 9 and 10.

However, in the case of manufacturing a TFT array substrate constituting a transflective liquid crystal display device, a patterning process of the reflective electrode is separately performed in contrast to the four photolithography processes in the manufacturing method of the transmissive TFT array substrate. Since this is necessary, at least five photolithography steps are required.
JP-A-9-152626 Japanese Patent Laid-Open No. 9-236827 JP 2000-258799 A JP 2001-5038 A Japanese Patent Laid-Open No. 3-60042 JP-A-8-224004 JP 2001-188252 A JP 2002-343811 A Japanese Patent No. 3369502 JP 2003-195329 A

  As described above, four or more photolithography processes are required for manufacturing a transmissive TFT array substrate, and five or more photolithography processes are required for manufacturing a semi-transmissive TFT array substrate. Therefore, it is extremely difficult to reduce the number of processes.

  The present invention has been made in view of the above points, and the object of the present invention is to reduce the number of photolithography processes compared to the conventional manufacturing method, shorten the manufacturing process of the TFT array substrate, and reduce the manufacturing cost. Is to make it possible.

  In the present invention, the number of photolithography processes in the manufacturing process of the TFT array substrate is reduced to 3 times for the transmissive TFT array substrate and 4 times for the transflective TFT array substrate. .

  Specifically, the manufacturing method of the TFT array substrate of the present invention includes a plurality of pixels provided on the substrate, and arranged for each pixel, corresponding to the gate electrode, the source electrode, the drain electrode, and the gate electrode. A method of manufacturing a thin film transistor array substrate, comprising: a plurality of thin film transistors having a semiconductor film having a channel portion; a source line connected to the source electrode; and a pixel electrode connected to the drain electrode. A first step of patterning the gate electrode on a substrate by a photolithography method; and a transparent substrate provided on the substrate on which the gate electrode is formed so as to cover the gate insulating film, the semiconductor film, and the semiconductor film A conductive film including a conductive film is stacked in this order to form a stacked body, and the thin film transistor is formed on the stacked body by photolithography. Forming a protective layer covering the thin film transistor by photolithography, and forming a pixel electrode by exposing a part of the transparent conductive film. In the second step, after forming a resist layer covering the stacked body, a region of the stacked body with respect to the resist layer other than a portion that becomes the channel portion, the source line, the source electrode, and the drain electrode. A resist pattern forming step of forming a first opening for exposing the conductive film at an upper position and a second opening having a bottom with a predetermined thickness at a position above the region of the stacked body to be the channel section; A first etching step of etching the conductive film exposed from the first opening and a semiconductor film below the conductive film; and exposing the bottom of the second opening by removing the bottom. Characterized in that a second etching step of etching the conductive film in which.

  According to the above manufacturing method, first, in the first step, the gate electrode is patterned on the substrate.

  Next, in the second step, a gate insulating film, a semiconductor film, and a conductive film including a transparent conductive film provided to cover the semiconductor film are stacked in this order on the substrate on which the gate electrode is formed. And forming a resist layer covering the stacked body, and then, with respect to the resist layer, above the region of the stacked body other than the portion that becomes the channel portion, the source line, the source electrode, and the drain electrode A resist pattern is formed by forming a first opening that exposes the conductive film at a position and a second opening having a bottom with a predetermined thickness above the region of the stacked body that becomes the channel.

  Then, the conductive film exposed from the first opening and the semiconductor film below the conductive film are etched, and the conductive film in which the bottom of the second opening is removed to expose the conductive film is etched. Then, the thin film transistor is patterned.

  Next, in a third step, a protective layer covering the thin film transistor is formed, and a part of the transparent conductive film is exposed to form a pixel electrode.

  As a result, a transmissive TFT array substrate can be manufactured in a total of three photolithography steps, ie, the first step, the second step, and the third step. Therefore, in the transmissive TFT array substrate, the manufacturing process can be shortened and the manufacturing cost can be reduced.

  The manufacturing method of the TFT array substrate of the present invention may include a fourth step of patterning the reflective electrode by a photolithography method on the protective layer formed in the third step.

  According to the above manufacturing method, first, in the first step, the gate electrode is patterned on the substrate.

  Next, in the second step, a gate insulating film, a semiconductor film, and a conductive film including a transparent conductive film provided to cover the semiconductor film are stacked in this order on the substrate on which the gate electrode is formed. And forming a resist layer covering the stacked body, and then, with respect to the resist layer, above the region of the stacked body other than the portion that becomes the channel portion, the source line, the source electrode, and the drain electrode A resist pattern is formed by forming a first opening that exposes the conductive film at a position and a second opening having a bottom with a predetermined thickness above the region of the stacked body that becomes the channel.

  Then, the conductive film exposed from the first opening and the semiconductor film below the conductive film are etched to remove the bottom of the second opening to expose the conductive film. The film is etched to pattern the thin film transistor.

  Next, in a third step, a protective layer covering the thin film transistor is formed, and a part of the transparent conductive film is exposed to form a pixel electrode.

  Next, in the fourth step, a reflective electrode is patterned on the protective layer by photolithography.

  Accordingly, the transflective TFT array substrate can be manufactured by a total of four photolithography processes including the first process, the second process, the third process, and the fourth process. Therefore, in the transflective TFT array substrate, the manufacturing process can be shortened and the manufacturing cost can be reduced.

  In the TFT array substrate manufacturing method of the present invention, the conductive film may have a light shielding property, and the conductive film inside the peripheral edge of the drain electrode may be etched in the third step.

  According to the above manufacturing method, the pixel electrode is formed by etching the conductive film inside the peripheral edge of the drain electrode. Therefore, the periphery of the light transmissive pixel electrode is formed of a light-shielding conductive film. The drain electrode is shielded from light. Thereby, light leakage between pixel electrodes is suppressed.

  In the manufacturing method of the TFT array substrate of the present invention, the semiconductor film is composed of an upper first semiconductor film and a lower second semiconductor film, and the exposed conductive film and the first semiconductor film are formed in the second etching step. The semiconductor layer may be etched.

  According to the above manufacturing method, for example, when the upper first semiconductor film is an n + amorphous silicon film and the lower second semiconductor film is an intrinsic amorphous silicon film, the second opening is formed in the second etching step. By etching the conductive film exposed by removing the bottom of the first semiconductor layer and the first semiconductor layer of the n + amorphous silicon film, the second semiconductor film of the intrinsic amorphous silicon film is exposed to form a channel portion.

  In the manufacturing method of the TFT array substrate of the present invention, a light shielding layer may be formed on an upper layer or a lower layer of the protective layer, and the light shielding layer may be formed simultaneously with the protective layer in the third step.

  According to said manufacturing method, a light shielding layer is formed simultaneously with a protective layer by forming a light shielding layer in the upper layer or lower layer of a protective film. Thereby, the light shielding layer can be formed without increasing the number of photolithography processes.

  In the manufacturing method of the TFT array substrate of the present invention, the protective layer may be formed of a light shielding material.

  According to the above manufacturing method, since the protective layer is formed of the light shielding material, there is no need to provide a step of forming the light shielding film. Therefore, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  In the manufacturing method of the TFT array substrate of the present invention, the gate electrode is formed of a first metal laminated film configured by laminating a plurality of metal films, and the first metal laminated film is an aluminum film or an aluminum alloy film. The metal film comprised by these may be included.

  According to said manufacturing method, the 1st metal laminated film which forms a gate electrode contains the metal film comprised by the aluminum film or the aluminum alloy film. In general, an aluminum film or an aluminum alloy film is a low-resistance material, so that wiring resistance can be reduced.

  In the manufacturing method of the TFT array substrate of the present invention, the conductive film may be composed of a single layer composed of only the transparent conductive film.

  According to the above manufacturing method, since the conductive film is composed of a single layer made of only the transparent conductive film, it is not necessary to expose the transparent conductive film in the third step. Therefore, in the third step, the pixel electrode is formed only by forming the protective layer. Thereby, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  The method for producing a TFT array substrate of the present invention includes: the above-described transparent conductive film in which the conductive film is composed of a compound of indium oxide and tin oxide; and a plurality of metal films provided so as to cover the transparent conductive film. A second metal multilayer film formed by stacking, and the second metal multilayer film may be formed of a lower molybdenum film or molybdenum alloy film and an upper aluminum film or aluminum alloy film. .

  According to the above manufacturing method, the upper layer of the transparent conductive film formed of a compound of indium oxide and tin oxide (ITO (Indium Tin Oxide) film) is the molybdenum film or molybdenum alloy film, and the molybdenum film or molybdenum alloy film. The upper layer becomes an aluminum film or an aluminum alloy film. Therefore, since the molybdenum film or the molybdenum alloy film is interposed between the aluminum film or the aluminum alloy film and the ITO film, the aluminum film or the aluminum alloy film and the ITO film are etched when the aluminum film or the aluminum alloy film is etched. The formation of a local battery between the two is suppressed. Thereby, electrical corrosion (electric corrosion) between the aluminum film or aluminum alloy film and the ITO film can be prevented.

  In the manufacturing method of the TFT array substrate of the present invention, the semiconductor film may be formed of a material having higher light transmittance than amorphous silicon having the same thickness.

  According to the above manufacturing method, the semiconductor film is formed of a material having a higher light transmittance than amorphous silicon having the same thickness. Then, since the semiconductor film is overlapped with the pixel electrode, the light transmittance of the region corresponding to the pixel electrode can be improved.

  In the TFT array substrate manufacturing method of the present invention, in the first step, a plurality of gate lines connected to the gate electrode and a gate line external lead electrode which is an extension portion thereof are formed simultaneously with the gate electrode. Also good.

  According to the above manufacturing method, since the plurality of gate lines and the gate line external extraction electrode which is an extension portion thereof are formed at the same time as the gate electrode, the gate lines and the gate line external extraction electrode can be formed without increasing the manufacturing process. Can be formed. Therefore, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  In the method of manufacturing a TFT array substrate according to the present invention, the gate electrode, the gate line, and the gate line external extraction electrode are formed of a first metal laminated film formed by laminating a plurality of metal films. The lowermost layer of one metal laminated film is formed of a titanium film or a titanium alloy film, and in the third step, the portion of the titanium film or titanium alloy film corresponding to the gate line external extraction electrode is exposed by etching. Also good.

  According to the above manufacturing method, the gate line external extraction electrode is formed of a titanium film or a titanium alloy film. Since the titanium film or the titanium alloy film is a material that is not easily oxidized, the oxidation of the gate line external extraction electrode is suppressed.

  In the manufacturing method of the TFT array substrate of the present invention, the first metal laminated film covers the metal film composed of the lowermost titanium film or titanium alloy film, the aluminum film or the aluminum alloy film, and the metal film. And a molybdenum film or a molybdenum alloy film provided as described above.

  According to the above manufacturing method, the molybdenum film or the molybdenum alloy film can be easily etched by the etchant used for etching the aluminum film or the aluminum alloy film. The gate line external extraction electrode can be formed leaving the titanium film or titanium alloy film.

  In addition, since there is a molybdenum film or a molybdenum alloy film on the upper layer of the metal film composed of the aluminum film or the aluminum alloy film, the protrusions generated on the surface of the aluminum film or the aluminum alloy film by the molybdenum film or the molybdenum alloy film. (Hillock) can be suppressed. Therefore, for example, occurrence of interlayer leakage caused by hillocks penetrating the insulating film is reduced.

  Further, the first metal laminated film includes a metal film made of an aluminum film or an aluminum alloy film. Therefore, since the aluminum film or the aluminum alloy film is a low resistance material, the wiring resistance can be reduced.

  In the method of manufacturing a TFT array substrate according to the present invention, the gate electrode, the gate line, and the gate line external extraction electrode are formed of a first metal laminated film formed by laminating a plurality of metal films. The uppermost layer of one metal laminated film may be formed of a titanium film or a titanium alloy film.

  According to the above manufacturing method, the titanium film or the titanium alloy film is less likely to be oxidized than, for example, a metal film made of an aluminum film or an aluminum alloy film, so that the oxidation of the gate line external extraction electrode can be suppressed. it can. Therefore, unlike the case where a metal film made of an aluminum film or aluminum alloy film that is easily oxidized is exposed, etching of the metal film that is easily oxidized at the corresponding part of the gate line external extraction electrode becomes unnecessary, and the manufacturing process Can be shortened and the manufacturing cost can be reduced.

  In the manufacturing method of the TFT array substrate according to the present invention, the first metal laminated film includes an aluminum film or an aluminum alloy film, and in the third step, protection is performed on the inner side of the peripheral end of the gate line external lead electrode. The layer and the gate insulating film may be etched.

  According to the above manufacturing method, the protective layer and the gate insulating film inside the peripheral edge of the gate line external extraction electrode are etched, and the aluminum film or the aluminum alloy film constituting the first metal laminated film is not exposed. It will be. Further, since the uppermost layer of the first metal laminated film exposed by etching is a titanium film or a titanium nitride film that is not easily oxidized, the gate line external extraction electrode is configured to be hardly oxidized.

  In the manufacturing method of the TFT array substrate according to the present invention, in the second step, the plurality of source lines and the source line external extraction electrode which is an extended portion thereof are arranged in the direction intersecting with the plurality of gate lines. It may be formed at the same time.

  According to the above manufacturing method, the plurality of source lines and the source line external extraction electrodes which are extended portions thereof are formed at the same time as the source electrodes. Therefore, the source lines and the source line external extraction electrodes can be formed without increasing the number of manufacturing steps. Can be formed. Therefore, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  In the method of manufacturing a TFT array substrate according to the present invention, the gate electrode, the gate line, and the gate line external extraction electrode are formed of a first metal laminated film formed by laminating a plurality of metal films, and the source electrode and source The line and source line external extraction electrodes are formed of a second metal laminated film formed by laminating a plurality of metal films, and in the third step, the gate line external extraction electrode and the source line are etched. At least the uppermost layer of the first metal multilayer film and the second metal multilayer film corresponding to the external extraction electrode may be removed.

  According to the above manufacturing method, at the same time as the formation of the pixel electrode, at least the uppermost layer of each laminated film corresponding to the gate line external extraction electrode and the source line external extraction electrode is removed, so that the manufacturing process is increased. However, the laminated structure of the portion corresponding to the gate line external extraction electrode and the source line external extraction electrode can be changed. Therefore, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  In the TFT array substrate manufacturing method of the present invention, the uppermost layer of the first and second metal laminated films is an aluminum film or an aluminum alloy film, or a molybdenum film or a molybdenum alloy film is laminated on the aluminum film or the aluminum alloy film. It may be formed by the film formed.

  According to the above manufacturing method, the uppermost layer of each laminated film corresponding to the gate line external extraction electrode and the source line external extraction electrode is on the aluminum film or the aluminum alloy film, or the aluminum film or the aluminum alloy film. Since the film is formed by laminating a molybdenum film or a molybdenum alloy film, the gate line external extraction electrode and the source line external extraction electrode are formed simultaneously with the formation of the pixel electrode, and the manufacturing process of the TFT array substrate is shortened. Manufacturing cost can be reduced.

  At this time, when the uppermost layer of the laminated film is formed of an aluminum film or an aluminum alloy film, the easily oxidized aluminum film or aluminum alloy film is removed, and the gate line external extraction electrode and the source line external extraction electrode Can prevent oxidation.

  Further, when the uppermost layer of the laminated film is formed of a film formed by laminating a molybdenum film or a molybdenum alloy film on an aluminum film or an aluminum alloy film, the molybdenum film as an upper layer of the aluminum film or the aluminum alloy film Alternatively, the molybdenum alloy film suppresses generation of protrusions (hillocks) on the surface of the aluminum film or the aluminum alloy film.

  Further, when the ITO film is formed under the molybdenum film or the molybdenum alloy film, the molybdenum film or the molybdenum alloy film is interposed between the aluminum film or the aluminum alloy film and the ITO film. When etching a film or an aluminum alloy film, a local battery is prevented from being formed between the aluminum film or the aluminum alloy film and the ITO film, and an electrical connection between the aluminum film or the aluminum alloy film and the ITO film is suppressed. Corrosion (electric corrosion) is suppressed.

  In the manufacturing method of the TFT array substrate of the present invention, the protective layer may have a light shielding property, and may be formed so as to cover the thin film transistor, the gate line, and the source line.

  According to the above manufacturing method, since the protective layer having a light shielding property is formed so as to cover the thin film transistor, the gate line, and the source line, the protective layer blocks light incident on the thin film transistor (TFT), and It functions as a light blocking pattern (black matrix) between the pixels. For this reason, a black matrix is usually unnecessary for the counter substrate disposed opposite to the TFT array substrate, and the manufacturing process of the counter substrate is shortened. Further, light leakage between pixels and light leakage current in the TFT due to the bonding deviation between the TFT array substrate and the counter substrate are suppressed.

  In the TFT array substrate manufacturing method of the present invention, in the third step, one opening is formed by etching corresponding to at least one of the plurality of gate line external extraction electrodes and the plurality of source line external extraction electrodes. Thus, the plurality of gate line external extraction electrodes and the plurality of source line external extraction electrodes may be exposed.

  According to the manufacturing method described above, since it is exposed through one opening corresponding to at least one of the plurality of gate line external extraction electrodes and the plurality of source line external extraction electrodes, the upper layer of each external extraction electrode and between There will be no layers. Therefore, it becomes easy to connect each external extraction electrode to an external drive circuit by, for example, a TAB (Tape Automated Bonding) method. In addition, when an opening is formed for each external extraction electrode and connected to an external drive circuit, the thin film near the bottom of the opening may fall off, resulting in an unstable cross-sectional structure called an overhang. is there. In the present invention, since each external extraction electrode is exposed through one opening, it does not cause an overhang and can be stably connected to an external drive circuit.

  In the manufacturing method of the TFT array substrate of the present invention, in the third step, the protective film for forming the protective layer in the region outside the peripheral edge of the drain electrode and the gate insulating film may be etched.

  For example, if the semiconductor film to be etched in the first etching process of the second process is not completely etched, the semiconductor film may remain between the pixel electrode and the source line. According to the above manufacturing method, in the third step, when the semiconductor film and the gate insulating film are materials that are etched simultaneously, the protective film that forms the protective layer in the region outside the peripheral edge of the drain electrode When the gate insulating film is etched, the remaining semiconductor film is etched simultaneously with the etching of the gate insulating film. Therefore, a short circuit between the pixel electrode and the source line is suppressed.

  In the manufacturing method of the TFT array substrate of the present invention, the uppermost layer of the protective layer is formed of a photosensitive resin film, and in the third step, the surface is formed in an uneven shape, and the uppermost layer of the protective film is a photosensitive resin. It may be formed of a film.

  According to the above manufacturing method, since the uppermost layer of the protective layer is formed of a photosensitive resin film, the surface of the protective layer can be easily formed into an uneven shape by adjusting the light amount and exposing the photosensitive resin. can do.

  In the manufacturing method of the TFT array substrate of the present invention, the surface of the reflective electrode may be formed in a shape reflecting the uneven shape of the surface of the protective layer.

  According to the above manufacturing method, the surface of the reflective electrode has a shape that reflects the uneven shape of the surface of the protective layer, so that the reflection direction of the light incident on the reflective electrode is concentrated in the normal direction of the substrate surface. Can do. For this reason, the amount of light in the normal direction of the substrate surface increases, so that the reflectivity of the reflective electrode is substantially improved.

  In the TFT array substrate manufacturing method of the present invention, in the third step, a protective film is formed to cover the thin film transistor, and the protective film inside the peripheral edge of the drain electrode is etched to thereby form the drain electrode. A drain electrode exposed portion in which the conductive film constituting the electrode is exposed may be formed.

  Here, in the case of etching up to the protective film outside the peripheral edge of the drain electrode, there is a large step with the conductive film as an upper layer at the peripheral edge of the drain electrode, and the conductive film is easily destroyed, and the reflective electrode There is a risk of hindering conduction between the transparent electrode and the transparent electrode. According to the above manufacturing method, the protective film inside the peripheral edge of the drain electrode is etched to form the drain electrode exposed portion, so that the protective film outside the peripheral edge of the drain electrode may be etched. Absent. For this reason, a large step cannot be formed, and conduction between the reflective electrode and the transparent electrode is ensured.

  In the manufacturing method of the TFT array substrate of the present invention, in the fourth step, the transparent electrode may be formed by etching the conductive film inside the peripheral end of the drain electrode exposed portion.

  According to the above manufacturing method, the transparent electrode is formed by etching the conductive film inside the peripheral edge of the exposed portion of the drain electrode, so that the transparent electrode and the reflective electrode are connected at the peripheral edge of the transparent electrode. Will be. On the other hand, when the conductive film outside the peripheral edge of the drain electrode exposed portion is etched, not only the connection between the transparent electrode and the reflective electrode is lost, but also there is a gap between the transparent electrode and the reflective electrode. As a result, the transmittance and the reflectance are modulated around the gap.

  In the manufacturing method of the TFT array substrate of the present invention, the reflective electrode may be formed of an aluminum film or an aluminum alloy film.

  According to the above manufacturing method, the aluminum film or the aluminum alloy film is a material having a high reflectivity and an excellent light shielding property. Therefore, the reflective electrode efficiently reflects ambient light and is applied to the TFT. Incident light can be reliably blocked.

  In the TFT array substrate manufacturing method of the present invention, the conductive film is formed of a single layer of only a transparent conductive film formed of a compound of indium oxide and tin oxide, and the reflective electrode is a lower molybdenum film or molybdenum. It may be formed of two layers of an alloy film and an aluminum film or aluminum alloy film as an upper layer.

  According to the above manufacturing method, the molybdenum film or the molybdenum alloy film forming the reflective electrode is interposed between the transparent conductive film formed of the ITO film and the aluminum film or the aluminum alloy film forming the reflective electrode. become. Therefore, when the aluminum film or the aluminum alloy film is etched, the formation of a local battery between the aluminum film or the aluminum alloy film and the ITO film is suppressed. Thereby, electrical corrosion (electric corrosion) between the aluminum film or aluminum alloy film and the ITO film can be prevented.

  Further, since the molybdenum film or the molybdenum alloy film can be easily etched by an etchant used for etching the aluminum film or the aluminum alloy film, the manufacturing process of the TFT array substrate and the manufacturing cost can be reduced. .

  In the manufacturing method of the TFT array substrate of the present invention, in the first step, a plurality of gate lines connected to the gate electrode and a gate line external extraction electrode which is an extension portion thereof are formed simultaneously with the gate electrode, In the second step, a plurality of source lines connected to the source electrode and a source line external extraction electrode as an extension portion thereof are formed simultaneously with the source electrode in a direction intersecting with the plurality of gate lines. In addition, the gate line and the source line may be formed so as to have a light shielding property, and a peripheral end of the reflective electrode overlaps the gate line and the source line.

  According to the above manufacturing method, since the light-shielding gate line and source line are arranged between the reflective electrodes, the occurrence of light leakage between the reflective electrodes is suppressed. In addition, the gate line and the source line also function as a light blocking pattern (black matrix) between the pixels. Normally, the black matrix is not required for the counter substrate disposed opposite to the TFT array substrate, and the counter substrate The manufacturing process is shortened. Furthermore, the occurrence of light leakage between pixels and light leakage current in the TFT due to the misalignment between the TFT array substrate and the counter substrate is suppressed.

  In the manufacturing method of the TFT array substrate of the present invention, the protective layer may include an organic film.

  According to the above manufacturing method, since the organic film has a low relative dielectric constant, the parasitic capacitance formed by the protective layer between the peripheral edge of the reflective electrode and the overlapping portion of the gate line and the source line can be reduced.

  In the manufacturing method of the TFT array substrate of the present invention, the first metal laminated film constituting the gate electrode is composed of the lowermost titanium film or titanium alloy film and the aluminum film or aluminum alloy film, The film includes a transparent conductive film, a molybdenum film or a molybdenum alloy film provided so as to cover the transparent conductive film, and an aluminum film or an aluminum alloy film provided so as to cover the molybdenum film or the molybdenum alloy film. The reflective electrode is composed of two layers of a lower molybdenum film or molybdenum alloy film and an upper aluminum film or aluminum alloy film. In the fourth step, the gate line external lead is formed by etching. Exposing the titanium film or titanium alloy film in a portion corresponding to the electrode, and the source line external extraction electrode It may be exposed above the transparent conductive film of the corresponding portion.

  According to the above manufacturing method, the portion of the aluminum film or aluminum alloy film corresponding to the gate line external extraction electrode and the portion corresponding to the source line external extraction electrode are easily oxidized by the etching in the fourth step. Since the aluminum film or the aluminum alloy film and the molybdenum film or the molybdenum alloy film are removed at the same time, the oxidation of the gate line external extraction electrode and the source line external extraction electrode can be prevented. Thereby, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  The manufacturing method of the TFT array substrate of the present invention comprises a transmissive TFT array substrate in a total of three photolithography steps, a first step, a second step, and a third step, and a transflective TFT array substrate. , The first process, the second process, the third process, and the fourth process, respectively, can be produced in a total of four photolithography processes. Therefore, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, a TFT array substrate constituting a liquid crystal display device will be described. However, the present invention is not limited to the following embodiments, and may have other configurations.

Embodiment 1 of the Invention
The TFT array substrate 20a according to Embodiment 1 of the present invention will be described below.

  FIG. 1 is a schematic plan view of one pixel of the TFT array substrate 20a, and FIGS. 2 and 3 are schematic cross-sectional views showing a manufacturing process of the TFT array substrate 20a in the A-A 'cross section in FIG. FIG. 3C corresponds to a schematic cross-sectional view of the TFT array substrate 20a.

  The TFT array substrate 20a constitutes a liquid crystal display device together with a counter substrate provided so as to face each other and a liquid crystal layer provided so as to be sandwiched between the two substrates.

  The TFT array substrate 20a includes a plurality of gate lines 2 provided on the insulating substrate 1 so as to extend in parallel to each other, and a plurality of gate lines provided so as to extend in parallel to each other in a direction orthogonal to the gate lines 2. And a source line 6. A TFT 8 is provided at each intersection between the gate line 2 and the source line 6. In addition, a pixel electrode 5 a constituting a pixel is provided in a display region surrounded by the pair of gate lines 2 and the pair of source lines 6 corresponding to each TFT 8. Furthermore, a gate line external lead terminal 2d and a source line external lead terminal 6e, which will be described later, are disposed at the ends of each gate line 2 and source line 6, respectively.

  In this embodiment, the TFT array substrate 20a in which the pixels are arranged in a matrix and the gate lines 2 and the source lines 6 are orthogonal to each other is illustrated. However, the present invention is, for example, a TFT array in which the pixels are arranged in a delta arrangement. It can also be applied to a substrate. The same applies to Embodiments 2 to 4 described later.

  The TFT 8 includes a gate electrode 2c having a protruding portion protruding laterally from the gate line 2, a semiconductor film 4 provided on the gate electrode 2c via a gate insulating film 3, and a source line 6 on the semiconductor film 4. The source electrode 6c is a projecting portion projecting sideways, and the drain electrode 6d is provided on the semiconductor film 4 so as to face the source electrode 6c and is connected to the pixel electrode 5a. A protective layer 9 and a light shielding layer 10 are provided so as to cover the TFT 8. Further, in the semiconductor film 4, a channel portion 14 is provided in a region between the source electrode 6c and the drain electrode 6d corresponding to the gate electrode 2c.

  Further, in the present embodiment, the TFT 8 in which the gate electrode 2c protrudes from the gate line 2 is illustrated, but the present invention is, for example, a so-called TFT on-gate structure in which a TFT channel portion is disposed on the gate line 2 It can also be applied to the case. The same applies to Embodiments 2 to 4 described later.

  The counter substrate has a multilayer stacked structure in which a color filter layer, a common electrode, and an alignment film are sequentially stacked on an insulating substrate.

  The color filter layer is provided with any colored layer of red, green, and blue corresponding to each pixel of the TFT array substrate 20a. The colored layer may be a combination of cyan, magenta, and yellow in addition to a combination of red, green, and blue.

  The liquid crystal layer is made of a nematic liquid crystal material having electro-optical characteristics.

  Next, a manufacturing method of the TFT array substrate 20a according to Embodiment 1 of the present invention will be described.

<First step (gate electrode forming step)>
As shown in FIG. 2A, a titanium film (thickness of about 500 mm) and an aluminum film (thickness of about 3000 mm) are sequentially formed on the entire substrate on the glass substrate 1 by sputtering, and then photolithography is performed. A gate electrode 2c and a gate line formed by a first metal laminated film composed of a gate first metal film 2a and a gate second metal film 2b by pattern formation by a technology (Photo Engraving Process, hereinafter referred to as “PEP technology”) 2. Form a gate line external extraction electrode. Thereby, the substrate 20a1 is obtained. In addition, since the gate line 2, the gate line external extraction electrode that is an extension portion thereof, and the gate electrode 2c that is a protrusion portion thereof are simultaneously formed, it is possible to shorten the manufacturing process and the manufacturing cost.

  Here, since the 1st metal laminated film which forms the gate electrode 2c contains the aluminum film or aluminum alloy film which is a low resistance material, the wiring resistance of the gate line 2 can be reduced.

  Further, a molybdenum film or a molybdenum alloy film may be further formed on the gate second metal film 2b made of an aluminum film. According to this configuration, protrusions (hillocks) generated on the surface of the aluminum film can be suppressed by the molybdenum film or the molybdenum alloy film as the upper layer of the aluminum film. Therefore, for example, occurrence of interlayer leakage caused by hillocks penetrating the insulating film is reduced. Here, the hillock is a projection generated on the surface of the aluminum film due to a thermal history such as a thermal process or a plasma process. The molybdenum film or molybdenum alloy film is easily etched by an etchant used for etching the aluminum film or aluminum alloy film, for example, a mixed solution of nitric acid, phosphoric acid and acetic acid. It is removed at the same time, and there is no need to provide a separate etching process.

<Second Step / Laminate Forming Step>
First, a silicon nitride film (thickness of about 4000 mm), an amorphous silicon film (thickness of about 1500 mm), and phosphorus are formed on the entire substrate 20a1 on which the gate electrode 2c, the gate line 2, and the gate line external extraction electrode are formed by plasma CVD. An amorphous silicon film (thickness of about 500 mm) doped with impurities such as is sequentially formed.

  Next, an ITO (Indium Tin Oxide) film (thickness of about 1000 mm), a molybdenum film (thickness of about 1000 mm), and an aluminum film (thickness of about 1000 mm) are sequentially formed on the entire substrate by sputtering.

  Here, since the molybdenum film is interposed between the aluminum film and the ITO film, when the aluminum film is etched in a later process, formation of a local battery between the aluminum film and the ITO film is suppressed. The Thereby, electrical corrosion (electric corrosion) between the aluminum film and the ITO film can be prevented.

  In this manner, in order from the lower layer, the gate insulating film 3, the first semiconductor film 4a, the second semiconductor film 4b, the transparent conductive film 5, and the second source composed of the source first metal film 6a and the source second metal film 6b. A laminate composed of a metal laminate film is formed. Here, the semiconductor film 4 is composed of two layers of a first semiconductor film 4a and a second semiconductor film 4b, and the conductive film is a transparent conductive film 5, a source first metal film 6a, and a source second metal film 6b. Composed of layers. The transparent conductive film 5 is not particularly limited to ITO, and may be any material that can obtain a desired resistance value such as IZO (Indium Zinc Oxide), zinc oxide, and tin oxide.

  In the present embodiment, a molybdenum film is exemplified as the source first metal film 6a, but the present invention is not limited to this, and an alloy film such as a titanium film, a chromium film, and a molybdenum alloy film is used. May be. Furthermore, although the aluminum film is illustrated as the source second metal film 6b, it is not limited to this and may be an aluminum alloy film or the like.

<Second step / resist pattern forming step 1>
First, a resist made of a photosensitive resin is applied to the entire substrate to form a resist layer.

  Next, the exposure amount is adjusted using a slit mask or the like on the resist layer formed on the entire substrate to form a first resist pattern 7a having a plurality of film thicknesses as shown in FIG. Here, the first resist pattern 7a is a first layer that exposes the conductive film (source second metal film 6b) above the region other than the portions that become the channel portion 14, the source line 6, the source electrode 6c, and the drain electrode 6d. An opening 7c and a second opening 7d having a bottom with a predetermined thickness at a position above the gate electrode 2c, specifically, at an upper position to be the channel portion 14, are provided. The ratio between the thickness of the resist layer in the second opening 7d and the thickness of the resist layer in other portions differs depending on the etching conditions, ashing conditions, and the like in the subsequent process. The film thickness of the resist layer of the part 7d is about 15000 to 20000 mm, and the film thickness of other parts is about 40000 mm. Thereby, the substrate 20a2 is obtained.

<Second step / first etching step>
2C, using the first resist pattern 7a as a mask, the source second metal film 6b, the source first metal film 6a, and the transparent conductive film 5 on the substrate 20a2 are etched in this order by wet etching. Subsequently, the second semiconductor film 4b and the first semiconductor film 4a are etched in this order by dry etching to form the source / drain formation portion 6f. Thereby, the substrate 20a3 is obtained.

<Second step / resist pattern forming step 2>
As shown in FIG. 3A, the entire first resist pattern 7a on the substrate 20a3 is ashed. As a result, the first resist pattern 7a is thinned as a whole, the bottom of the second opening 7d is removed, and the second resist pattern 7b is formed in which the conductive film (source second metal film 6b) is exposed. Thereby, the substrate 20a4 is obtained.

<Second step / second etching step>
First, using the second resist pattern 7b as a mask, the transparent conductive film 5, the source first metal film 6a, and the source second metal film 6b (source / drain formation portion 6f) on the substrate 20a4 are etched by wet etching to form the source electrode 6c, drain electrode 6d ', source line 6 and source line external lead electrode are formed. In addition, since the source line 6, the source line external extraction electrode that is the extended portion, and the source electrode that is the protruding portion are formed at the same time, the manufacturing process can be shortened and the manufacturing cost can be reduced.

  Next, using the second resist pattern 7b as a mask, the second semiconductor film 4b is etched by dry etching to form a channel portion to form the TFT 8.

  Next, the second resist pattern 7b on the substrate is removed. As a result, a substrate 20a5 as shown in FIG. 3B is obtained.

<Third Step (Protective Layer / Pixel Electrode Formation Step)>
In advance, a light-shielding dry film having an OD value of 3.0 and a film thickness of 2.5 μm is prepared by sandwiching a resin film of a photosensitive resin in which carbon is dispersed with a cover film such as a PET (polyethylene terephthalate) film.

  Here, the OD value is a value indicating the light shielding degree of the light shielding film, and indicates the transmission density. When the intensity of the incident light is I and the intensity of the transmitted light after passing through the light shielding film is I ′, the OD value is represented by OD value = −log (I ′ / I). Usually, the transmission density in the visible light region of 400 to 700 nm is shown, and the transmittance is lower as the OD value is larger.

  First, a silicon nitride film (thickness of about 2000 mm) is formed on the entire substrate 20a5 by plasma CVD to form a protective film.

  Next, after the cover film on one side of the prepared dry film is peeled off, the dry film is bonded to the substrate while pressing the surface on which the cover film is peeled off, and the other cover film is peeled off. Thereby, the resin film of the photosensitive resin in which carbon is dispersed is transferred onto the substrate, and a light shielding film is formed. This step is generally executed while heating the dry film, a so-called thermal transfer process, a method of transferring the resin film on the substrate that a dry film lamination method.

  Here, the light-shielding film is not limited to the resin film of photosensitive resin in which carbon is dispersed, and is a material that can obtain a desired OD value, taper shape, and dielectric constant, such as a pigment-dispersed black resist. Also good. Further, in the present embodiment, the configuration in which the light shielding film is provided on the upper layer of the protective film is illustrated, but on the contrary, the configuration in which the light shielding film is provided on the lower layer of the protective film may be employed.

  Thus, by forming the light shielding film on the upper layer or the lower layer of the protective film, it is possible to pattern the light shielding layer 10 together with the protective layer 9 in a subsequent photolithography process. Thereby, the light shielding layer 10 can be formed without increasing the number of photolithography processes.

  Further, the protective film may have a one-layer structure of a black photoresist having a light-shielding property instead of a two-layer structure with the light-shielding film. In this case, the light shielding film can be omitted, and there is no need to provide a process for forming the light shielding film. Therefore, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  Next, the light shielding film formed on the entire substrate is exposed, developed, and post-baked using a photomask to form the light shielding layer 10.

  Next, using the light shielding layer 10 as a mask, the protective film and the conductive film (the source first metal film 6a and the source second metal film 6b) are etched to expose a part of the transparent conductive film 5 and cover the TFT 8 9 and the pixel electrode 5a are formed. Here, since etching is performed on the conductive film inside the peripheral edge of the drain electrode 6d, the periphery of the light-transmissive pixel electrode 5a is shielded from light by the drain electrode 6d formed of a light-shielding conductive film. Will be. Thereby, light leakage between the pixel electrodes 5a is suppressed, and a TFT array substrate 20a as shown in FIG. 3C is obtained.

  The protective layer 9 and the light shielding layer 10 are formed so as to cover not only the TFT 8 but also the gate line 2 and the source line 6. Thereby, the protective layer 9 and the light shielding layer 10 having a light shielding property block light incident on the TFT 8 and function as a light blocking pattern (black matrix) between the pixels. For this reason, a black matrix is usually unnecessary for the counter substrate disposed opposite to the TFT array substrate, and the manufacturing process of the counter substrate is shortened. Further, light leakage between pixels and light leakage current in the TFT due to the bonding deviation between the TFT array substrate and the counter substrate are suppressed.

  In the present embodiment, the method of etching the conductive film inside the peripheral edge of the drain electrode 6d in the third step is exemplified, but the protective film and the gate insulating film in the region outside the peripheral edge of the drain electrode 6d are etched. May be.

  Specifically, for example, when the semiconductor film 4 to be etched in the first etching process of the second process is not completely etched, the semiconductor film 4 remains between the pixel electrode 5 a and the source line 6. There is a fear. However, in the third step, when etching the conductive film and the gate insulating film 3 in the region outside the peripheral edge of the drain electrode, the remaining semiconductor film 4 is etched simultaneously with the etching of the gate insulating film 3. Therefore, a short circuit between the pixel electrode 5a and the source line 6 is suppressed. The same applies to Embodiments 2 to 4 described later.

  Next, the gate line external extraction electrode 2d and the source line external extraction electrode 6e will be described in more detail.

  FIG. 4A is a schematic plan view of an end portion of the TFT array substrate 20a provided with a plurality of gate line external lead terminals 2d, and FIG. 4B is a cross-sectional view taken along line B- in FIG. It is a cross-sectional schematic diagram in a B 'cross section. FIG. 5A is a schematic plan view of an end portion of the TFT array substrate 20a provided with a plurality of source line external lead terminals 6e. FIG. 5B is a plan view of FIG. It is a cross-sectional schematic diagram in CC 'cross section.

  First, in the stage before the formation of the protective layer 9 and the pixel electrode 5a, the gate line external extraction electrode 2f and the source line external extraction electrode 6g are formed on the gate line external extraction electrode 6g as shown in FIGS. 17 (a) and 19 (a). In addition, a protective film (protective layer 9) and a light shielding film (light shielding layer 10) are formed.

  At the same time as the formation of the protective layer 9 and the pixel electrode 5a, the gate insulating film 3, the protective film, and the light-shielding film laminated on the gate line external extraction electrode 2d are stacked on the source line external extraction electrode 6e. Then, as shown in FIGS. 17B and 19B, the gate line external extraction electrode 2f and the source line external extraction electrode 6g are exposed by removing the light shielding film and the light shielding film, respectively.

  Further, in the present embodiment, the gate second metal film 2b which is the uppermost layer of the gate line external extraction electrode 2f and the source second metal film 6b which is the uppermost layer of the source line external extraction electrode 6e are formed. Since each is an aluminum film, the gate line external extraction electrode 2f and the source line external extraction electrode 6g are exposed, and at the same time, as shown in FIGS. 17 (c) and 19 (c), each gate second metal film 2b. The source first metal film 6a and the source second metal film 6b are etched, the gate line external lead terminal 2d where the gate first metal film 2a is exposed, and the source line external lead terminal 6e where the transparent conductive film 5 is exposed, Each is formed. As a result, the aluminum film that is easily oxidized can be removed from the external extraction electrode portion, and oxidation of the gate line external extraction electrode and the source line external extraction electrode can be prevented.

  Then, an aluminum film (aluminum alloy film) constituting the gate second metal film 2b and the source second metal film 6b is formed as a film formed by laminating a molybdenum film (molybdenum alloy film) on the aluminum film (aluminum alloy film). Also good.

  In this case, generation of protrusions (hillocks) on the surface of the aluminum film (aluminum alloy film) is suppressed by the molybdenum film (molybdenum alloy film), which is an upper layer of the aluminum film (aluminum alloy film).

  Further, when an ITO film is formed under the molybdenum film (molybdenum alloy film), the molybdenum film (molybdenum alloy film) is interposed between the aluminum film (aluminum alloy film) and the ITO film. Therefore, when the aluminum film (aluminum alloy film) is etched, the formation of a local battery between the aluminum film (aluminum alloy film) and the ITO film is suppressed, and the aluminum film (aluminum alloy film) and the ITO film are suppressed. Electrical corrosion (electric corrosion) between the two is suppressed.

  Here, in the source line external extraction electrode 6g, since the source first metal film 6a is a molybdenum film, the source first metal film 6a is also sourced by wet etching using a mixed solution of nitric acid, phosphoric acid and acetic acid as an etchant. Etching is performed simultaneously with the second metal film 6b (aluminum film).

  Further, since the gate line external lead terminal 2d (gate line external lead electrode 2f) and the source line external lead terminal 6e (source line external lead electrode 6g) are each exposed through one opening, the gate line external lead terminal As shown in FIGS. 17 (c) and 19 (c), no thin film material exists between the upper layer of 2d and the source line external lead terminal 6e and between them, and an overhang described later does not occur. Therefore, for example, each external drive circuit can be easily and stably connected to the gate line external lead terminal 2d and the source line external lead terminal 6e by a TAB (Tape Automated Bonding) method.

  On the other hand, when a contact hole is formed for each external lead electrode and connection with an external drive circuit is made, as shown in FIGS. 18 (c) and 20 (c), the contact hole is formed. The gate second metal film 2b, the source first metal film 6a and the source second metal film 6b are isotropically etched by wet etching, so that a thin film does not exist in the lower layer called an overhang. Since an unstable cross-sectional structure in which film peeling is likely to occur is formed, the connection between the external extraction electrode (terminal) and the external drive circuit becomes unstable. Each process shown in FIGS. 18 and 20 corresponds to each process shown in FIGS.

  In the present embodiment, the titanium film is exemplified as the gate first metal film 2a under the first metal laminated film constituting the gate line 2, the gate electrode 2c, and the gate line external extraction electrode 2f. However, the present invention is not limited to this. However, it may be a chromium film, a molybdenum film, or the like.

  However, specifically, when a titanium film is used as the gate first metal film 2a in the lower layer of the first metal laminated film and an aluminum film or an aluminum alloy film is used as the gate second metal film 2b in the upper layer, By dry etching, the gate line 2, the gate electrode 2c, and the gate line external extraction electrode 2f can be easily patterned. When the gate line external lead terminal 2d is formed, wet etching is performed so that only the titanium film, which is the gate first metal film 2a, is selectively etched, and the gate second metal film 2b is used. A corresponding portion of an aluminum film or an aluminum alloy film can be removed.

  As described above, if the gate first metal film 2a is formed of a titanium film, the titanium film is less likely to be oxidized than the aluminum film or the aluminum alloy film. The electrical connection by the TAB method with the external drive circuit is ensured, and the reliability can be improved.

  Here, the TAB method is to electrically connect conductors, for example, by using a copper foil lead wiring pattern formed on a tape-like film based on polyimide resin.

  Further, by forming the gate second metal film 2b from an aluminum film or an aluminum alloy film, an effect of lowering the wiring resistance can be obtained, and selective etching for easily leaving only the titanium film by the wet etching is performed. It can be done reliably.

  As described above, according to the manufacturing method of the present invention, the transmissive TFT array substrate 20a is formed on the light shielding layer 10 covering the TFT 8, the black matrix between the pixels, the gate line external lead terminal 2d, and the source line external lead terminal 6e. Including the formation, it can be manufactured by a total of three photolithography processes including a first process, a second process, and a third process. Therefore, it is possible to shorten the manufacturing process and the manufacturing cost of the transmissive TFT array substrate.

<< Embodiment 2 of the Invention >>
The TFT array substrate 20b according to Embodiment 2 of the present invention will be described below.

  6 and 7 are schematic cross-sectional views showing the manufacturing process of the TFT array substrate 20b corresponding to FIGS. FIG. 7C corresponds to a schematic cross-sectional view of the TFT array substrate 20b.

  The TFT array substrate 20b constitutes a liquid crystal display device together with a counter substrate provided so as to face each other and a liquid crystal layer provided so as to be sandwiched between the two substrates.

  The TFT array substrate 20b includes a plurality of gate lines 2 provided on the insulating substrate 1 so as to extend in parallel with each other and a plurality of gate lines provided in parallel with each other in a direction orthogonal to the gate lines 2. Source line 6. A TFT 8 is provided at each intersection between the gate line 2 and the source line 6. In addition, a pixel electrode 5 a constituting a pixel is provided in a display region surrounded by the pair of gate lines 2 and the pair of source lines 6 corresponding to each TFT 8. Furthermore, a gate line external extraction electrode 2d and a source line external extraction electrode 6e, which will be described later, are disposed at the ends of each gate line 2 and source line 6, respectively.

  The TFT 8 includes a gate electrode 2c having a protruding portion protruding laterally from the gate line 2, a semiconductor layer 4 provided on the gate electrode 2c via a gate insulating film 3, and a source line 6 on the semiconductor layer 4. The source electrode 5b is a projecting portion projecting sideways, and the drain electrode 6d is provided on the semiconductor layer 4 so as to face the source electrode 5b and connected to the pixel electrode 5a. A protective layer 9 and a light shielding layer 10 are provided so as to cover the TFT 8. Further, in the semiconductor film 4, a channel portion 14 is provided in a region between the source electrode 6c and the drain electrode 6d corresponding to the gate electrode 2c.

  Since the counter substrate and the liquid crystal layer are the same as those in the first embodiment, description thereof is omitted.

  Next, a manufacturing method of the TFT array substrate 20b according to Embodiment 2 of the present invention will be described.

<First step (gate electrode forming step)>
As shown in FIG. 6A, a titanium film (thickness of about 500 mm), an aluminum film (thickness of about 3000 mm), and a titanium nitride film (thickness of about 1000 mm) are formed on the entire substrate on the glass substrate 1 by sputtering. Are sequentially formed, and then patterned by the PEP technique to form a gate electrode 2c composed of a first metal laminated film including the gate first metal film 2a, the gate second metal film 2b, and the gate third metal film 2e. The gate line 2 and the gate line external extraction electrode are formed. Thereby, the substrate 20b1 is obtained.

  Here, the metal film used as the gate first metal film 2a is not particularly limited, and examples thereof include a titanium film, a chromium film, and a molybdenum film. The metal film used as the gate second metal film 2b is not particularly limited, and examples thereof include an aluminum film, a tantalum film, and a titanium film. Of these exemplified metals, an aluminum film is particularly preferable. Furthermore, the metal film used as the gate third metal film 2e is not particularly limited, and examples thereof include a titanium film and a titanium nitride film. The reason for selecting these metal films will be described later.

<Second Step / Laminate Forming Step>
First, a silicon nitride film (having a thickness of about 4000 mm) is formed by plasma CVD on the entire substrate 20a1 on which the gate electrode 2c, the gate line 2, and the gate line external extraction electrode are formed.

  Next, a zinc oxide film (having a thickness of about 1500 mm) is formed on the entire substrate on which the silicon nitride film is formed by a pulse laser deposition CVD method.

  Next, an ITO (Indium Tin Oxide) film (thickness of about 1000 mm) is formed by sputtering on the entire substrate on which the zinc oxide film is formed.

  As a result, a laminate composed of the gate insulating film 3, the semiconductor film 4, and the transparent conductive film 5 is formed in order from the lower layer. Here, the semiconductor film 4 is composed of a zinc oxide film, and the conductive film is composed only of the transparent conductive film 5.

  The semiconductor film 4 may be made of a material having a higher light transmittance than amorphous silicon having the same thickness, such as a magnesium zinc oxide film, a cadmium zinc oxide film, and a cadmium oxide film, in addition to the exemplified zinc oxide film. Good.

  Further, the semiconductor film 4 is transparent in order to obtain a desired mobility and on / off ratio (ratio of on-state current to off-state leakage current when the drain current is switched by the gate voltage). You may dope impurities, such as phosphorus, in the grade which does not lose property.

  The transparent conductive film 5 is not particularly limited to ITO, and may be any material that can obtain a desired resistance value, such as IZO (Indium Zinc Oxide), a zinc oxide film, and a tin oxide film.

  With such a configuration, since the lower layer of the transparent conductive film 5 constituting the pixel electrode 5a is formed of a transparent zinc oxide film, the light transmittance in the region corresponding to the pixel electrode 5a is improved. And the contrast and luminance of the liquid crystal display device can be improved.

  In addition, since the conductive film is composed of only the transparent conductive film 5, it is not necessary to etch the metal film and expose the transparent conductive film 5 as in the first embodiment in the third step described later. Therefore, in the third step, the pixel electrode 5a is formed only by forming the protective layer. Thereby, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

<Second step / resist pattern forming step 1>
First, a resist made of a photosensitive resin is applied to the entire substrate to form a resist layer.

  Next, the exposure amount is adjusted using a slit mask or the like on the resist layer formed on the entire substrate to form a first resist pattern 7a having a plurality of film thicknesses as shown in FIG.

  Here, the first resist pattern 7a is a first layer that exposes the conductive film (source second metal film 6b) above the region other than the portions that become the channel portion 14, the source line 6, the source electrode 6c, and the drain electrode 6d. An opening 7c and a second opening 7d having a bottom with a predetermined thickness at a position above the gate electrode 2c, specifically, at an upper position to be the channel portion 14, are provided. The ratio of the thickness of the resist layer in the second opening 7d and the thickness of the resist layer in the other portion varies depending on the etching conditions in the subsequent process. For example, the resist in the second opening 7d The film thickness of the layer is about 15000-20000 mm, and the film thickness of the other part is about 40000 mm. Thereby, the substrate 20b2 is obtained.

<Second step / first etching step>
As shown in FIG. 6C, using the first resist pattern 7a as a mask, the semiconductor film 4 and the transparent conductive film 5 on the substrate 20a2 are etched to form the source / drain formation portion 6f. Thereby, the substrate 20b3 is obtained.

<Second step / resist pattern forming step 2>
As shown in FIG. 7A, the entire first resist pattern 7a on the substrate 20b3 is ashed. As a result, the thickness of the first resist pattern 7a is reduced as a whole, and the bottom of the second opening 7d is removed to form the second resist pattern 7b in which the transparent conductive film 5 is exposed. Thereby, the substrate 20b4 is obtained.

<Second step / second etching step>
First, using the second resist pattern 7b as a mask, the transparent conductive film 5 on the substrate 20b4 is etched to form a source electrode 5b, a drain electrode 5c, a source line 6, and a source line external lead electrode. Thereby, the TFT 8 is formed.

  Next, the second resist pattern 7b on the substrate is removed. As a result, a substrate 20b5 as shown in FIG. 7B is obtained.

<Third Step (Protective Layer / Pixel Electrode Formation Step)>
As in the first embodiment, a light-shielding dry film is prepared in advance.

  First, a silicon nitride film (thickness of about 2000 mm) is formed on the entire substrate 20a5 by plasma CVD to form a protective film.

  Next, after the cover film on one side of the prepared dry film is peeled off, the dry film is bonded to the substrate while pressing the surface on which the cover film is peeled off, and the other cover film is peeled off. Thereby, the resin film of the photosensitive resin in which carbon is dispersed is transferred onto the substrate, and a light shielding film is formed.

  The light-shielding film is not limited to a resin film of photosensitive resin in which carbon is dispersed, and any material that can obtain a desired OD value, taper shape, and dielectric constant, such as a pigment-dispersed black resist, may be used. .

  Further, the protective film may have a one-layer structure of a black photoresist having a light-shielding property instead of a two-layer structure with the light-shielding film. In this case, the light shielding film can be omitted.

  Next, the light shielding film formed on the entire substrate is exposed, developed, and post-baked using a photomask to form the light shielding layer 10.

  Next, using the light shielding layer 10 as a mask, the protective film is etched to form the protective layer 9 and the pixel electrode 5 a that cover the TFT 8. As a result, a TFT array substrate 20b as shown in FIG. 7C is obtained. The protective layer 9 and the light shielding layer 10 are formed so as to cover not only the TFT 8 but also the gate line 2 and the source line 6.

  Here, the gate line external extraction electrode 2f and the source line external extraction electrode will be described in more detail.

  FIG. 8A is a schematic plan view of an end portion of the TFT array substrate 20b provided with a plurality of gate line external extraction electrodes 2f, and FIG. 8B is a diagram of FIG. It is a cross-sectional schematic diagram in a D 'cross section.

  The gate line external extraction electrode 2f is formed of the gate insulating film 3 stacked on the gate line external extraction electrode at the same time as the formation of the protective layer 9 and the pixel electrode 5a, and the gate line external extraction electrode composed of a protective film and a light shielding film. The contact hole 11c is formed on the inner side of the peripheral edge of 2f to be exposed. As a result, the easily oxidized aluminum film constituting the gate second metal film 2b of the first metal laminated film is not exposed. The uppermost layer of the first metal laminated film exposed by etching is a titanium nitride film that is not easily oxidized. With these configurations, the gate line external extraction electrode 2f is configured not to be oxidized. Therefore, the electrical connection between the gate line external extraction electrode 2f and the external drive circuit can be ensured, and the reliability can be improved. Furthermore, unlike Embodiment 1, it is not necessary to etch the gate second metal film 2b (aluminum film) that is easily oxidized to form the gate line external lead terminal 2d, which shortens the manufacturing process and reduces the manufacturing cost. It becomes possible.

  In addition, since the titanium nitride film or the titanium film has better adhesion to the silicon nitride film constituting the gate insulating film 3 than the aluminum film, film peeling hardly occurs and a stable manufacturing yield can be obtained. it can.

  The source line external extraction electrode does not need to etch the second metal laminated film as in the first embodiment, and at the same time as the formation of the protective layer 9 and the pixel electrode 5a, only the protective film and the light shielding film on the upper layer thereof are etched. Will be exposed.

  In the present embodiment, since an aluminum film is used as the gate second metal film 2b, an effect of reducing the wiring resistance of the gate line 2 can be obtained. Further, since a titanium nitride film is used as the gate third metal film 2e on the upper layer, generation of hillocks on the surface of the aluminum film is suppressed, and interlayer leakage between the gate lines 2 and the source signal lines 6 due to hillocks can be reduced. .

  As described above, according to the manufacturing method of the present invention, the transmissive TFT array substrate 20b is formed on the light shielding layer 10 covering the TFT 8, the black matrix between the pixels, the gate line external extraction electrode 2f, and the source line external extraction electrode. Including the first step, the second step, and the third step, a total of three photolithography steps. Therefore, it is possible to shorten the manufacturing process and the manufacturing cost of the transmissive TFT array substrate.

<< Embodiment 3 of the Invention >>
The TFT array substrate 20c according to Embodiment 3 of the present invention will be described below.

  FIG. 9 is a schematic plan view of the TFT array substrate 20c. FIGS. 10, 11 and 12 are schematic cross-sectional views showing the manufacturing process of the TFT array substrate 20c in the E-E 'cross section in FIG. FIG. 12B corresponds to a schematic cross-sectional view of the TFT array substrate 20c.

  The TFT array substrate 20c constitutes a liquid crystal display device together with a counter substrate provided so as to face each other and a liquid crystal layer provided so as to be sandwiched between the two substrates.

  The TFT array substrate 20c includes a plurality of gate lines 2 provided on the insulating substrate 1 so as to extend in parallel to each other, and a plurality of gate lines provided so as to extend in parallel to each other in a direction orthogonal to the gate lines 2. Source line 6. A TFT 8 is provided at each intersection between the gate line 2 and the source line 6. In addition, pixel electrodes (transparent electrode 5 d and reflective electrode 12) constituting pixels are provided in a display region surrounded by a pair of gate lines 2 and a pair of source lines 6 corresponding to each TFT 8. Here, the periphery of the transparent electrode 5d is the reflective electrode 12, and the transparent electrode 5d and the reflective electrode 12 constitute a pixel electrode. Furthermore, a gate line external lead terminal and a source line external lead terminal, which will be described later, are disposed at the ends of each gate line 2 and source line 6, respectively.

  The TFT 8 includes a gate electrode 2c having a protruding portion protruding laterally from the gate line 2, a semiconductor film 4 provided on the gate electrode 2c via a gate insulating film 3, and a source line 6 on the semiconductor film 4. The source electrode 6c is a projecting portion projecting sideways, and the drain electrode 6d is provided on the semiconductor film 4 so as to face the source electrode 6c and is connected to the transparent pixel 5d. A protective layer 9 and a light shielding layer 10 are provided so as to cover the TFT 8. Further, in the semiconductor film 4, a channel portion 14 is provided in a region between the source electrode 6c and the drain electrode 6d corresponding to the gate electrode 2c.

  Since the counter substrate and the liquid crystal layer are the same as those in Embodiment 1, the description thereof is omitted.

  Next, a manufacturing method of the TFT array substrate 20c according to Embodiment 3 of the present invention will be described.

  As in the first embodiment, the first step (gate electrode forming step), the second step / laminated body forming step, the second step / resist pattern forming step 1, the second step / first etching step, the second step / resist. The substrate 20c5 is obtained by performing the pattern forming step 2 and the second step / second etching step.

<Third Step (Protective Layer / Pixel Electrode Formation Step)>
As in the first embodiment, a light-shielding dry film is prepared in advance.

  First, a silicon nitride film (thickness of about 2000 mm) is formed on the entire substrate 20c5 by plasma CVD to form a protective film.

  Next, after the cover film on one side of the prepared dry film is peeled off, the dry film is bonded to the substrate while pressing the surface on which the cover film is peeled off, and the other cover film is peeled off. Thereby, the resin film of the photosensitive resin in which carbon is dispersed is transferred onto the substrate, and a light shielding film is formed.

  The light-shielding film is not limited to a resin film of photosensitive resin in which carbon is dispersed, and any material that can obtain a desired OD value, taper shape, and dielectric constant, such as a pigment-dispersed black resist, may be used. . Further, in the present embodiment, the configuration in which the light shielding film is provided on the upper layer of the protective film is illustrated, but on the contrary, the configuration in which the light shielding film is provided on the lower layer of the protective film may be employed.

  In this way, by forming the light shielding layer on the upper layer or the lower layer of the protective film, the light shielding layer 10 is formed together with the formation of the protective layer 9. Thereby, the light shielding layer 10 can be formed without increasing the number of photolithography processes.

  Further, the protective film may have a one-layer structure of a black photoresist having a light-shielding property instead of a two-layer structure with the light-shielding film. In this case, the light shielding film can be omitted, and there is no need to provide a process for forming the light shielding film. Therefore, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  Here, the silicon nitride film is exemplified as the protective film, but a silicon oxide film may be used. Moreover, you may form a protective film by apply | coating resin films, such as a polyimide and an acrylic resin, and thermosetting. In particular, the resin film has a lower relative dielectric constant than that of the silicon nitride film, and the parasitic capacitance formed by the protective layer 9 between the peripheral edge of the reflective electrode 12 and the overlapping portion of the gate line 2 and the source line 6. Can be reduced.

  Next, the light shielding film formed on the entire substrate is exposed, developed, and post-baked using a photomask to form the light shielding layer 10.

  Next, using the light shielding layer 10 as a mask, the protective film inside the peripheral edge of the drain electrode is etched to form a drain electrode exposed portion and a protective layer 9 that covers the TFT 8. As a result, a substrate 20c6 as shown in FIG. 11C is obtained. The protective layer 9 and the light shielding layer 10 are formed so as to cover not only the TFT 8 but also the gate line 2 and the source line 6.

  Here, since the drain electrode exposed portion is formed by etching the protective film inside the peripheral edge of the drain electrode 6d, the protective film outside the peripheral edge of the drain electrode 6d is not etched. . Therefore, a large step cannot be formed, and conduction between the reflective electrode 12 and the transparent electrode 5d is ensured. On the other hand, when etching up to the protective film outside the peripheral edge of the drain electrode 6d, a large step with the conductive film as an upper layer is formed at the peripheral edge of the drain electrode 6d, and the conductive film is easily destroyed. Therefore, there is a possibility that conduction between the reflective electrode 12 and the transparent electrode 5d may be hindered.

<4th process (reflection electrode and transparent electrode formation process)>
First, an aluminum film (thickness of about 1000 mm) 12a is formed on the entire substrate 20c6 by sputtering. Here, since the aluminum film 12a is a material having a high reflectance and an excellent light shielding property, the reflective electrode 12 efficiently reflects ambient light and reliably blocks light incident on the TFT 8. can do. An aluminum alloy film may be used instead of the aluminum film.

  Next, a resist made of a photosensitive resin is applied to the entire substrate to form a resist layer.

  Next, the resist pattern formed on the resist layer formed on the entire substrate is exposed, developed, and post-baked using a photomask, and the conductive film inside the peripheral edge of the exposed portion of the drain electrode is etched. 7 is formed.

  Next, using the resist pattern 7 as a mask, the aluminum film 12a, the source first metal film 6a, and the source second metal film 6b are etched to form the reflective electrode 12 and the transparent electrode 5b. Thereby, the TFT array substrate 20c is obtained. Here, the conductive film inside the peripheral edge of the exposed portion of the drain electrode is etched to form the transparent electrode 5b, so that the transparent electrode and the reflective electrode are connected at the peripheral edge of the transparent electrode. . On the other hand, when the conductive film outside the peripheral edge of the exposed portion of the drain electrode is etched, not only is the connection between the transparent electrode and the reflective electrode impossible, but there is a gap between the transparent electrode and the reflective electrode. As a result, the transmittance and the reflectance are modulated around the gap.

  Further, since the light-shielding gate line 2 and the source line 6 are disposed between the reflective electrodes 12, the occurrence of light leakage between the reflective electrodes 12 is suppressed. In addition, the gate line 2 and the source line 6 also function as a light blocking pattern (black matrix) between the pixels. Normally, the black matrix is not required on the counter substrate disposed opposite to the TFT array substrate. The manufacturing process of the counter substrate is shortened. Furthermore, the occurrence of light leakage between pixels and light leakage current in the TFT due to the misalignment between the TFT array substrate and the counter substrate is suppressed.

  The gate line external lead terminal and the source line external lead terminal are formed simultaneously with the formation of the protective layer 9 and the pixel electrode 5a in the third step in the first embodiment. It is formed simultaneously with the formation of the reflective electrode 12 and the transparent electrode 5d. Since the contents are substantially the same as those of the first embodiment, a detailed description thereof is omitted. However, by etching in the fourth step, a portion of the aluminum film that easily corresponds to the gate line external extraction electrode is easily oxidized. Since the portions of the aluminum film and the molybdenum film that are easily oxidized corresponding to the source line external extraction electrode are removed at the same time, oxidation of the gate line external extraction electrode and the source line external extraction electrode can be prevented. Thereby, the manufacturing process of the TFT array substrate can be shortened and the manufacturing cost can be reduced.

  As described above, according to the manufacturing method of the present invention, the transflective TFT array substrate 20c is formed on the light shielding layer 10 covering the TFT 8, the black matrix between the pixels, the gate line external lead terminal, and the source line external lead terminal. Including the first step, the second step, the third step, and the fourth step. Therefore, it is possible to shorten the manufacturing process and the manufacturing cost of the transflective TFT array substrate.

<< Embodiment 4 of the Invention >>
The TFT array substrate 20d according to Embodiment 4 of the present invention will be described below.

  13, FIG. 14 and FIG. 15 are schematic cross-sectional views showing the manufacturing process of the TFT array substrate 20d corresponding to FIG. 10, FIG. 11 and FIG. FIG. 15B corresponds to a schematic cross-sectional view of the TFT array substrate 20d.

  The TFT array substrate 20d constitutes a liquid crystal display device together with a counter substrate provided so as to face each other and a liquid crystal layer provided so as to be sandwiched between the two substrates.

  The TFT array substrate 20d includes a plurality of gate lines 2 provided on the insulating substrate 1 so as to extend in parallel with each other and a plurality of gate lines provided in parallel with each other in a direction orthogonal to the gate lines 2. Source line 6. A TFT 8 is provided at each intersection between the gate line 2 and the source line 6. In addition, pixel electrodes (transparent electrode 5 d and reflective electrode 12) constituting pixels are provided in a display region surrounded by a pair of gate lines 2 and a pair of source lines 6 corresponding to each TFT 8. Here, the periphery of the transparent electrode 5d is the reflective electrode 12, and the transparent electrode 5d and the reflective electrode 12 constitute a pixel electrode. Furthermore, a gate line external lead terminal and a source line external lead terminal, which will be described later, are disposed at the ends of each gate line 2 and source line 6, respectively.

  The TFT 8 includes a gate electrode 2c having a protruding portion protruding laterally from the gate line 2, a semiconductor film 4 provided on the gate electrode 2c via a gate insulating film 3, and a source line 6 on the semiconductor film 4. The source electrode 5b is a projecting portion projecting sideways, and the drain electrode 6d is provided on the semiconductor film 4 so as to face the source electrode 5b and connected to the transparent pixel 5d. A protective layer 9 and a light shielding layer 10 are provided so as to cover the TFT 8. Further, in the semiconductor film 4, a channel portion 14 is provided in a region between the source electrode 6c and the drain electrode 6d corresponding to the gate electrode 2c.

  Since the counter substrate and the liquid crystal layer are the same as those in Embodiment 1, the description thereof is omitted.

  Next, a manufacturing method of the TFT array substrate 20d according to Embodiment 4 of the present invention will be described.

  As in the second embodiment, the first step (gate electrode forming step), the second step / laminated body forming step, the second step / resist pattern forming step 1, the second step / first etching step, the second step / resist. The substrate 20d5 is obtained by performing the pattern formation step 2 and the second step / second etching step.

<Third Step (Protective Layer / Pixel Electrode Formation Step)>
First, a silicon nitride film (thickness of about 2000 mm) is formed on the entire substrate 20d5 by plasma CVD to form a first protective film.

  Next, a photosensitive acrylic resin film (thickness of about 30000 mm) containing carbon powder is applied to the entire substrate on which the first protective film has been formed by spin coating.

  Next, two-stage exposure is performed as follows.

  Here, the exposed part of the photosensitive acrylic resin film is easily soluble.

  First, using a ray of h-rays (ultraviolet light having a wavelength of 405 nm), exposure is performed so that a half-exposure state is obtained with an exposure energy of 40 mJ, thereby forming a recess on the surface of the photosensitive acrylic resin.

  Next, only the part where the gate line external extraction electrode, source line external extraction electrode and transparent electrode are formed is completely exposed with an exposure energy of 240 mJ using h-ray light, developed and thermally cured, and the surface is uneven. A second protective layer 9b having a shape is formed.

  As described above, since the uppermost layer of the protective film is formed of a photosensitive resin film, the surface of the protective film can be easily formed into an uneven shape by adjusting the light amount and exposing the photosensitive resin. .

  The second protective layer 9b also functions as a light-shielding film because the photosensitive acrylic resin that is a constituent material contains carbon powder. In addition, since an organic film such as a photosensitive acrylic resin generally has a low relative dielectric constant, it is composed of a second protective layer 9b between the peripheral edge of the reflective electrode 12 and the overlapping portion of the gate line 2 and the source line 6. Can reduce the parasitic capacitance.

  Next, using the second protective layer 9b as a mask, the first protective film is etched to form a first protective layer 9a covering the TFT 8. As a result, a substrate 20d6 as shown in FIG. 11C is obtained.

  The first protective layer 9 a and the second protective layer 9 b are formed so as to cover not only the TFT 8 but also the gate line 2 and the source line 6. As a result, the second protective layer 9b having a light blocking property blocks light incident on the TFT 8 and functions as a light blocking pattern (black matrix) between the pixels. For this reason, a black matrix is usually unnecessary for the counter substrate disposed opposite to the TFT array substrate, and the manufacturing process of the counter substrate is shortened. Further, light leakage between the pixels due to a bonding deviation between the TFT array substrate and the counter substrate and generation of light leakage current in the TFT 8 are suppressed.

<4th process (reflection electrode and transparent electrode formation process)>
First, a molybdenum film (about 1000 mm thick) 12b and an aluminum film (about 1000 mm thick) 12a are formed on the entire substrate 20d6 by sputtering.

  Next, a resist made of a photosensitive resin is applied to the entire substrate to form a resist layer.

  Next, the resist layer formed on the entire substrate is exposed, developed, and post-baked using a photomask to form a resist pattern 7.

  Next, with the resist pattern 7 as a mask, the aluminum film 12a and the molybdenum film 12b are etched to form the reflective electrode 12 and the transparent electrode 5d.

  Here, since the surface of the reflective electrode 12 has a shape reflecting the irregular shape of the surface of the second protective layer 9b, the reflection direction of the light incident on the reflective electrode 12 is concentrated in the normal direction of the substrate surface. Can do. For this reason, the amount of light in the normal direction of the substrate surface increases, so that the reflectance of the reflective electrode 12 is substantially improved.

  Further, the molybdenum film 12b is interposed between the transparent conductive film 5 made of the ITO film and the aluminum film 12a constituting the reflective electrode 12. Therefore, when the aluminum film 12a is etched, the formation of a local battery between the aluminum film 12a and the transparent conductive film 5 is suppressed. Thereby, electrical corrosion (electric corrosion) between the aluminum film 12a and the transparent conductive film 5 can be prevented.

  Thereby, the TFT array substrate 20d is obtained.

  Note that the gate line external extraction electrode and the source line external extraction electrode were exposed simultaneously with the formation of the protective layer 9 and the pixel electrode 5a in the third step in the second embodiment, but in the present embodiment, in the fourth step. It is exposed simultaneously with the formation of the reflective electrode 12 and the transparent electrode 5d. FIG. 16 is a schematic cross-sectional view of the gate line external extraction electrode 2f, which is substantially the same as FIG. 8B of the second embodiment, and a description thereof will be omitted.

  As described above, according to the manufacturing method of the present invention, the transflective TFT array substrate 20c is formed on the light shielding layer 10 covering the TFT 8, the black matrix between the pixels, the gate line external lead terminal, and the source line external lead terminal. Including the first step, the second step, the third step, and the fourth step. Therefore, it is possible to shorten the manufacturing process and the manufacturing cost of the transflective TFT array substrate.

  As described above, the present invention is useful for a liquid crystal display device including a TFT array substrate because the manufacturing process can be shortened and the manufacturing cost can be reduced in the TFT array substrate.

It is a plane schematic diagram of the TFT array substrate 20a according to the first embodiment of the present invention. It is a cross-sectional schematic diagram which shows the manufacturing process (1/2) of the TFT array substrate 20a which concerns on Embodiment 1 of this invention, and respond | corresponds to the A-A 'cross section in FIG. It is a cross-sectional schematic diagram which shows the manufacturing process (2/2) of the TFT array substrate 20a which concerns on Embodiment 1 of this invention, and respond | corresponds to the A-A 'cross section in FIG. (A) is a plane schematic diagram of the edge part of TFT array substrate 20a concerning Embodiment 1 of the present invention, and shows gate line external extraction terminal 2d. (B) is a cross-sectional schematic diagram in the B-B 'cross section in (a). (A) is a plane schematic diagram of the edge part of TFT array substrate 20a concerning Embodiment 1 of the present invention, and shows source line outside lead-out terminal 6e. (B) is a cross-sectional schematic diagram in the C-C 'cross section in (a). It is a cross-sectional schematic diagram which shows the manufacturing process (1/2) of the TFT array substrate 20b which concerns on Embodiment 2 of this invention, and respond | corresponds to the cross-sectional schematic diagram of FIG. It is a cross-sectional schematic diagram which shows the manufacturing process (2/2) of the TFT array substrate 20b which concerns on Embodiment 2 of this invention, and respond | corresponds to the cross-sectional schematic diagram of FIG. (A) is a plane schematic diagram of the edge part of TFT array substrate 20b concerning Embodiment 2 of the present invention, and shows gate line outside extraction electrode 2f. (B) is a cross-sectional schematic diagram in the D-D 'cross section in (a). FIG. 6 is a schematic plan view of a TFT array substrate 20c according to Embodiment 3 of the present invention. It is a cross-sectional schematic diagram which shows the manufacturing process (1/3) of the TFT array substrate 20c which concerns on Embodiment 3 of this invention, and respond | corresponds to the E-E 'cross section in FIG. It is a cross-sectional schematic diagram which shows the manufacturing process (2/3) of the TFT array substrate 20c which concerns on Embodiment 3 of this invention, and respond | corresponds to the E-E 'cross section in FIG. It is a cross-sectional schematic diagram which shows the manufacturing process (3/3) of the TFT array substrate 20c which concerns on Embodiment 3 of this invention, and respond | corresponds to the E-E 'cross section in FIG. It is a cross-sectional schematic diagram which shows the manufacturing process (1/3) of TFT array substrate 20d which concerns on Embodiment 4 of this invention, and respond | corresponds to the cross-sectional schematic diagram of FIG. It is a cross-sectional schematic diagram which shows the manufacturing process (2/3) of TFT array substrate 20d which concerns on Embodiment 4 of this invention, and respond | corresponds to the cross-sectional schematic diagram of FIG. It is a cross-sectional schematic diagram which shows the manufacturing process (3/3) of TFT array substrate 20d which concerns on Embodiment 4 of this invention, and respond | corresponds to the cross-sectional schematic diagram of FIG. It is a cross-sectional schematic diagram of the edge part of the TFT array substrate 20d which concerns on Embodiment 4 of this invention corresponding to the cross-sectional schematic diagram of FIG.4 (b), and shows the gate line external extraction electrode 2f. It is a cross-sectional schematic diagram which shows the process of forming the gate line external extraction terminal 2d of the TFT array substrate 20a which concerns on Embodiment 1 of this invention, and respond | corresponds to the cross-sectional schematic diagram of FIG.4 (b). It is a cross-sectional schematic diagram which shows the process of forming a gate line external extraction terminal by the conventional method. It is a cross-sectional schematic diagram which shows the process of forming the source line external extraction terminal 6e of the TFT array substrate 20a which concerns on Embodiment 1 of this invention, and respond | corresponds to the cross-sectional schematic diagram of FIG.5 (b). It is a cross-sectional schematic diagram which shows the process of forming a source line external extraction terminal by the conventional method.

Explanation of symbols

1 Insulating Substrate 2 Gate Line 2a Gate First Metal Film 2b Gate Second Metal Film 2c Gate Electrode 2d Gate Line External Lead Terminal 2e Gate Third Metal Film 2f Gate Line External Lead Electrode 3 Gate Insulating Film 4a First Semiconductor Film 4b First 2 Semiconductor film 4 Semiconductor film 5 Transparent conductive film 5a Pixel electrode 5b, 6c Source electrode 5c, 6d, 6d 'Drain electrode 5d Transparent electrode 6 Source line 6a Source first metal film 6b Source second metal film 6f Source / drain formation portion 6e Source line external lead terminal 6g Source line external lead electrode 7 Resist pattern 7a First resist pattern 7b Second resist pattern 7c First opening 7d Second opening 8 TFT
9 protective layer 9a first protective layer 9b second protective layer 10 light shielding layers 11a, 11b, 11c opening 12 reflective electrode 12a aluminum film 12b molybdenum film 13 overhang part 14 channel parts 20a, 20b, 20c, 20d TFT array substrate

Claims (30)

A plurality of thin film transistors each including a plurality of pixels provided on a substrate and a semiconductor film that is disposed for each pixel and has a gate electrode, a source electrode, a drain electrode, and a semiconductor film in which a channel portion is formed corresponding to the gate electrode; A method of manufacturing a thin film transistor array substrate comprising a source line connected to the source electrode and a pixel electrode connected to the drain electrode,
A first step of patterning the gate electrode on the substrate by a photolithography method;
On the substrate on which the gate electrode is formed, a gate insulating film, the semiconductor film, and a conductive film including a transparent conductive film provided so as to cover the semiconductor film are stacked in this order to form a stacked body, A second step of patterning the thin film transistor by photolithography on the laminate;
Forming a protective layer covering the thin film transistor by photolithography, and forming a pixel electrode by exposing a part of the transparent conductive film,
In the second step, after forming a resist layer covering the stacked body, a region of the stacked body other than the portion that becomes the channel portion, the source line, the source electrode, and the drain electrode is formed on the resist layer. A resist pattern forming step of forming a first opening that exposes the conductive film at a position above and a second opening having a bottom having a predetermined thickness at a position above the region of the stacked body that becomes the channel portion; A first etching step of etching the conductive film exposed from the first opening and a semiconductor film below the conductive film; and a conductive film exposed by removing a bottom of the second opening And a second etching process for etching the thin film transistor array substrate. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
A method of manufacturing a thin film transistor array substrate, comprising a fourth step of patterning a reflective electrode by a photolithography method on the protective layer formed in the third step. In the manufacturing method of the thin film transistor array substrate according to claim 1,
The conductive film has a light shielding property,
A method of manufacturing a thin film transistor array substrate, wherein the conductive film inside the peripheral edge of the drain electrode is etched in the third step. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
The semiconductor film includes an upper first semiconductor film and a lower second semiconductor film,
The thin film transistor array substrate, wherein the exposed conductive film and the first semiconductor layer are etched in the second etching step. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
On the upper layer or lower layer of the protective layer, a light shielding layer is formed,
The method of manufacturing a thin film transistor array substrate, wherein the light shielding layer is formed simultaneously with the protective layer in the third step. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
The method for manufacturing a thin film transistor array substrate, wherein the protective layer is formed of a light shielding material. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
The gate electrode is formed of a first metal laminated film formed by laminating a plurality of metal films,
The method of manufacturing a thin film transistor array substrate, wherein the first metal laminated film includes a metal film made of an aluminum film or an aluminum alloy film. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
The method of manufacturing a thin film transistor array substrate, wherein the conductive film is composed of a single layer made of only the transparent conductive film. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
The conductive film is a second metal laminate film formed by laminating the transparent conductive film composed of a compound of indium oxide and tin oxide and a plurality of metal films provided to cover the transparent conductive film. And formed by
The method of manufacturing a thin film transistor array substrate, wherein the second metal laminated film is formed of a lower molybdenum film or molybdenum alloy film and an upper aluminum film or aluminum alloy film. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
The method of manufacturing a thin film transistor array substrate, wherein the semiconductor film is formed of a material having higher light transmittance than amorphous silicon having the same thickness. In the manufacturing method of the thin film transistor array substrate according to claim 1 or 2,
In the first step, a plurality of gate lines connected to the gate electrode and a gate line external extraction electrode which is an extension portion thereof are formed simultaneously with the gate electrode, and the method of manufacturing a thin film transistor array substrate . In the manufacturing method of the thin film transistor array substrate according to claim 11,
The gate electrode, the gate line, and the gate line external extraction electrode are formed of a first metal laminated film formed by laminating a plurality of metal films,
The lowermost layer of the first metal laminated film is formed of a titanium film or a titanium alloy film,
In the third step, the portion of the titanium film or titanium alloy film corresponding to the gate line external extraction electrode is exposed by etching. The method of manufacturing a thin film transistor array substrate according to claim 12,
The first metal laminated film includes a lowermost titanium film or a titanium alloy film, a metal film composed of an aluminum film or an aluminum alloy film, and a molybdenum film or a molybdenum alloy film provided so as to cover the metal film. And a method of manufacturing a thin film transistor array substrate. In the manufacturing method of the thin film transistor array substrate according to claim 11,
The gate electrode, the gate line, and the gate line external extraction electrode are formed of a first metal laminated film configured by laminating a plurality of metal films,
A method of manufacturing a thin film transistor array substrate, wherein an uppermost layer of the first metal laminated film is formed of a titanium film or a titanium alloy film. The method of manufacturing a thin film transistor array substrate according to claim 14,
The first metal laminated film includes an aluminum film or an aluminum alloy film,
In the third step, the method of manufacturing a thin film transistor array substrate includes etching the protective layer and the gate insulating film inside the peripheral edge of the gate line external extraction electrode. In the method for manufacturing a thin film transistor array substrate according to claim 1, 2, or 11,
In the second step, the plurality of source lines and a source line external extraction electrode as an extension portion thereof are formed simultaneously with the source electrodes in a direction intersecting with the plurality of gate lines. A method for manufacturing an array substrate. The method of manufacturing a thin film transistor array substrate according to claim 16,
The gate electrode, the gate line, and the gate line external extraction electrode are formed of a first metal laminated film configured by laminating a plurality of metal films,
The source electrode, the source line, and the source line external extraction electrode are formed of a second metal laminated film formed by laminating a plurality of metal films,
In the third step, at least an uppermost layer of the first metal laminated film and the second metal laminated film corresponding to the gate line external extraction electrode and the source line external extraction electrode is removed by etching. A method of manufacturing a thin film transistor array substrate. The method of manufacturing a thin film transistor array substrate according to claim 17,
The uppermost layer of the first and second metal laminated films is formed of an aluminum film or an aluminum alloy film, or a film formed by laminating a molybdenum film or a molybdenum alloy film on the aluminum film or the aluminum alloy film. A method of manufacturing a thin film transistor array substrate. The method of manufacturing a thin film transistor array substrate according to claim 16,
The method for manufacturing a thin film transistor array substrate, wherein the protective layer has a light shielding property and is formed so as to cover the thin film transistor, the gate line, and the source line. The method of manufacturing a thin film transistor array substrate according to claim 16,
In the third step, a plurality of gate line external extraction electrodes are formed by etching to form one opening corresponding to at least one of the plurality of gate line external extraction electrodes and the plurality of source line external extraction electrodes. And a method of manufacturing a thin film transistor array substrate, wherein a plurality of source line external extraction electrodes are exposed. In the manufacturing method of the thin film transistor array substrate according to claim 1,
In the third step, the method of manufacturing a thin film transistor array substrate includes etching the protective film for forming the protective layer in the region outside the peripheral edge of the drain electrode and the gate insulating film. In the manufacturing method of the thin film transistor array substrate according to claim 2,
The method for producing a thin film transistor array substrate, wherein the uppermost layer of the protective layer is formed of a photosensitive resin film, and the surface thereof is formed in an uneven shape in the third step. The method of manufacturing a thin film transistor array substrate according to claim 22,
The method of manufacturing a thin film transistor array substrate, wherein the surface of the reflective electrode is formed in a shape reflecting the irregular shape of the surface of the protective layer. In the manufacturing method of the thin film transistor array substrate according to claim 2,
In the third step, a protective film covering the thin film transistor is formed, and the protective film inside the peripheral edge of the drain electrode is etched to expose the conductive film constituting the drain electrode. Forming a thin film transistor array substrate. In the manufacturing method of the thin film transistor array substrate according to claim 24,
In the fourth step, the transparent electrode is formed by etching the conductive film on the inner side of the peripheral edge of the drain electrode exposed portion. In the manufacturing method of the thin film transistor array substrate according to claim 2,
The method of manufacturing a thin film transistor array substrate, wherein the reflective electrode is formed of an aluminum film or an aluminum alloy film. In the manufacturing method of the thin film transistor array substrate according to claim 2,
The conductive film is formed of a single layer of only a transparent conductive film formed of a compound of indium oxide and tin oxide,
The method of manufacturing a thin film transistor array substrate, wherein the reflective electrode is formed of two layers of a lower molybdenum film or molybdenum alloy film and an upper aluminum film or aluminum alloy film. In the manufacturing method of the thin film transistor array substrate according to claim 2,
In the first step, a plurality of gate lines connected to the gate electrode and a gate line external extraction electrode which is an extension portion thereof are formed simultaneously with the gate electrode,
In the second step, a plurality of source lines connected to the source electrode and a source line external extraction electrode as an extension portion thereof are formed simultaneously with the source electrode in a direction intersecting with the plurality of gate lines. With
The gate line and the source line have light shielding properties,
The method of manufacturing a thin film transistor array substrate, wherein the reflective electrode is formed so that a peripheral end thereof overlaps the gate line and the source line. The method of manufacturing a thin film transistor array substrate according to claim 28,
The method for manufacturing a thin film transistor array substrate, wherein the protective layer includes an organic film. The method of manufacturing a thin film transistor array substrate according to claim 28,
The first metal laminated film constituting the gate electrode is composed of a lowermost titanium film or a titanium alloy film, and an aluminum film or an aluminum alloy film,
The conductive film includes a transparent conductive film, a molybdenum film or a molybdenum alloy film provided so as to cover the transparent conductive film, an aluminum film or an aluminum alloy film provided so as to cover the molybdenum film or the molybdenum alloy film, And composed of
The reflective electrode is composed of two layers of a lower molybdenum film or molybdenum alloy film and an upper aluminum film or aluminum alloy film,
In the fourth step, the portion of the titanium film or titanium alloy film corresponding to the gate line external extraction electrode is exposed by etching, and the portion of the transparent conductive film corresponding to the source line external extraction electrode is exposed. A method of manufacturing a thin film transistor array substrate.

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