KR100233151B1 - Fabrication method of thin film transistor panel - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor substrate, and more particularly, to a method of manufacturing a thin film transistor substrate on which a thin film transistor as a switching element is formed in a flat panel display device. In the method of manufacturing a substrate of the thin film transistor according to the present invention, by using the dry etching method, the metal film and the amorphous silicon layer are simultaneously etched continuously to reduce the complicated process, and the tapering process can be performed in the range of 85 ° or less. Since the widths of the gate lines and the data lines can be adjusted appropriately, disconnection can be prevented.

Description

Method of manufacturing thin film transistor substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate on which a thin film transistor that is a switching element in a flat panel display device is formed.

In general, a liquid crystal display includes a thin film transistor substrate in which a plurality of pixel units in which a thin film transistor and a pixel electrode are formed are formed in a matrix form, and a gate line and a data line are formed along a pixel row and a pixel column, respectively. It includes a color filter substrate on which a common electrode is formed, and a liquid crystal material enclosed therebetween.

In such a liquid crystal display, low-resistance materials such as aluminum (Al), copper (Cu), molybdenum (Mo), or molybdenum alloy (Mo alloy) are used to form gate lines and data lines.

Further, many researches have been made on materials for gate, drain, and source electrodes of thin film transistors, which are switching elements used in liquid crystal displays, and some of them have been applied in practice.

However, a material such as copper has a problem in that adhesion between the glass substrate and the insulating film is weak, dry etching is very difficult, and like aluminum, it is easily oxidized in the air. In particular, as the thickness of copper increases, there is a problem in taper etching during wet etching, which makes it difficult to use it as a signal line or an electrode. Molybdenum, molybdenum alloys, or chromium or the like are suitable as pad materials because they have a low specific resistance and can reduce the possibility of disconnection even in the process conditions of the display device. However, molybdenum is difficult to process such as taper processing with gentle slope, surface uniformity, etching ratio, and etching selectivity without wet chemical etching.

In addition, in recent years, a method for reducing the number of processes has been developed in the method of manufacturing a liquid crystal display, and a method of manufacturing a thin film transistor substrate using four masks has been developed.

In this case, in a method of manufacturing a thin film transistor substrate using a four-mask, a process of simultaneously etching a metal layer when etching an amorphous silicon layer for forming a semiconductor layer is needed, and etching an amorphous silicon layer to form a channel portion of the semiconductor layer. At the same time, a process of forming a source / drain electrode by simultaneously etching a central portion of the metal layer is required.

However, when etching the metal film and the amorphous silicon layer at the same time in the process of forming the source layer and the drain electrode semiconductor layer and the channel portion of the semiconductor layer, when the two layers of different physical properties are etched at the same time, an under cut This occurs, so the wet etching and dry etching must be performed in turn, there is a hassle. In addition, when the metal layer is formed of molybdenum or molybdenum alloy and the non-geographic silicon layer and the metal layer are patterned by wet etching at the same time, a taper process having a gentle slope is difficult, and thus a complementary process is required.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and to provide a taper process having a gentle slope while reducing a complex process in applying a four-sheet mask process.

1 is a plan view showing the structure of a general thin film transistor substrate.

2 is a cross-sectional view illustrating a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention according to a process sequence thereof.

In the method of manufacturing a thin film transistor substrate according to the present invention, dry etching is performed simultaneously with the metal layer and the semiconductor layer in a process of forming an amorphous silicon layer and an ohmic contact layer as a semiconductor layer and forming a source / drain electrode with a metal layer. Patterning method.

Here, a gas used for dry etching uses a mixed gas such as SF ₆ / O ₂ / Ar or Cl ₂ / O ₂ / Ar.

In the method of manufacturing a thin film transistor substrate according to the present invention, when the amorphous silicon layer and the metal layer are simultaneously etched through the dog etching method, taper processing having a smooth inclined surface can be performed, and the taper angle can be formed within a range of 85 ° or less. have. In addition, the process conditions may be adjusted to prevent undercuts from occurring, the width of the wiring may be adjusted to prevent disconnection, and the characteristics of the material forming the etchant and the source / drain electrodes may not be particularly considered.

Next, an embodiment of a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains may easily implement the present invention.

1 is a plan view showing the structure of a general thin film transistor substrate.

FIG. 1 is a plan view illustrating a structure of a thin film transistor substrate, in which a gate line 20 and a data line 60 defining a pixel portion are formed to cross each other, and a pixel electrode 80 is formed on the pixel portion. ) Is formed. The TFT portion is formed at the portion where the gate line 20 and the data line 60 cross each other, and a thin film transistor including a gate electrode 21, a source electrode 62, and a drain electrode 61 is formed in the TFT portion. One side of the data line 60 has a data pad portion, which is a path through which data signals are transmitted from the outside, a data pad 63 is formed at the data pad portion, and one side of the gate line 20 has a scan signal. There is a gate pad portion serving as a path, and a gate pad 22 is formed in the gate pad portion.

FIG. 2 is a cross-sectional view illustrating a portion A-A in FIG. 1 and illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention, in the order of their processes.

As shown in FIG. 2A, a metal material having low resistance is deposited on the substrate 10 and photo-etched using the first mask to form the gate electrode 21, the gate line 20, and the gate pad. (22) is formed (see FIG. 2).

As shown in FIG. 2 (b), a gate insulating film 30 made of an oxide film or a nitride film, an amorphous silicon layer, a highly concentrated N-type exogenous amorphous silicon layer as a contact layer, and a metal film as a source / drain electrode are sequentially stacked. Next, a photolithography process is performed using a second mask, and the metal film, the exogenous amorphous silicon layer, and the amorphous silicon layer are sequentially and simultaneously etched using a dry etching method using the remaining photoresist as a mask. ), The semiconductor layer 40 and the contact layer 50 are formed. At this time, the data pad 63 and the data line 60 are also simultaneously formed in the same pattern as the amorphous silicon layer (see FIG. 2).

Next, as shown in FIG. 2 (c), after laminating ITO which is a transparent conductive material, a photoresist is performed using a third mask, and a portion of the ITO film is etched using the remaining photoresist as a mask. The pixel electrode 80 is formed. At this time, the ITO film formed on the center portion of the metal film 600 and the upper portion of the gate pad 22 is removed at the same time. Using the ITO film, part of which is the pixel electrode 80 as a mask, the center portions of the metal film 60 and the contact layer 50 are etched by dry etching to form the source / drain electrodes 61 and 62, and the semiconductor layer ( 40) expose the central part (see Figure 2).

Here, the materials of the source / drain electrodes 61 and 52 and the data line 60 may be used as molybdenum, molybdenum alloy, titanium, tantalum, and chromium chromium, which may have low resistance and may be simultaneously etched with an amorphous silicon layer. In the case of forming a double film, aluminum and an aluminum alloy may be added.

In addition, the gas used for dry etching is preferably SF ₆ / O ₂ / Ar or Cl ₂ / O ₂ / Ar.

In this case, when the source / drain electrodes 61 and 62 and the data line 60 are formed by dry etching, the taper angle may be less than 85 °.

Finally, as shown in FIG. 2 (d), the protective film 70 is formed by laminating a nitride film or an oxide film on the substrate 10. As shown in FIG. At this time, the gate pad 22 and the upper portion of the data pad 63 are simultaneously removed using the fourth mask (see FIG. 2).

In the thin film transistor substrate according to the second exemplary embodiment of the present invention, the gate electrode 20 is formed on the transparent insulating substrate 10. The gate insulating film 30 having an opening on the gate pad 22 covers the substrate 10, and the semiconductor layer 40 and the contact on the gate insulating film 30 corresponding to the gate electrode 21. The layer 50 and the source / drain electrodes 61 and 62 are formed in the same width. In addition, a pixel electrode 80 having an opening on the gate electrode 21 is formed on the substrate 10, and a passivation layer 70 having an opening on the gate pad 22 and the data pad 63. ) Is formed.

Therefore, in the method of manufacturing a thin film transistor substrate according to the present invention, by using the dry etching method to simultaneously and continuously etch the metal film and the amorphous silicon layer can reduce the complicated process, can be tapered in the range of 85 ° or less, Since the widths of the gate lines and the data lines can be adjusted appropriately, disconnection can be prevented.

Claims (6)

Stacking a metal film on a substrate, patterning the metal film with a first mask to form a gate line, a gate pad, and a gate electrode; forming a gate insulating film, an amorphous silicon layer, an amorphous silicon layer and a metal layer doped with high concentration impurities on the substrate. Sequentially stacking, sequentially etching a portion of the amorphous silicon layer, the amorphous silicon layer doped with a high concentration impurity, and the metal film using a second mask using a dry etching method, and depositing a transparent conductive film on the substrate Forming a pixel electrode having an opening on the metal layer using a third mask, and simultaneously etching the high concentration amorphous silicon layer and the metal layer using the pixel electrode as a mask to continuously contact the source layer and the source / drain electrode; Forming a data pad and a data line on the substrate And etching the gate insulating film and the passivation layer on the gate pad using a fourth mask after forming the passivation layer. The method of claim 1, wherein the dry etching method comprises a gas consisting of SF ₆ / O ₂ / Ar. The method of claim 2, wherein the metal film is formed of molybdenum, molybdenum alloy, titanium, tantalum, tungsten, or chromium. The method of claim 3, wherein the metal layer and the amorphous silicon layer are formed in the same pattern. The method of claim 4, wherein a taper angle between the source / drain electrodes and the data line is formed to be 85 ° or less. Stacking a metal film on a substrate, patterning the metal film with a first mask to form a gate line, a gate pad, and a gate electrode; forming a gate insulating film, an amorphous silicon layer, an amorphous silicon layer and a metal layer doped with high concentration impurities on the substrate. Sequentially stacking, sequentially etching a portion of the amorphous silicon layer, the amorphous silicon layer doped with a high concentration impurity, and the metal film using a second mask using a dry etching method, and depositing a transparent conductive film on the substrate And forming a pixel electrode having an opening on the metal layer using a third mask, using the pixel electrode as a mask, simultaneously etching the high concentration amorphous silicon layer and the metal layer by a dry etching method to simultaneously contact the source layer and the source. To form drain / drain electrodes, data pads and data lines A method for manufacturing a liquid crystal display thin film transistor substrate for which the gate pad upper portion by using a fourth mask after forming the protective film on the substrate includes the step of photo etching the gate insulating film and the protective film.

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