CN111128877B - Preparation method of etching barrier type array substrate - Google Patents
Preparation method of etching barrier type array substrate Download PDFInfo
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- CN111128877B CN111128877B CN201911352202.1A CN201911352202A CN111128877B CN 111128877 B CN111128877 B CN 111128877B CN 201911352202 A CN201911352202 A CN 201911352202A CN 111128877 B CN111128877 B CN 111128877B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
Abstract
The invention provides a preparation method of an etching barrier type array substrate, which comprises the following steps: preparing a grid electrode layer and a grid electrode insulating layer on a substrate; sequentially depositing a metal oxide semiconductor film and an etching stopper film on the gate insulating layer; forming a photoresist pattern on the etching barrier film, wherein the photoresist pattern comprises a first photoresist positioned in the display area and a second photoresist positioned in the fan-out area, the first photoresist comprises a middle part and a side part connected with the middle part, and the thickness of the side part is less than that of the middle part; respectively adopting wet etching to remove the etching barrier film and the metal oxide semiconductor film which are not protected by the light resistance; removing the side part by adopting dry etching, and thinning the middle part and the second light resistance; removing the etching barrier film which is not protected by the middle part by wet etching; stripping off the residual photoresist to obtain a patterned active layer and an etching barrier layer; and sequentially preparing a source drain layer, a passivation layer and a pixel electrode layer. One photomask process is saved, and the active layer channel region is protected from erosion and damage.
Description
Technical Field
The invention relates to the field of display, in particular to a preparation method of an etching barrier type array substrate.
Background
The etching barrier type thin film transistor is protected by the etching barrier layer, so that the damage of source-drain back channel etching to the active layer is avoided, good stability is presented, and the etching barrier type thin film transistor is widely applied to array substrates.
However, in the process of etching the barrier array substrate, the photoresist stripper will erode the active layer, resulting in an increase in the surface roughness of the active layer; meanwhile, the photo-resist yellow light and the stripping process can also increase the defect state of the oxygen vacancy of the active layer, so that the performance of the device is reduced; in addition, the manufacturing process of the etching type array substrate has more photomask processes and higher cost.
Therefore, the existing preparation process of the etching barrier type array substrate has defects and needs to be improved.
Disclosure of Invention
The invention provides a preparation method of an etching barrier type array substrate, which is used for overcoming the defects of the existing preparation process of the etching barrier type array substrate.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides a preparation method of an etching barrier type array substrate, which comprises the following steps:
preparing a grid electrode layer and a grid electrode insulating layer on a substrate in sequence;
depositing a metal oxide semiconductor film and an etching barrier film in this order on the gate insulating layer;
coating a layer of light resistance on the etching barrier film;
exposing and developing the photoresist by using a half-tone photomask to form a photoresist pattern; the photoresist pattern comprises a first photoresist positioned in a display area and a second photoresist positioned in a fan-out area, the first photoresist comprises a middle part and a side part positioned on the side edge of the middle part and connected with the middle part, and the thickness of the side part is smaller than that of the middle part;
etching and removing the etching barrier film which is not protected by the first light resistor and the second light resistor by adopting a hydrofluoric acid medicament wet etching process;
etching and removing the metal oxide semiconductor film which is not protected by the first light resistor and the second light resistor by adopting an oxalic acid series medicament wet etching process;
etching and removing the side parts by adopting a dry etching process, and etching and thinning the middle part and the second light resistance;
etching and removing the etching barrier film which is not protected by the middle part by adopting an oxalic acid series medicament wet etching process;
stripping off the residual photoresist to obtain a patterned active layer and an etching barrier layer;
and sequentially preparing a source drain layer, a passivation layer and a pixel electrode layer on the etching barrier layer.
In the preparation method provided by the invention, the thickness of the middle part is 1.4-2.5 um, and the thickness of the side part is 0.5-0.8 um.
In the preparation method provided by the present invention, the step of sequentially depositing a metal oxide semiconductor film and an etching stopper film on the gate insulating layer includes:
depositing a layer of the metal oxide semiconductor film on the gate insulating layer by adopting a physical vapor sputtering method;
and depositing an etching barrier film on the metal oxide semiconductor film by using a plasma chemical vapor method.
In the preparation method provided by the invention, the material of the metal oxide semiconductor film is any one of indium gallium zinc oxide, indium zinc oxide and indium gallium zinc tin oxide.
In the preparation method provided by the invention, the etching barrier film is any one of a silicon oxide film, a laminated structure of a silicon oxide film and a silicon nitride film.
In the preparation method provided by the invention, the photoresist coated on the etching barrier film is any one of a positive photoresist and a negative photoresist.
In the preparation method provided by the invention, the step of forming the photoresist pattern by exposing and developing the photoresist by using the halftone mask comprises the following steps:
exposing the positive photoresist by using a first halftone photomask as a mask;
and developing the exposed positive photoresist by adopting an alkaline developing solution, removing the exposed photoresist and keeping the unexposed photoresist.
In the preparation method provided by the invention, the step of forming the photoresist pattern by exposing and developing the photoresist by using the halftone mask comprises the following steps:
exposing the negative photoresist by using a second halftone photomask as a mask;
and developing the exposed negative photoresist by using an alkaline developing solution, removing the unexposed photoresist and keeping the exposed photoresist.
In the preparation method provided by the invention, the step of sequentially preparing the gate electrode layer and the gate insulating layer on the substrate comprises the following steps:
depositing a layer of metal conductive film on the substrate by adopting a physical vapor sputtering method;
patterning the metal conductive film by adopting a one-time photoetching process to form a gate layer;
and depositing an insulating film layer on the gate electrode layer by adopting a plasma chemical vapor method to serve as a gate insulating layer.
In the preparation method provided by the invention, the step of sequentially preparing the source drain layer, the passivation layer and the pixel electrode layer on the etching barrier layer comprises the following steps:
depositing a layer of metal conductive film on the etching barrier layer by adopting a physical vapor sputtering method; patterning the metal conductive film by adopting a one-time photoetching process to form a source drain layer;
depositing an insulating film layer on the source drain layer by adopting a plasma chemical vapor method; etching a preset area of the insulating film layer by adopting a one-time photoetching process to form a passivation layer;
depositing a layer of metal conductive film on the passivation layer by adopting a physical vapor sputtering method; and patterning the metal conductive film by adopting a one-time photoetching process to form a pixel electrode layer.
The invention has the beneficial effects that: the invention provides a preparation method of an etching barrier type array substrate, which comprises the following steps: preparing a grid electrode layer and a grid electrode insulating layer on a substrate in sequence; depositing a metal oxide semiconductor film and an etching stopper film in this order on the gate insulating layer; coating a layer of light resistance on the etching barrier film; exposing and developing the photoresist by using a half-tone photomask to form a photoresist pattern; the photoresist pattern comprises a first photoresist positioned in the display area and a second photoresist positioned in the fan-out area, the first photoresist comprises a middle part and a side part positioned on the side edge of the middle part and connected with the middle part, and the thickness of the side part is less than that of the middle part; etching and removing the etching barrier film which is not protected by the first light resistance and the second light resistance by adopting a hydrofluoric acid medicament wet etching process; etching and removing the metal oxide semiconductor film which is not protected by the first light resistance and the second light resistance by adopting an oxalic acid series medicament wet etching process; etching and removing the side part by adopting a dry etching process, and etching and thinning the middle part and the second light resistance; etching and removing the etching barrier film which is not protected by the middle part by adopting an oxalic acid series medicament wet etching process; stripping off the residual photoresist to obtain a patterned active layer and an etching barrier layer; and sequentially preparing a source drain electrode layer, a passivation layer and a pixel electrode layer on the etching barrier layer. The method saves a photomask manufacturing process, saves the manufacturing cost, protects the channel region of the active layer from yellow light and liquid medicine in the etching manufacturing process, reduces the risk of interface defects of the channel region and the etching barrier layer, and improves the performance of the etching barrier type array substrate.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart illustrating a process of fabricating an etch barrier array substrate according to an embodiment of the present invention.
Fig. 2(a) to 2(j) are schematic views illustrating a manufacturing method of an etching barrier type array substrate according to an embodiment of the present invention.
Detailed Description
While the embodiments and/or examples of the present invention will be described in detail below in conjunction with the specific embodiments of the present invention, it is to be understood that the embodiments and/or examples described below are only a part of the embodiments and/or examples of the present invention, and not all of the embodiments and/or examples. All other embodiments and/or examples, which can be obtained by a person skilled in the art without inventive step, are within the scope of protection of the present invention.
Directional terms used in the present invention, such as [ upper ], [ lower ], [ left ], [ right ], [ front ], [ rear ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terminology is used for the purpose of describing and understanding the invention and is in no way limiting. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature.
Aiming at the problem that the existing preparation process of the etching barrier type array substrate has defects, the invention provides a preparation method of the etching barrier type array substrate, which can relieve the problem.
In an embodiment, referring to fig. 1, fig. 1 is a flowchart illustrating a process for manufacturing an etch barrier array substrate according to an embodiment of the invention. The preparation method of the etching barrier type array substrate provided by the invention comprises the following steps:
s101, preparing a grid layer and a grid insulating layer on a substrate in sequence;
step S102, depositing a metal oxide semiconductor film and an etching barrier film on the gate insulating layer in sequence;
step S103, coating a layer of light resistance on the etching barrier film;
step S104, exposing and developing the photoresist by adopting a half-tone photomask to form a photoresist pattern;
step S105, etching and removing the etching barrier film which is not protected by the first light resistance and the second light resistance by adopting a hydrofluoric acid medicament wet etching process;
step S106, etching and removing the metal oxide semiconductor film which is not protected by the first light resistance and the second light resistance by adopting an oxalic acid series medicament wet etching process;
step S107, etching and removing the side part by adopting a plasma dry etching process, and etching and thinning the middle part and the second light resistance;
step S108, etching and removing the etching barrier film which is not protected by the middle part by adopting an oxalic acid series medicament wet etching process;
step S109, stripping the residual photoresist to obtain a patterned active layer and an etching barrier layer;
step S110, preparing a source drain electrode layer, a passivation layer and a pixel electrode layer on the etching barrier layer in sequence.
The embodiment provides a preparation method of an etching barrier type array substrate, which not only saves a photomask manufacturing process and manufacturing cost, but also protects an active layer channel region from being corroded and damaged by yellow light and liquid medicine in the etching manufacturing process, so that the risk of interface defects of the channel region and the etching barrier layer is reduced, and the performance of the etching barrier type array substrate is improved.
In one embodiment, referring to fig. 2(a), the step S101 of sequentially depositing a gate layer and a gate insulating layer on a substrate includes:
a substrate 201 is provided. In order to prevent harmful substances, such as alkali metal ions and other impurities, from affecting the properties of the polycrystalline silicon thin film layer, the substrate needs to be cleaned. The substrate may be a rigid substrate such as glass or may be a flexible substrate. The flexible substrate generally includes a first flexible substrate, a second flexible substrate, and an inorganic layer positioned between the first flexible substrate and the second flexible substrate; the first flexible substrate and the second flexible substrate are made of acetamide or polyethylene terephthalate and are used for ensuring the flexibility of the flexible substrates; the inorganic layer is made of silicon nitride or silicon oxide and is used for preventing water or oxygen outside the array substrate from entering the thin film transistor.
A gate layer 202 is deposited over a substrate 201. Sputtering a layer of metal conductive film on a substrate by adopting a physical vapor sputtering method, particularly a magnetron sputtering method, wherein the metal conductive film can be metal molybdenum, metal aluminum, metal copper, the composition of metal molybdenum and metal aluminum or the composition of metal molybdenum and metal copper; preparing a grid electrode and a grid electrode line through a photoetching process, specifically, depositing a photoresist layer on a metal film, exposing the photoresist layer by adopting a set of grid mask plate, and then developing the exposed photoresist by using a developing solution to obtain a grid electrode layer pattern; then, wet etching is carried out on the exposed metal film, and the metal film without the protection of the photoresist is removed; and then carrying out plasma ashing stripping removal on the residual photoresist, wherein the remained metal conductive film is the patterned gate layer.
A gate insulating layer 203 is deposited over the gate layer 202. An insulating film layer is deposited on the gate electrode layer by using a plasma chemical vapor deposition method, and the insulating film layer covers the gate electrode layer 202 and the substrate 201. The insulating film layer may be a single-layer silicon nitride film or a laminated film of silicon oxide/silicon nitride. The silicon nitride has higher breakdown voltage and can be used as a good grid electrode insulating material, the silicon oxide and the surface of the polycrystalline silicon have good crystal boundary matching and stress matching, and meanwhile, the silicon oxide has good step coverage.
In one embodiment, as shown in fig. 2(b), the step S102 of sequentially depositing a metal oxide semiconductor film and an etching stopper film on the gate insulating layer includes:
a metal oxide semiconductor film 204 is deposited on the gate insulating layer by a physical vapor sputtering method, specifically, a magnetron sputtering method, and the material of the metal oxide semiconductor film 204 is any one of metal oxides such as indium gallium zinc oxide, indium gallium zinc tin, and the like.
An etching stopper film 205 is deposited on the metal oxide semiconductor film by a plasma chemical vapor deposition method, and the etching stopper film 205 is any one of a silicon oxide film, and a silicon nitride film in a stacked structure.
In one embodiment, the photoresist coated on the etching barrier film in step S103 may be a positive photoresist or a negative photoresist.
In one embodiment, when the photoresist coated on the etching barrier film is a positive photoresist, the step S104 exposes and develops the photoresist using a half-tone mask, and the step of forming the photoresist pattern includes:
and adopting the first halftone photomask as a mask plate to perform exposure treatment on the positive photoresist.
And developing the exposed positive photoresist by using an alkaline developing solution to remove the completely-illuminated positive photoresist and leave the non-illuminated and semi-illuminated positive photoresist to obtain a first photoresist pattern. As shown in fig. 2(c), the first photoresist pattern includes a first photoresist in the display region and a second photoresist 2063 in the fan-out region, the first photoresist including a middle portion 2061 and side portions 2062 connected to the middle portion 2061 at sides of the middle portion 2061; the thickness of the side portions 2062 is smaller than that of the middle portion 2061, the thickness of the middle portion 2061 is 1.4-2.5 um, and the thickness of the side portions 2062 is 0.5-0.8 um.
In another embodiment, when the photoresist coated on the etching barrier film is a negative photoresist, the step S104 exposes and develops the photoresist by using a half-tone mask, and the step of forming the photoresist pattern includes:
and exposing the negative photoresist by using the second half-tone photomask as a mask.
And developing the exposed negative photoresist by using an alkaline developing solution, removing the non-illuminated negative photoresist, and leaving the fully-illuminated and semi-illuminated negative photoresist to obtain a first photoresist pattern. As shown in fig. 2(c), the first photoresist pattern includes a first photoresist in the display region and a second photoresist 2063 in the fan-out region, the first photoresist including a middle portion 2061 and side portions 2062 connected to the middle portion 2061 at the sides of the middle portion 2061; the thickness of the side portions 2062 is smaller than that of the middle portion 2061, the thickness of the middle portion 2061 is 1.4-2.5 um, and the thickness of the side portions 2062 is 0.5-0.8 um.
In one embodiment, as shown in fig. 2(d), in step S105 and step S106, a hydrofluoric acid-based chemical wet etching process and an oxalic acid-based chemical wet etching process are sequentially adopted to etch and remove the etching barrier film and the metal oxide semiconductor film which are not protected by the first photoresist and the second photoresist, so as to obtain the remaining etching barrier film and the remaining metal oxide semiconductor film with the same pattern.
In one embodiment, as shown in fig. 2(e), in step S107, a plasma dry etching process is used to etch and remove the side portions 2601, and etch and thin the middle portion 2062 and the second photoresist 2063 to form a second photoresist pattern; the second photoresist pattern includes a thinned middle portion 2064 and a thinned second photoresist 2065. While exposing the etch stop film protected by the side portions.
In one embodiment, as shown in fig. 2(f), in step S108, an oxalic acid-based chemical wet etching process is used to etch and remove the etching barrier film that is not protected by the middle portion.
In one embodiment, as shown in fig. 2(g), the step S109 strips off the remaining photoresist to obtain the patterned active layer and the etch stop layer, and the remaining middle portion 2064 and the second photoresist 2065 are removed by a plasma dry etching process.
Therefore, the active layer and the etching barrier layer with complete patterns are obtained, and in the whole active layer preparation and patterning process, the etching barrier layer is always covered on the channel region of the active layer, so that the channel region of the active layer is protected from being corroded and damaged by yellow light and liquid medicine in an etching process, the risk of interface defects of the channel region and the etching barrier layer is reduced, and the performance of the etching barrier type array substrate is improved.
In an embodiment, referring to fig. 2(h) to fig. 2(j), the step S106 of sequentially preparing the source/drain electrode layer, the passivation layer, and the pixel electrode layer on the etching stop layer includes:
referring to fig. 2(h), a source/drain layer 207 is sequentially formed on the etch stop layer 205.
And sputtering a layer of metal conductive substance film on the etching barrier layer by adopting a magnetron sputtering mode under the action of a strong magnetic field. The metal conductive film can be a metal molybdenum film, a metal molybdenum/copper laminated structure, a titanium/aluminum/titanium laminated structure, or a molybdenum/aluminum/molybdenum laminated structure. The source electrode and the drain electrode are respectively connected with the doped regions positioned at two sides of the active region.
And patterning the metal conductive object film by adopting a one-time photoetching process to form a pattern of a source electrode and a drain electrode. The photoetching process can adopt wet etching, and the used etching solution is hydrogen peroxide system etching solution. And the source electrode and the drain electrode which are formed in a patterning mode are respectively connected with the region of the active layer which is not covered by the etching barrier layer.
Referring to fig. 2(i), a passivation layer 208 is formed on the source/drain layer 207.
An insulating film is deposited on the source/drain layer 207 by ion chemical vapor deposition, and the insulating material may be a single-layer silicon nitride film, a single-layer silicon oxide film, or a laminated silicon oxide/silicon nitride film. The passivation layer covers the source drain electrode layer, the etching barrier layer and the grid electrode insulating layer and is mainly used for separating a source electrode, a drain electrode and the like in the source drain electrode layer, avoiding short circuit among the source electrode, the drain electrode and the like and insulating the source drain electrode layer from a metal layer on the source drain electrode layer.
And etching a preset area of the passivation layer 208 by adopting a one-time photoetching process to expose the source drain layer in the display area and the gate layer in the fan-out area. The photolithography process can be performed by a dry etching process using a plasma formed from an oxidizing gas such as fluorine.
Referring to fig. 2(j), a pixel electrode layer 209 is formed on the passivation layer 208.
And sputtering a layer of indium tin oxide film on the passivation layer 208 in a magnetron sputtering mode under the action of a strong magnetic field. The temperature of the magnetron sputtering substrate is controlled to be lower than 100 ℃, and the formed indium tin oxide film is in an amorphous state, has high etching rate and does not have residue.
And patterning the indium tin oxide film by adopting a one-time photoetching process to form a pattern of a pixel electrode.
According to the above embodiments:
the embodiment of the invention provides a preparation method of an etching barrier type array substrate, which comprises the following steps: preparing a grid electrode layer and a grid electrode insulating layer on a substrate in sequence; depositing a metal oxide semiconductor film and an etching stopper film in this order on the gate insulating layer; coating a layer of light resistance on the etching barrier film; exposing and developing the photoresist by using a half-tone photomask to form a photoresist pattern; the photoresist pattern comprises a first photoresist positioned in the display area and a second photoresist positioned in the fan-out area, the first photoresist comprises a middle part and a side part positioned on the side edge of the middle part and connected with the middle part, and the thickness of the side part is less than that of the middle part; etching and removing the etching barrier film which is not protected by the first light resistance and the second light resistance by adopting a hydrofluoric acid medicament wet etching process; etching and removing the metal oxide semiconductor film which is not protected by the first light resistance and the second light resistance by adopting an oxalic acid series medicament wet etching process; etching and removing the side part by adopting a dry etching process, and etching and thinning the middle part and the second light resistance; etching and removing the etching barrier film which is not protected by the middle part by adopting an oxalic acid medicament wet etching process; stripping off the residual photoresist to obtain a patterned active layer and an etching barrier layer; and sequentially preparing a source drain electrode layer, a passivation layer and a pixel electrode layer on the etching barrier layer. The method saves a photomask manufacturing process, saves the manufacturing cost, protects the channel region of the active layer from being corroded and damaged by yellow light and liquid medicine in the etching manufacturing process, reduces the risk of interface defects of the channel region and the etching barrier layer, and improves the performance of the etching barrier type array substrate.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A preparation method of an etching barrier type array substrate is characterized by comprising the following steps:
preparing a grid electrode layer and a grid electrode insulating layer on a substrate in sequence;
sequentially depositing a metal oxide semiconductor film and an etching barrier film on the gate insulating layer;
coating a layer of photoresist on the etching barrier film;
exposing and developing the photoresist by using a half-tone photomask to form a photoresist pattern; the photoresist pattern comprises a first photoresist positioned in a display area and a second photoresist positioned in a fan-out area, the first photoresist comprises a middle part and a side part positioned on the side edge of the middle part and connected with the middle part, and the thickness of the side part is smaller than that of the middle part;
etching and removing the etching barrier film which is not protected by the first light resistor and the second light resistor by adopting a hydrofluoric acid medicament wet etching process;
etching and removing the metal oxide semiconductor film which is not protected by the first light resistance and the second light resistance by adopting an oxalic acid series medicament wet etching process;
etching and removing the side parts by adopting a plasma dry etching process, and etching and thinning the middle part and the second light resistance;
etching and removing the etching barrier film which is not protected by the middle part by adopting an oxalic acid medicament wet etching process;
stripping off the residual photoresist to obtain a patterned active layer and an etching barrier layer;
and sequentially preparing a source drain electrode layer, a passivation layer and a pixel electrode layer on the etching barrier layer.
2. The method of claim 1, wherein the middle portion has a thickness of 1.4 to 2.5um, and the side portions have a thickness of 0.5 to 0.8 um.
3. The manufacturing method according to claim 1, wherein the step of sequentially depositing a metal oxide semiconductor film and an etching stopper film over the gate insulating layer comprises:
depositing a layer of the metal oxide semiconductor film on the gate insulating layer by using a physical vapor sputtering method;
and depositing an etching barrier film on the metal oxide semiconductor film by using a plasma chemical vapor method.
4. The production method according to claim 3, wherein a material of the metal oxide semiconductor film is any one of indium gallium zinc oxide, indium zinc oxide, and indium gallium zinc tin oxide.
5. The production method according to claim 3, wherein the etching stopper film is any one of a silicon oxide film, a laminated structure of a silicon oxide film and a silicon nitride film.
6. The method according to claim 1, wherein the photoresist coated on the etching barrier film is any one of a positive photoresist and a negative photoresist.
7. The method according to claim 6, wherein the step of forming the resist pattern by exposing and developing the resist using a halftone mask comprises:
exposing the positive photoresist by using a first halftone photomask as a mask;
and developing the exposed positive photoresist by using an alkaline developing solution, removing the exposed photoresist and keeping the unexposed photoresist.
8. The method according to claim 6, wherein the step of forming the resist pattern by exposing and developing the resist using a halftone mask comprises:
exposing the negative photoresist by using a second halftone photomask as a mask;
and developing the exposed negative photoresist by using an alkaline developing solution, removing the unexposed photoresist and keeping the exposed photoresist.
9. The method of claim 1, wherein the step of sequentially forming a gate electrode layer and a gate insulating layer on the substrate comprises:
depositing a layer of metal conductive film on the substrate by adopting a physical vapor sputtering method;
patterning the metal conductive film by adopting a one-time photoetching process to form a gate layer;
and depositing an insulating film layer on the gate electrode layer by adopting a plasma chemical vapor method to serve as a gate insulating layer.
10. The method according to claim 1, wherein the step of sequentially forming a source/drain electrode layer, a passivation layer, and a pixel electrode layer on the etch stop layer comprises:
depositing a layer of metal conductive film on the etching barrier layer by adopting a physical vapor sputtering method; patterning the metal conductive film by adopting a primary photoetching process to form a source drain electrode layer;
depositing an insulating film layer on the source drain layer by adopting a plasma chemical vapor method; etching a preset area of the insulating film layer by adopting a one-time photoetching process to form a passivation layer;
depositing a layer of metal conductive film on the passivation layer by adopting a physical vapor sputtering method; and patterning the metal conductive film by adopting a one-time photoetching process to form a pixel electrode layer.
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