CN112071867A - Active switch array substrate and manufacturing method of thin film transistor array substrate - Google Patents

Active switch array substrate and manufacturing method of thin film transistor array substrate Download PDF

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Publication number
CN112071867A
CN112071867A CN202010980787.8A CN202010980787A CN112071867A CN 112071867 A CN112071867 A CN 112071867A CN 202010980787 A CN202010980787 A CN 202010980787A CN 112071867 A CN112071867 A CN 112071867A
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layer
metal layer
patterned photoresist
photoresist
electrode
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卓恩宗
陈曦
许哲豪
叶利丹
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HKC Co Ltd
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HKC Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Abstract

After a metal layer is subjected to wet etching for the first time or a metal layer is subjected to wet etching for the second time, dry etching is firstly carried out on a light resistor, the volume of the light resistor is reduced, and then the edge width difference between the metal layer which is shielded by the light resistor and has a cross section area smaller than that of the light resistor on the metal layer due to the influence of critical dimension loss and the light resistor is reduced, so that the tail phenomenon is reduced, and the performance stability of devices on the active switch array substrate is improved.

Description

Active switch array substrate and manufacturing method of thin film transistor array substrate
Technical Field
The present disclosure relates to display technologies, and particularly to a method for manufacturing an active switch array substrate and a thin film transistor array substrate.
Background
Each pixel cell on a display device such as a liquid crystal display is driven by an active switching element such as a Thin Film Transistor (TFT) integrated therebehind. The TFT array substrate generally includes a substrate, a thin film transistor arranged on the substrate, a passivation layer, and a pixel electrode. With the development of display technology, the TFT array substrate process has gradually progressed from the initial 7Mask (7Mask) process to the current mainstream 4Mask (4Mask) process, which greatly reduces the production cost of the display device. In the 4Mask process, the key process is the second photomask process, and the wet etching and the dry etching are performed twice to form the source and the drain of the thin film transistor and the conductive channel between the source and the drain. The TFT array substrate after the two wet etches and the two dry etches generally includes a substrate 100 ', a gate 200' formed on the substrate, a gate insulating layer 300 'covering the gate 200', an active layer 400 'formed on the gate insulating layer 300' and opposite to the gate 300 ', discontinuous doping layers 500' formed on both ends of the active layer 400 ', and a source 610' and a drain 620 'formed on the doping layers 500', referring to fig. 1. However, in the related art, after the metal layer 600 'is wet-etched for the first time (the metal layer 600' is finally etched to form the line structures such as the source 610 'and the drain 620'), the doped layer 400 'and the active layer 500' are dry-etched and then Photoresist (PR) ashing is performed, as shown in fig. 2 to 4. Referring to fig. 2, a Critical Dimension LOSS (CD LOSS) is generated by wet etching the metal layer 600 'for the first time, and then the doped layer 400' and the active layer 500 '(refer to fig. 3) under the metal layer 600' are etched by using the photoresist thereon as a mask, so that the metal layer 600 '(forming the line structures such as the source and the drain after the metal layer) after the wet etching for the first time also has a plurality of doped layers 400' and active layers 500 'outside the edge, i.e., the wider doped layer 400' and the Tail (Tail) formed by the active layer 500 'exist outside the edge of the metal layer 600', and the TFT array substrate having the display device with the wider Tail may generate a leakage current between the source and the drain due to light absorption, thereby causing unstable performance of the display device based on the TFT array substrate.
Disclosure of Invention
The present application provides a method for manufacturing an active switch array substrate to solve the technical problem of unstable performance of the display device.
In order to achieve the purpose, the following technical scheme is adopted in the application:
a method for manufacturing an active switch array substrate comprises the following steps:
providing a substrate, and forming a grid electrode on the substrate through a first photomask;
depositing a gate insulating layer to cover the gate electrode and the substrate, and sequentially forming an active layer and a metal layer above the gate insulating layer;
coating a photoresist on the metal layer, and patterning the photoresist through a second photomask to obtain a first patterned photoresist;
taking the first patterned photoresist as a mask, and performing first wet etching on the metal layer to remove the exposed metal layer on the outer side of the first patterned photoresist, wherein the duration of the first wet etching on the metal layer is 60-90 seconds;
performing dry etching on the first patterned photoresist for the first time to obtain a second patterned photoresist, exposing a region between a source electrode region and a drain electrode region to be formed on the metal layer, and removing the active layer and the gate insulating layer exposed on the outer side of the metal layer;
taking the second patterned photoresist as a mask, performing second wet etching on the metal layer to remove a region between a source electrode and a drain electrode to be formed, and performing the second wet etching to form the source electrode and the drain electrode and expose the active layer;
performing second dry etching on the active layer by taking the second patterned photoresist as a mask to form a conductive channel;
and removing the second patterned photoresist and finishing the preparation of the second insulating layer and the electrode layer.
In addition, another embodiment of the present application provides a method for manufacturing an active switch array substrate, which includes:
providing a substrate, and forming a grid electrode on the substrate through a first photomask;
depositing a gate insulating layer to cover the gate electrode and the substrate, and sequentially forming an active layer and a metal layer above the gate insulating layer;
coating a photoresist on the metal layer, and patterning the photoresist through a second photomask to obtain a first patterned photoresist;
taking the first patterned photoresist as a mask, and performing first wet etching on the metal layer to remove the exposed metal layer on the outer side of the first patterned photoresist, wherein the duration of the first wet etching on the metal layer is 60-90 seconds;
performing first dry etching by taking the first patterned photoresist as a mask to expose a region between a source electrode region and a drain electrode region to be formed on the metal layer; simultaneously removing the active layer and the gate insulating layer exposed outside the metal layer;
taking the second patterned photoresist as a mask, performing second wet etching on the metal layer to remove a region between a source electrode and a drain electrode to be formed, and performing the second wet etching to form the source electrode and the drain electrode and expose the active layer; wherein the duration time of the second wet etching of the metal layer is 60-85 seconds;
dry etching the second patterned photoresist to reduce the volume of the second patterned photoresist;
performing second dry etching on the active layer by taking the second patterned photoresist with the reduced volume as a mask to form a conductive channel;
and removing the second patterned photoresist and finishing the preparation of the second insulating layer and the electrode layer.
The present application also provides a method for manufacturing a thin film transistor array substrate, which includes:
providing a substrate, and forming a grid electrode on the substrate through a first photomask process;
depositing a gate insulating layer to cover the gate and the substrate, and sequentially forming an active layer, a doping layer and a metal layer above the gate insulating layer;
coating a photoresist on the metal layer, and patterning the photoresist through a second photomask to obtain a first patterned photoresist;
taking the first patterned photoresist as a mask, and performing first wet etching on the metal layer to remove the exposed metal layer on the outer side of the first patterned photoresist, wherein the duration of the first wet etching on the metal layer is 60-90 seconds;
dry etching the first patterned photoresist for the first time to obtain a second patterned photoresist; simultaneously exposing the region between the source electrode and the drain electrode to be formed on the metal layer; removing the active layer, the doping layer and the gate insulating layer exposed outside the metal layer by first dry etching;
performing second wet etching on the metal layer by taking the second patterned photoresist as a mask to remove a region between a source electrode and a drain electrode to be formed, and forming the source electrode and the drain electrode and exposing the active layer by the second wet etching; the duration time of the second wet etching of the metal layer is 60-85 seconds;
performing second dry etching on the active layer by taking the second patterned photoresist as a mask to form a conductive channel;
removing the second patterned photoresist and completing the preparation of the second insulating layer and the electrode layer
Therefore, according to the manufacturing method of the active switch array substrate, after the metal layer is subjected to wet etching for the first time or the metal layer is subjected to wet etching for the second time, dry etching is firstly performed on the photoresist, the volume of the photoresist is reduced, and then the edge width difference between the metal layer which is shielded by the photoresist and has the cross section area smaller than that of the photoresist on the metal layer due to the influence of CD LOSS and the photoresist is reduced, so that the Tail phenomenon is reduced, and the performance stability of a device based on the active switch array substrate is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of a main structure of a TFT substrate after two wet etches and two dry etches of a related art;
FIG. 2 is a schematic structural diagram of a metal layer after a first wet etching process in the related art;
FIG. 3 is a schematic structural diagram of a doped layer and an active layer under a metal layer etched according to the related art;
FIG. 4 is a schematic diagram illustrating a related art structure after Photoresist (PR) ashing;
FIGS. 5-14 are schematic structural diagrams illustrating a TFT substrate of the present application during a manufacturing process thereof;
fig. 15-19 are schematic structural views illustrating a TFT substrate manufacturing process according to another embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The technical solutions provided by the preferred embodiments of the present application are described in detail below with reference to the accompanying drawings.
The embodiment provides a method for manufacturing an active switch array substrate, such as a TFT array substrate, comprising the following steps:
step S1 is to provide a substrate 100, and form a patterned gate 200 and a gate line (not shown) electrically connected to the gate 200 on the substrate 100 through a first mask, as shown in fig. 5.
Specifically, the substrate 100 is generally a transparent substrate, and may be a glass substrate or a plastic substrate. First, one or more gate metal materials of aluminum (Al), molybdenum (Mo), copper (Cu), chromium (Cr), tungsten (W), aluminum (Al), or the like are deposited on the substrate 100 by magnetron sputtering or the like. The gate metal material is then patterned by coating a photoresist material thereon and by a photolithography process. The gate metal material is wet etched using the patterned photoresist material as a mask to form a gate electrode 200 and a gate line (or scan line) electrically connected to the gate electrode 200. The photoresist is then removed.
Step S2, depositing a gate insulating layer 300 covering the gate electrode 200, the gate line and the substrate 100, and sequentially forming an active layer 400, a doping layer 500 and a metal layer 600 above the gate insulating layer 300, as shown in fig. 6.
Specifically, the gate insulating layer 300 is deposited on the substrate 100 on which the gate electrode 200 is formed to cover the gate electrode 200, the gate line, and the substrate 100. The gate insulating layer 300 may be silicon oxide (SiO)x)Silicon nitride (SiN)x) Or silicon oxynitride (SiO)xNy) And the like, or combinations of several of the same. An active layer 400, a doping layer 500, and a metal layer 600 are sequentially formed over the gate insulating layer 300. The active layer 400 and the doped layer 500 are made of the same semiconductor material, and are typically selected from amorphous silicon, polysilicon, etc., although other semiconductor materials may be selected. The active layer 400 and the doped layer 500 may be formed by two depositions, or after a semiconductor layer (e.g., amorphous silicon) is deposited, impurities (e.g., phosphorus (P) ions or arsenic (As) ions) are doped on the semiconductor layer by a doping process to form the doped layer 500, and the undoped portion is the active layer 400. The active layer 400 is used to form a conductive channel of the thin film transistor. Since the doping layer 500 has a large doping concentration, it is actually an ohmic contact layer, and ohmic contact between the following metal layer 600 and the active layer 400 can be better achieved, although other embodiments of the present application may select whether to form the doping layer 500 according to actual situations. The metal layer 600 may be made of one or more selected from molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
In step S3, a photoresist (PR, not shown) is coated on the metal layer 600, and the photoresist is patterned through a second mask to obtain a first patterned photoresist PR 1. Through the second photo-mask lithography process, the Photoresist (PR) is removed to form the corresponding portions of the outer sides of the source and drain regions to be formed, and the portions of the regions between the source and drain regions to be formed are thinned, so as to form the first patterned photoresist PR1 as shown in fig. 7.
Specifically, a Photoresist (PR) is coated on the metal layer 600, and the photoresist is patterned through a Gray Tone Mask (GTM) or a Half Tone Mask (HTM). Completely removing the light resistance on the outer side of the source electrode and drain electrode area to be formed; and thinning the photoresist between the source electrode region and the drain electrode region to be formed. A Gray Tone Mask (GTM) or a Half Tone Mask (HTM) includes a completely transparent region, a semi-transparent region, and an opaque region. The portions of the photoresist outside the fully transparent regions, e.g., corresponding to the source and drain regions to be formed, may be removed. The semi-transparent region corresponds to, for example, a photoresist between the source and drain regions to be formed, and the photoresist may be thinned. The opaque region corresponds to the remaining photoresist, for example, and the portion of the photoresist is completely remained. Different portions of the photo-resist are exposed to different degrees for thinning, so that the source electrode, the drain electrode and the conductive channel between the source electrode and the drain electrode can be formed step by step later, and the detailed process is described as follows.
Step S4, using the first patterned photoresist PR1 as a mask, performing a first wet etching on the metal layer 600, and removing the metal layer 600 outside the source and drain regions to be formed, as shown in fig. 8.
Specifically, the metal layer 600 is wet-etched using the first patterned photoresist PR1 as a mask, and the metal layer outside the source and drain regions to be formed is removed. At this time, a Critical Dimension LOSS (CD LOSS) is generated at the edge of the metal layer 600 during the first wet etching process, i.e., the cross-sectional area of the metal layer 600 is smaller than that of the patterned photoresist. In the first wet etching process, a Taper angle (Taper) is generated at the same time when the CD LOSS is generated at the edge of the metal layer 600, that is, the edge of the metal layer 600 is inclined with respect to the layer below the metal layer 600, and the cross-sectional areas of the metal layer 600 are different at different heights in the longitudinal direction, in this embodiment, the duration of the first wet etching is controlled to be 60s to 90s to obtain a smaller CD LOSS, thereby reducing the LOSS of the cross-sectional area of the metal layer 600, and obtaining a better Taper angle, so that the deposition coverage of the subsequent process is better.
Step S5, performing a first dry etching on the first patterned photoresist PR1 to obtain a second patterned photoresist PR2, exposing the metal layer 600 between the source and the drain to be formed, and removing the active layer 400, the doped layer 500, and the gate insulating layer 300 exposed outside the metal layer, as shown in fig. 9 and 10.
Specifically, the first patterned photoresist PR1 is dry etched for the first time to expose the metal layer 600 between the source and drain regions to be formed, so as to pattern the metal layer 600 in the subsequent process. On the other hand, in the first dry etching of the patterned photoresist, the entire volume of the photoresist is reduced to form a second patterned photoresist PR 2. Therefore, after this step, the difference between the cross-sectional area of the metal layer 600 and the cross-sectional area of the photoresist after the first dry etching is reduced relative to the difference between the cross-sectional area of the metal layer 600 and the cross-sectional area of the photoresist before the first dry etching (i.e., the patterned photoresist).
Further, in the first dry etching process, the doped layer 500 and the active layer 400 are etched using the second patterned photoresist PR2 as a mask, and the exposed doped layer 500 and the exposed active layer 400 outside the source and the drain to be formed are removed, as shown in fig. 10. At this time, the volume of the second patterned photoresist PR2 is reduced to form a second patterned photoresist PR 2'.
Specifically, since the difference between the cross-sectional area of the metal layer 600 and the cross-sectional area of the photoresist after the first dry etching is reduced relative to the difference between the cross-sectional area of the metal layer 600 and the cross-sectional area of the photoresist before the first dry etching (i.e., the first patterned photoresist PR1), after the doping layer 500 and the active layer 400 are dry etched using the photoresist after the first dry etching as a mask (i.e., the second patterned photoresist PR2), the doping layer 500 and the active layer 400(Tail1) formed outside the edge of the metal layer 600 are reduced (refer to fig. 3 in comparison with the related art), so as to effectively improve the performance stability of the device, and even when the process conditions are properly controlled, the width of the Tail1 is 0, so that the. Of course, when the doped layer 500 is not formed in other embodiments of the present application, in this step, the active layer 400 is dry-etched only by using the photoresist after the first dry etching as a mask, and the active layer 400 outside the source and drain regions to be formed is removed.
The TFT array substrate is formed by performing the following steps based on the above steps, that is, the active switch array substrate is formed by performing the following process based on the structure obtained after step S5 (or the structure formed through steps S1 to S5).
Specifically, step S6 includes, for example, the steps of:
s61, using the second patterned photoresist PR 2' as a mask, performing a second wet etching on the metal layer 600 to remove a region between the source and the drain to be formed, and forming the source 610 and the drain 620 and a data line (not shown) electrically connected to the source 610 by the second wet etching, and exposing the doped layer 500, as shown in fig. 11.
At this time, similarly to step S4, since the edge of the source 610 and the drain 620 also generates Critical Dimension LOSS (CD LOSS) in the second wet etching process, i.e. the cross-sectional area of the source 610 and the drain 620 is further reduced compared to the cross-sectional area of the photoresist after the first dry etching. The source electrode 610 and the drain electrode 620 are formed simultaneously with a metal structure such as a data line electrically connected to the source electrode 610, and the formation process is similar to the source electrode 610 and the drain electrode 620. The TFT array substrate comprises a plurality of gate lines (formed simultaneously with the gate electrodes), a plurality of data lines and a plurality of gate lines, wherein the data lines are arranged approximately in parallel, the gate lines are arranged approximately in parallel, and the data lines and the gate lines are arranged in a crossed manner to define a pixel area of a display device (such as a liquid crystal display device) using the TFT array substrate. In the display device, the drain 620 of the driving TFT is electrically connected to a pixel electrode formed later, so that the pixel region is driven. In this embodiment, the duration of the wet etching is controlled to be 60s-85s to obtain a smaller CD LOSS, so as to reduce the LOSS of the cross-sectional areas of the source 610 and the drain 620, and avoid the wire breakage caused by the too small line width of the source 610 and the drain 620 and other metal structures (such as data lines) formed on the same layer as the source 610 and the drain 620, thereby affecting the electrical connection between the metal structures of the TFT array substrate. Meanwhile, a better Taper angle is obtained, so that the deposition coverage of the subsequent process is better, and the performance of the device is more stable.
S62, performing a second dry etching on the doped layer 500 by using the second patterned photoresist PR 2' as a mask. The doped layer 500 is dry etched to expose the active layer 400 between the source 610 and drain 620 regions, forming a conductive channel, i.e., a conductive channel in the active layer 500.
The present embodiment S62 may specifically include:
s621, using the second patterned photoresist PR2 'as a mask, performing a second dry etching, so that the volume of the second patterned photoresist PR 2' after the second dry etching is smaller than that of the second patterned photoresist PR2, as shown in fig. 12.
Specifically, the volume of the second patterned photoresist PR 2' after the second dry etching is reduced, so that the difference between the cross-sectional areas of the source electrode 610 and the drain electrode 620 and the cross-sectional area of the photoresist after the second dry etching is reduced relative to the difference between the cross-sectional areas of the source electrode 610 and the drain electrode 620 and the cross-sectional area of the second patterned photoresist PR 2.
S622, using the second patterned photoresist PR 2' as a mask, the doped layer 500 is dry etched for the second time to expose the active layer 400 between the source 610 and drain 620 regions, thereby forming a conductive channel, as shown in fig. 13.
Specifically, the active layer 400 between the source 610 and drain 620 regions is a conductive channel. Since the difference between the cross-sectional area of the photoresist and the cross-sectional areas of the source electrode 610 and the drain electrode 620 is reduced after the second dry etching, the doped layer 500(Tail2) formed outside the edges of the source electrode 610 and the drain electrode 620 is reduced after the second patterned photoresist PR 2' is used as a mask to dry etch the doped layer 500, and the performance stability of the device is further improved. The width of Tail2 on the non-conductive channel side is greater than the width of Tail2 on the conductive channel side because it is affected by the two-step wet etching CD LOSS of S4 and S71. When the process conditions are properly controlled, the width of the Tail2 on the side of the conductive channel is 0, so that the performance stability of the device is more effectively improved. In addition, in other embodiments of the present application, after the doped layer 500 is dry-etched, the active layer 400 with a partial thickness may be dry-etched to form an active layer with a smaller thickness and more controllable by the gate voltage.
Of course, this embodiment is an alternative embodiment, and the source 610 and the drain 620 are formed in the present embodiment in a lateral cross-sectional view with reference to fig. 14. In other embodiments, the doped layer 500 may be directly dry-etched to expose the active layer 400 between the source 610 and drain 620 regions to form a conductive channel, without performing a second dry etching on the photoresist after the first dry etching, as in the related art.
Another embodiment of the present application is consistent with the technical idea of the above embodiments, except that after the first wet etching in step S4, the same dry etching of the active layer 400 and the doped layer 500 is performed first and then the dry etching ashing of the patterned photoresist is performed, but after the second wet etching, a dry etching photoresist process is added with respect to the related art.
The specific process can comprise the following steps:
s1, providing the substrate 100, and forming the patterned gate 200 and the gate line electrically connected to the gate 200 on the substrate 100 through the first mask, as shown in fig. 5.
S2, depositing a gate insulating layer 300 covering the gate electrode 200, the gate line and the substrate 100, and sequentially forming an active layer 400, a doping layer 500 and a metal layer 600 above the gate insulating layer 300, as shown in fig. 6.
S3, coating photoresist on the metal layer 600, patterning the photoresist through a second photomask to obtain a first patterned photoresist PR1, and completely removing the photoresist on the outer side of the source electrode and drain electrode region to be formed; the photoresist between the source and drain regions to be formed is thinned, as shown in fig. 7.
S4, using the first patterned photoresist as a mask, performing first wet etching on the metal layer 600, and removing the metal layer 600 on the outer side of the source electrode and drain electrode region to be formed, wherein the duration of the first wet etching on the metal layer is 60-90 seconds; as shown in fig. 8.
S5, dry etching the doped layer 400 and the active layer 500 for the first time by using the first patterned photoresist PR1 as a mask, and removing the doped layer 400 and the active layer 500 outside the source and drain regions to be formed, as shown in fig. 15.
S6, a first dry etching is performed with the first patterned photoresist PR1 as a mask to expose the metal layer 600 between the source and drain regions to be formed, and a second patterned photoresist PR2 is obtained, as shown in fig. 16.
S7, wet etching the metal layer 600 with the second patterned photoresist PR2 as a mask to form a source 610, a drain 620 and a data line electrically connected to the source 610, as shown in fig. 17.
S8, dry etching the second patterned photoresist PR2 to reduce the volume of the second patterned photoresist PR2 and form a second patterned photoresist PR 2', as shown in fig. 18.
S9, dry etching the doped layer 500 with the second patterned photoresist PR 2' as a mask to expose the active layer 400 between the source 610 and drain 620 regions, thereby forming a conductive channel, as shown in fig. 19.
In the embodiment, a dry etching photoresist process is added after the second wet etching compared with the related technology, so that the volume of the photoresist is reduced. Because the difference between the cross-sectional area of the photoresist and the cross-sectional areas of the source 610 and the drain 620 is reduced after the second dry etching, the doped layer 500(Tail2) formed outside the edges of the source 610 and the drain 620 is reduced after the doped layer 500 is dry etched by using the photoresist after the second dry etching as a mask, and the performance stability of the device can also be improved to a certain extent compared with the related art.
The above embodiments describe in detail the first two Mask processes in the manufacturing method of the active switch array substrate for the display device, for example, the TFT array substrate, and after the above steps, the contact holes, the pixel electrodes, and the like may be formed through the two Mask processes (i.e., 4Mask processes in total) which are the same as those of the related main stream technology, or the pixel electrodes and the like may be formed through the one Mask (Mask) process (i.e., 3Mask processes in total) which is improved according to the related main stream technology and further reduces the cost, so as to form the TFT array substrate.
In summary, according to the manufacturing method of active switch array substrates such as the active TFT array substrate provided in the present application, after the metal layer is subjected to wet etching for the first time or the metal layer is subjected to wet etching for the second time, the photoresist is subjected to dry etching, so as to reduce the volume of the photoresist, and further reduce the edge width difference between the metal layer, which is shielded by the photoresist and has a cross-sectional area smaller than that of the photoresist thereon due to the influence of CD LOSS, and the photoresist, so as to reduce the Tail phenomenon, and improve the performance stability of devices based on the active switch array substrates such as the TFT array substrate.
The above-mentioned embodiments, which further illustrate the objects, technical solutions and advantages of the present application, should be understood that the above-mentioned embodiments are only examples of the present application and should not be construed as limiting the present application, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method for manufacturing an active switch array substrate is characterized by comprising the following steps:
providing a substrate, and forming a grid electrode on the substrate through a first photomask;
depositing a gate insulating layer to cover the gate electrode and the substrate, and sequentially forming an active layer and a metal layer above the gate insulating layer;
coating a photoresist on the metal layer, and patterning the photoresist through a second photomask to obtain a first patterned photoresist;
taking the first patterned photoresist as a mask, and performing first wet etching on the metal layer to remove the exposed metal layer on the outer side of the first patterned photoresist, wherein the duration of the first wet etching on the metal layer is 60-90 seconds;
performing dry etching on the first patterned photoresist for the first time to obtain a second patterned photoresist, exposing a region between a source electrode region and a drain electrode region to be formed on the metal layer, and removing the active layer and the gate insulating layer exposed on the outer side of the metal layer;
taking the second patterned photoresist as a mask, performing second wet etching on the metal layer to remove a region between a source electrode and a drain electrode to be formed, and performing the second wet etching to form the source electrode and the drain electrode and expose the active layer;
performing second dry etching on the active layer by taking the second patterned photoresist as a mask to form a conductive channel;
and removing the second patterned photoresist and finishing the preparation of the second insulating layer and the electrode layer.
2. The method for manufacturing an active switch array substrate of claim 1, wherein the duration of the second wet etching of the metal layer is 60-85 seconds.
3. The method for manufacturing an active switch array substrate according to claim 1 or 2, wherein a doped layer is further formed between the active layer and the metal layer, and the second dry etching process further comprises: and etching the doping layer by taking the second patterned photoresist as a mask to expose the active layer.
4. The method for manufacturing an active switch array substrate according to claim 1 or 3, wherein in the second dry etching process, the active layer is partially etched to form a conductive channel.
5. The method of claim 1 or 3, wherein the second insulating layer is deposited to cover the source electrode, the drain electrode, the active layer and the conductive channel, and the substrate.
6. The method of claim 5, further comprising: and etching a via hole above the second insulating layer corresponding to the source electrode or the drain electrode to expose the source electrode or the drain electrode.
7. The method of claim 6, further comprising: and depositing an electrode layer on the second insulating layer and connecting the electrode layer with the source electrode or the drain electrode through the through hole.
8. The method as claimed in claim 1, wherein the active switch array substrate is a thin film transistor array substrate.
9. A method for manufacturing an active switch array substrate is characterized by comprising the following steps:
providing a substrate, and forming a grid electrode on the substrate through a first photomask;
depositing a gate insulating layer to cover the gate electrode and the substrate, and sequentially forming an active layer and a metal layer above the gate insulating layer;
coating a photoresist on the metal layer, and patterning the photoresist through a second photomask to obtain a first patterned photoresist;
taking the first patterned photoresist as a mask, and performing first wet etching on the metal layer to remove the exposed metal layer on the outer side of the first patterned photoresist, wherein the duration of the first wet etching on the metal layer is 60-90 seconds;
performing first dry etching by taking the first patterned photoresist as a mask to expose a region between a source electrode region and a drain electrode region to be formed on the metal layer; simultaneously removing the active layer and the gate insulating layer exposed outside the metal layer;
taking the second patterned photoresist as a mask, performing second wet etching on the metal layer to remove a region between a source electrode and a drain electrode to be formed, and performing the second wet etching to form the source electrode and the drain electrode and expose the active layer; wherein the duration time of the second wet etching of the metal layer is 60-85 seconds;
dry etching the second patterned photoresist to reduce the volume of the second patterned photoresist;
performing second dry etching on the active layer by taking the second patterned photoresist with the reduced volume as a mask to form a conductive channel;
and removing the second patterned photoresist and finishing the preparation of the second insulating layer and the electrode layer.
10. A method for manufacturing a thin film transistor array substrate includes:
providing a substrate, and forming a grid electrode on the substrate through a first photomask process;
depositing a gate insulating layer to cover the gate and the substrate, and sequentially forming an active layer, a doping layer and a metal layer above the gate insulating layer;
coating a photoresist on the metal layer, and patterning the photoresist through a second photomask to obtain a first patterned photoresist;
taking the first patterned photoresist as a mask, and performing first wet etching on the metal layer to remove the exposed metal layer on the outer side of the first patterned photoresist, wherein the duration of the first wet etching on the metal layer is 60-90 seconds;
dry etching the first patterned photoresist for the first time to obtain a second patterned photoresist; simultaneously exposing the region between the source electrode and the drain electrode to be formed on the metal layer; removing the active layer, the doping layer and the gate insulating layer exposed outside the metal layer by first dry etching;
performing second wet etching on the metal layer by taking the second patterned photoresist as a mask to remove a region between a source electrode and a drain electrode to be formed, and forming the source electrode and the drain electrode and exposing the active layer by the second wet etching; the duration time of the second wet etching of the metal layer is 60-85 seconds;
performing second dry etching on the active layer by taking the second patterned photoresist as a mask to form a conductive channel;
and removing the second patterned photoresist and finishing the preparation of the second insulating layer and the electrode layer.
CN202010980787.8A 2020-09-17 2020-09-17 Active switch array substrate and manufacturing method of thin film transistor array substrate Pending CN112071867A (en)

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