CN109616416A - Active switch and preparation method thereof, display device - Google Patents
Active switch and preparation method thereof, display device Download PDFInfo
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- CN109616416A CN109616416A CN201811542005.1A CN201811542005A CN109616416A CN 109616416 A CN109616416 A CN 109616416A CN 201811542005 A CN201811542005 A CN 201811542005A CN 109616416 A CN109616416 A CN 109616416A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 87
- 238000000034 method Methods 0.000 claims abstract description 67
- 238000005530 etching Methods 0.000 claims abstract description 63
- 230000008569 process Effects 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000001039 wet etching Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 238000005516 engineering process Methods 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 238000001312 dry etching Methods 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 13
- 239000010410 layer Substances 0.000 description 259
- 239000010408 film Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- 230000000873 masking effect Effects 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- 239000011241 protective layer Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000003628 erosive effect Effects 0.000 description 7
- 230000008020 evaporation Effects 0.000 description 7
- 238000001704 evaporation Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000002207 thermal evaporation Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 230000002829 reductive effect Effects 0.000 description 4
- 239000003513 alkali Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 239000002585 base Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- -1 formation process Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Abstract
This application involves a kind of active switch and preparation method thereof, display device, the production method of the active switch includes: to provide a substrate, and form grid on the substrate；Gate insulating layer, active film layer, doping film layer and second metal layer are sequentially formed on the grid；First time wet-etching technology is used to perform etching to form the second sub- metal layer the second metal layer；It wherein, is -75 seconds 55 seconds to the etching period of the second metal layer；First time dry etch process is used to perform etching the active film layer and doping film layer to form active layer and doped layer while be ashed to the photoresist；Second of wet-etching technology is used to perform etching to form source-drain electrode the described second sub- metal layer；Second of dry etch process is used to perform etching to form channel region the active layer and doped layer.The application can effectively reduce the light leakage current of active switch device, improve ghost phenomena.
Description
Technical field
This application involves field of display technology, more particularly to a kind of active switch and preparation method thereof, display device.
Background technique
As the working performance to display panel have particularly significant effect switching device, be in display technology one it is non-
Want important Primary Component.With display technology iteration develop, higher performance, high image quality and large-sized display device at
For development trend, and directly affect the factor of user's viewing experience and shopping experience.For high-performance, it is desirable to display device
With higher performance, require have high performance switching device in display device from one aspect.
And in the processing procedure of general switching device, 5 masking process and 4 masking process can be divided into, 4 masking process are compared
5 masking process reduce a photoetching process, can shorten the processing time of switching device, so that relative inexpensiveness, but 4 cover
Membrane process is existed due to its special 2W2D (2Wet etching 2dry etching, 2 wet etchings, 2 dry etchings), meeting
When semiconductor layer and doped layer perform etching, formed biggish Tail (tail), that is, semiconductor layer and doped layer
The part at edge of the edge beyond source-drain electrode, this part directly can contact or be absorbed into the luminous ray of display panel, Jin Eryu
It can be seen that light reaction generates light leakage current, thus increases the leakage current of switching device, cause display device when reliability is tested
There is IS (image sticking, ghost) phenomenon in time.
Summary of the invention
Based on this, it is necessary to there are larger Tail (tail) and then be led for using switching device made of 4 masking process
The problem of causing light leakage current to increase provides a kind of active switch and preparation method thereof, display device.
A kind of production method of active switch, the production method of the active switch include:
One substrate is provided, and forms the first metal layer on the substrate, and the first metal layer is patterned
Processing forms grid；
Gate insulating layer, active film layer, doping film layer and second metal layer are sequentially formed on the grid；
It is coated with a layer photoresist in the second metal layer, and patterned process is carried out to the photoresist；
First time wet-etching technology is used to perform etching to form the second sub- metal layer the second metal layer；Its
In, the etching period to the second metal layer is -75 seconds 55 seconds；
Use first time dry etch process to the active film layer and doping film layer perform etching with formed active layer and
Doped layer is simultaneously ashed the photoresist；
Second of wet-etching technology is used to perform etching to form source-drain electrode the described second sub- metal layer；
Second of dry etch process is used to perform etching the active layer and doped layer to form channel region, the ditch
Road area is through the doped layer and is partially through to the active layer.
The edge and the same side of the active layer formed after the first time dry etching in one of the embodiments,
The described second sub- metal layer edge distance difference range be 0 micron -1.65 microns.
The edge and the same side of the doped layer formed after the first time dry etching in one of the embodiments,
The described second sub- metal layer edge distance difference range be 0 micron -0.4 micron.
The patterned process for forming the grid is etching technics in one of the embodiments, wherein to described
The etching period of the first metal layer is -120 seconds 100 seconds.
A kind of active switch is manufactured using the production method of the aforementioned active switch, the active switch packet
It includes:
Substrate；
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the grid；
Active layer is formed on the gate insulating layer；
Doped layer is formed on the active layer；And
The source electrode being formed on the doped layer and drain electrode；
Wherein, a channel region is located at the middle part of the doped layer, and the channel region is through the doped layer and partially runs through
To the active layer, the source electrode and drain electrode are positioned at the two sides of the channel region.
In one of the embodiments, the edge of the source electrode or drain electrode of the edge of the active layer and the same side away from
It is 0 micron -1.65 microns from difference range.
The edge of the source electrode or drain electrode of the outer ledge of the doped layer and the same side in one of the embodiments,
Distance difference range be 0 micron -0.4 micron.
The thickness range of the grid is 3000 angstroms -5000 angstroms in one of the embodiments,.
The thickness range of the source-drain electrode is 3000 angstroms -4500 angstroms in one of the embodiments,.
A kind of display device, including the active switch as described in aforementioned.
The production method of above-mentioned active switch, dry etch process is formed by using wet-etching technology twice and twice
Active switch can shorten the processing time of active switch, and relative inexpensiveness.By control first time wet etching when
It waits to the etching period of second metal layer between 55 seconds to 75 seconds, i.e., when being performed etching to the two sides of second metal layer,
So that the time of lateral erosion is between 55 seconds to 75 seconds, it is possible to increase the area of the second sub- metal layer two sides, it is subsequent with the second interest category
When layer is that etch stop layer performs etching active layer and doped layer, the Tail (tail) of generation will accordingly reduce, from
And light leakage current is reduced, increase the stability of switching device, improves display device and IS occur when reliability is tested
(image sticking, ghost) phenomenon.
Detailed description of the invention
Fig. 1 is the production method flow chart of the active switch in an embodiment；
Fig. 2 is the structural schematic diagram of the active switch in an embodiment；
Fig. 3 is the structural schematic diagram of the switching device in example technique；
Fig. 4 is the partial enlargement diagram of switching device in Fig. 3；
Fig. 5 is the structural schematic diagram formed according to step S100 in Fig. 1；
Fig. 6 is the structural schematic diagram formed according to step S200 in Fig. 1；
Fig. 7 is the structural schematic diagram formed according to step S300 and S400 in Fig. 1；
Fig. 8 is the structural schematic diagram formed according to step S500 in Fig. 1；
Fig. 9 is the structural schematic diagram formed according to step S600 in Fig. 1；
Figure 10 is the structural schematic diagram formed according to step S700 in Fig. 1；
Figure 11 is the structural schematic diagram of the active switch in another embodiment.
Specific embodiment
The application in order to facilitate understanding is described more fully the application below with reference to relevant drawings.In attached drawing
Give the optional embodiment of the application.But the application can realize in many different forms, however it is not limited to this
Embodiment described in text.On the contrary, the purpose of providing these embodiments is that making to disclosure of this application understanding
It is more thorough and comprehensive.
It should be noted that it can directly on the other element when element is referred to as " being fixed on " another element
Or there may also be elements placed in the middle.When an element is considered as " connection " another element, it, which can be, is directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " left side ",
" right side " and similar statement for illustrative purposes only, are not meant to be the only embodiment.
Unless otherwise defined, all technical and scientific terms used herein and the technical field for belonging to the application
The normally understood meaning of technical staff is identical.The term used in the description of the present application is intended merely to description tool herein
The purpose of the embodiment of body, it is not intended that in limitation the application.
Referring to Fig. 3, for the structural schematic diagram of the switching device in example technique, while assisting refering to Fig. 4, it is Fig. 3
The partial enlarged view of middle switching device.In the processing procedure of general switching device, 5 masking process and 4 masking process can be divided into,
4 masking process reduce a photoetching process compared to 5 masking process, can shorten the processing time of switching device, so that cost phase
To cheap.Fig. 3 show the structural schematic diagram for the switching device that example technique is formed using 4 masking process.In Fig. 3, S
(Source) indicating that the source electrode of switching device, D (Drain) indicate the drain electrode of switching device, N+ indicates the doped layer of switching device,
AS (a-Si:H) indicates that the semiconductor layer (active layer) of switching device, GI (Gate Insulation) indicate the grid of switching device
Pole insulating layer, G (Gate) indicate that the grid of switching device, Glass indicate the substrate (substrate) of switching device.4 masking process by
It, can be in semiconductor layer in its special 2W2D (2Wet etching 2dry etching, 2 wet etchings, 2 dry etchings)
When performing etching with doped layer, biggish Tail (tail) is formed, can specifically include T and t in Fig. 3, that is,
The part at edge of the edge of semiconductor layer and doped layer beyond S/D.Usual T indicates the outer ledge of semiconductor layer and doped layer
Marginal portion beyond S/D, t indicate that the inside edge of doped layer exceeds the interior survey marginal portion of S/D.As can be seen that this is
It is illustrated with the Tail of side, the other side also has same Tail.Wherein, t can be defined as N+Tail in substrate.
Specifically, referring to Fig. 4, T1 indicates that the outer ledge position of semiconductor layer exceeds the length of source electrode outer ledge position, T2 table
Show that the outer ledge position of doped layer exceeds the length of source electrode outer ledge position, T3 indicates that the inside edge position of doped layer is super
The length of source electrode inside edge position out.Since this three parts directly can contact or be absorbed into the luminous ray of display panel, into
And light leakage current is generated with visible light reaction, it thus will increase the leakage current of switching device.Also, it is found through experiments that, with
The length of Tail is longer, and the effect of IS is more bad.So the application wishes to obtain the shorter switching device of Tail.
Specifically, referring to Fig. 1, being the production method flow diagram of the active switch in an embodiment.This is actively opened
The production method of pass may include step: S100-S700.
Step S100 provides a substrate, and forms the first metal layer on the substrate, and to the first metal layer into
Row patterned process forms grid.
Specifically, it please assist refering to Fig. 5, substrate 10 can be glass substrate or plastic base, wherein glass substrate can be with
For no alkali borosilicate ultra-thin glass, no alkali borosilicate glass physical characteristic with higher, preferable corrosion resistance, compared with
High thermal stability and lower density and higher elasticity modulus.Forming the first metal layer on the substrate 10, (Fig. 5 is not marked
Show) it can be rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.The
One metal layer (Fig. 5 is not indicated) can be the heap stack combination of one or more of molybdenum, titanium, aluminium and copper.Patterned process can
Required pattern is formed by photoetching treatment to be, that is, grid 20, can also be and grid is formed by wet-etching technology.
In this embodiment, grid 20 is formed using wet-etching technology.Wherein, to the first metal layer perform etching when
It waits, grid 20 can be formed by control etch period.It illustratively, can be 100 to the etch period of the first metal layer
Between second to 120 seconds, optionally, the etch period to the first metal layer is 110 seconds；Optionally, to the etching of the first metal layer
Time is 106 seconds；It optionally, is 96 seconds to the etching period of the first metal layer.It is appreciated that " control " be considered as increase or
Person is to reduce, as long as last etch period is between 100 seconds to 120 seconds.By controlling the etching to the first metal layer
Time between 100 seconds to 120 seconds, can make the etch quantity to the first metal layer smaller, and then the face of the grid 20 formed
Product is larger, correspondingly, so that it may more block and impinge upon the light of Tail in active layer (t in Fig. 3) above, so as to reduce
Tail (t in Fig. 3) reacts the leakage current to be formed with light in active layer so that display device reliability test when
IS effect is preferable." reliability " refer in the lab deliberately to some rugged environments of display panel, judges to show with this
The stability of panel.
Step S200 is sequentially depositing gate insulating layer, active film layer, doping film layer and the second metal on the grid
Layer.
Specifically, referring to Fig. 6, gate insulating layer 30, active film layer 40, doping film layer can be sequentially depositing on grid 20
50 and second metal layer 60.Wherein, depositing operation may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and
Plasma reinforced chemical vapour deposition technique.
Step 300, it is coated with a layer photoresist in the second metal layer, and the photoresist is carried out at patterning
Reason.
Specifically, referring to Fig. 7, one layer of photoresist layer (figure does not indicate) is coated with above second metal layer 60, using together
Light shield technique is patterned processing to photoresist layer, obtains the photoresist 70 with predetermined pattern.
Step S400 uses first time wet-etching technology to perform etching the second metal layer to form the second interest
Belong to layer；It wherein, is -75 seconds 55 seconds to the etching period of the second metal layer.
Specifically, please continue to refer to Fig. 7, first time wet-etching technology is used to perform etching with shape second metal layer 60
At the second sub- metal layer 60A.Wherein, when performing etching to second metal layer 60, it can control etch period to be formed
Second sub- metal layer 60A.Illustratively, the etch period of second metal layer can control between 55 seconds to 75 seconds, it is optional
Ground, the etch period to second metal layer 60 are 64 seconds；It optionally, is 56 seconds to the etch period of second metal layer 60.It can be with
Understand, " control ", which is considered as increasing, either to be reduced, as long as last etch period controls within 55 seconds to 75 seconds.
By controlling within 55 seconds to 75 seconds when first time wet etching the etching period of second metal layer, i.e., to second
When the two sides of metal layer perform etching, so that the time of lateral erosion is within 55 seconds to 75 seconds, it is possible to increase the second sub- metal layer
The area of the two sides 60A so that it is subsequent using the second sub- metal layer 60A as etch stop layer to performing etching when, generation
Tail (tail) (T in Fig. 3) will accordingly reduce, to reduce light leakage current, increase the stability of switching device, improve aobvious
There is IS phenomenon when reliability is tested in showing device.
Step S500 uses first time dry etch process to perform etching to be formed the active film layer and doping film layer
Active layer and doped layer are simultaneously ashed the photoresist.
Specifically, can refer to Fig. 8, can using first time dry etch process to active film layer 40 and doping film layer 50 into
Row etching carries out ashing processing to photoresist 70 to form active layer 40A and doped layer 50A, obtains knot as shown in Figure 8
Structure, the ashing of photoresist just refers to be fallen photoresist as the target etch that is etched, and is generally reacted using oxygen with photoresist, raw
At volatile materials.When due to using the second sub- metal layer 60A as etching barrier layer, the two sides of the second sub- metal layer 60A are etched
Area it is smaller so that the Tail of generation is (in Fig. 3 when performing etching to active film layer 40 and doping film layer 50
T length) is smaller, to reduce the area with visible light reaction, and then reduces light leakage current, increases the stabilization of switching device
Property, improve display device and IS phenomenon occurs when reliability is tested.Optionally, what is formed after first time dry etching is active
The distance difference range at the edge of the second sub- metal layer 60A at the edge and the same side of layer 40A is 0 micron -1.65 microns, can be with
Assist understanding the edge of the active layer 40A formed after first time dry etching and second son of the same side by the T1 in Fig. 4
The distance difference at the edge of metal layer 60A, certainly, the range of the T1 in Fig. 4 can not be interpreted as being equal to 0 micron -1.65 microns；
Optionally, the edge of the second sub- metal layer 60A at the edge and the same side of the active layer 40A formed after first time dry etching
Distance difference is 1.64 microns；Optionally, the second of the edge of the active layer 40A formed after first time dry etching and the same side
The distance difference at the edge of sub- metal layer 60A is 1.6 microns.
Optionally, the edge of the doped layer 50A formed after first time dry etching and the second sub- metal layer 60A of the same side
Edge distance difference range be 0 micron -0.4 micron.It can assist understanding first time dry etching by the T2 in Fig. 4
The distance difference at the edge of the second sub- metal layer 60A at the edge and the same side of the doped layer 50A formed afterwards, certainly, in Fig. 4
The range of T2 can not be interpreted as being equal to 0 micron -0.4 micron；Optionally, the doped layer 50A formed after first time dry etching
Edge and the same side the second sub- metal layer 60A edge distance difference be 0.32 micron；Optionally, first time dry method is carved
The distance difference at the edge of the second sub- metal layer 60A at the edge and the same side of the doped layer 50A formed after erosion is 0.34 micron.
This embodiment is described only for the side of active switch, it is possible to understand that, the other side of active switch can be joined
According to the description of above-described embodiment, therefore not to repeat here.By by the thickness control of active layer, doped layer in a certain range, can
The area with visible light reaction is reduced, and then reduces light leakage current, increases the stability of switching device, improves display device and is believing
There is IS phenomenon when relying property test.
Step S600 uses second of wet-etching technology to perform etching to form source and drain the described second sub- metal layer
Pole.
Specifically.Referring to Fig. 9, use again second of wet-etching technology to the second sub- metal layer 60A perform etching with
Form source electrode 610, drain electrode 620.
Step S700 uses second of dry etch process to perform etching to form channel the active layer and doped layer
Area, the channel region is through the doped layer and is partially through to the active layer.
Specifically, it can refer to Figure 10, be etching barrier layer with source electrode 610 and drain electrode 620, using second of dry etching work
Skill performs etching doped layer 50A and active layer 40A, forms a channel region 80, wherein channel region 80 is through doped layer 50A, simultaneously
Part is through to active layer 40A." partially running through " does not all etch away the active layer part in the second groove, because
Active layer is as conductive medium, so cannot all be etched away.It is appreciated that for the specific thickness of " part ", it can be with
It makes a choice and adjusts according to practical condition and properties of product.Second metal layer 60 is partitioned into source electrode 610 by channel region 80
With drain electrode 620, source electrode 610 is located at the two sides of channel region 80 with drain electrode 620.
Above-described embodiment can by using wet-etching technology twice and the active switch of dry etch process formation twice
Shorten the processing time of active switch, and relative inexpensiveness.To the second gold medal when by controlling first time wet etching
Belong to the etching period of layer within 55 seconds to 75 seconds, i.e., when being performed etching to the two sides of second metal layer, so that lateral erosion
Time is within 55 seconds to 75 seconds, it is possible to increase the area of the second sub- metal layer two sides, it is subsequent to be hindered with the second sub- metal layer for etching
When barrier performs etching active layer and doped layer, the Tail (tail) of generation will accordingly reduce, to reduce light leakage
Electric current increases the stability of switching device, improves display device and IS (image occurs when reliability is tested
Sticking, ghost) phenomenon.
Referring to Fig. 2, for the structural schematic diagram of the active switch in an embodiment, which is opened using aforementioned active
The production method embodiment of pass is manufactured.The active switch may include: substrate 10, grid 20, and gate insulating layer 30 is active
Layer 40A, doped layer 50A and source electrode 610, drain electrode 620.Wherein, grid 20 is formed on substrate 10；Gate insulating layer 30 is formed in
On substrate 10, while gate insulating layer 30 covers grid 20；Active layer 40A is formed on gate insulating layer 30；Doped layer 50A shape
At on active layer 40A；Source electrode 610, drain electrode 620 are formed on doped layer 50A.One channel region 80 is located in doped layer 50A
Portion, channel region 80 is through doped layer 50A and is partially through to active layer 40A, and source electrode 610 and drain electrode 620 are located at channel region 80
Two sides.It is appreciated that the active switch in the present embodiment can regard thin film transistor (TFT) as.
Above-mentioned active switch is manufactured by using the production method of aforementioned active switch, and the system of aforementioned active switch
Make method by using wet-etching technology twice and the active switch of dry etch process formation twice, active switch can be shortened
Processing time, and relative inexpensiveness.To the etching period of second metal layer when by controlling first time wet etching
Within 55 seconds to 75 seconds, i.e., when being performed etching to the two sides of second metal layer, so that the time of lateral erosion was at 55 seconds to 75
Second within, it is possible to increase the area of the second sub- metal layer two sides, it is subsequent using the second sub- metal layer be etch stop layer to active layer with
When doped layer performs etching, the Tail (tail) of generation will accordingly reduce, to reduce light leakage current, increase derailing switch
The stability of part improves display device and IS (image sticking, ghost) phenomenon occurs when reliability is tested.
Substrate 10 can be glass substrate or plastic base, wherein glass substrate can be the ultra-thin glass of alkali-free borosilicate
Glass, no alkali borosilicate glass physical characteristic with higher, preferable corrosion resistance, higher thermal stability and lower
Density and higher elasticity modulus.
Grid 20 is formed on substrate 10, wherein the formation process of grid 20 may include rf magnetron sputtering, heat steaming
Hair, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that the formation process of grid 20 can be with
It is selected and is adjusted according to practical situations and properties of product, be not further limited herein.The material of grid 20
It can be the heap stack combination of one or more of molybdenum, titanium, aluminium and copper；Select molybdenum, titanium, aluminium and copper can as 20 material of grid
To guarantee good electric conductivity.It is appreciated that the material of grid 20 can according to practical situations and properties of product into
Row selection and adjustment, are not further limited herein.The thickness range of grid 20 can be 3000 angstroms -5000 angstroms, optionally,
The thickness of grid 20 can be 3000 angstroms -4000 angstroms, and optionally, the thickness of grid 20 can be 4000 angstroms -5000 angstroms.It can manage
Solution, the thickness of grid 20 can be selected and be adjusted according to practical situations and properties of product, not made herein further
Restriction.
Gate insulating layer 30 is formed on substrate 10, and the formation process of gate insulating layer 30 may include that radio frequency magnetron splashes
It penetrates, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that gate insulating layer 30
Formation process can be selected and be adjusted according to practical situations and properties of product, do not limit further herein
It is fixed.The material of gate insulating layer 30 can be one of silica, silicon nitride or combination, i.e. gate insulating layer 30
It can be silica, be also possible to silicon nitride, can also be the mixture of silica and silicon nitride.It is appreciated that gate insulator
The material of layer 30 can be selected and be adjusted according to practical situations and properties of product, not limited further herein
It is fixed.The thickness of gate insulating layer 30 can be 3500 angstroms -4000 angstroms, and optionally, the thickness of gate insulating layer 30 can be 3500
Angstroms -3700 angstroms, optionally, the thickness of gate insulating layer 30 can be 3700 angstroms -4000 angstroms.It is appreciated that gate insulating layer 30
Thickness can be selected and be adjusted according to practical situations and properties of product, be not further limited herein.
Active layer 40A is formed on gate insulating layer 30, and the formation process of active layer 40A may include that radio frequency magnetron splashes
It penetrates, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that the shape of active layer 40A
It can be selected and be adjusted according to practical situations and properties of product at technique, be not further limited herein.Have
The material of active layer 40A can be amorphous silicon, and active layer 40A is usually as conductive medium.The edge and the same side of active layer 40A
Source electrode 610 or drain 620 edge distance difference range be 0 micron -1.65 microns, in other words, the side of active layer 40A
Edge can be 0 micron -1.65 microns with the distance difference range at the edge of the source electrode 610 of the same side；The edge of active layer 40A is also
It can be 0 micron -1.65 microns with the distance difference range at the edge of the drain electrode 620 of the same side.Can by the T1 in Fig. 4 come
Auxiliary understands the distance difference at the edge of the edge of active layer 40A and the source electrode 610 of the same side or drain electrode 620, certainly, in Fig. 4
T1 range can not be interpreted as be equal to 0 micron -1.65 microns；For ease of description, this sentence the edge of active layer 40A with
It is illustrated for the distance difference at the edge of the source electrode 610 of the same side.Optionally, the edge and the same side of active layer 40A
The distance difference at the edge of source electrode 610 is 1.64 microns；Optionally, the side of the source electrode 610 at the edge and the same side of active layer 40A
The distance difference of edge is 1.6 microns.
Doped layer 50A is formed on active layer 40A, the formation process of doped layer 50A may include rf magnetron sputtering,
Thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that the formation of doped layer 50A
Technique can be selected and be adjusted according to practical situations and properties of product, be not further limited herein.Doping
Layer 50A can be carries out n-type doping in amorphous silicon layer, is also possible to carry out p-type doping in amorphous silicon layer, optionally, doping
Layer 50A be n-type doping is carried out in amorphous silicon layer, meanwhile, be N-type heavy doping, wherein doping way may include High temperature diffusion
And ion implanting.High temperature diffusion is to spread or be deposited to silicon wafer by gaseous sources or doped oxide for foreign atom
Surface, these impurity concentrations will from surface to internal monotonic decreasing, in High temperature diffusion, the distribution of impurity mainly by high temperature with
Diffusion time determines.Ion implanting is injected Doped ions in semiconductor in the form of ion beam, and impurity concentration is partly being led
There is peak Distribution in vivo, in ion implanting, Impurity Distribution is mainly determined by mass of ion and Implantation Energy.N-type doping is main
It is the incorporation pentavalent impurity element in semiconductor, such as: phosphorus, arsenic.Ion implanting is relative to the advantages of High temperature diffusion: 1, injecting
Ion be to be selected by mass analyzer come the particle that is selected purity is high, energy is single, to ensure that doping is dense
Degree is not influenced by impurity source purity.In addition, injection process carries out under cleaning, dry vacuum condition, various pollutions are dropped to
Floor level；2, the foreign atom number being injected into chip can be accurately controlled, implantation dosage is from for adjusting threshold voltage
1011/cm2To forming the 10 of insulating buried layer17/cm2, wider range.3, when ion implanting, substrate is generally kept in room temperature or low
Under 400 DEG C of temperature environment.Therefore, as silica, silicon nitride, aluminium and photoresist etc. may serve to alternatively adulterate
Masking film, make device manufacture in autoregistration macking technique it is more flexible.The outer ledge of doped layer 50A and the source of the same side
The distance difference range at pole 610 or the edge of drain electrode 620 is 0 micron -0.4 micron.In other words, the outer side edges of doped layer 50A
Edge can be 0 micron -0.4 micron with the distance difference range at the edge of the source electrode 610 of the same side；The outer side edges of doped layer 50A
Edge can also be 0 micron -0.4 micron with the distance difference range at the edge of the drain electrode 620 of the same side.It can be by Fig. 4
T2 come assist understanding doped layer 50A outer ledge and the same side source electrode 610 or drain 620 edge distance difference, when
So, the range of the T2 in Fig. 4 can not be interpreted as being equal to 0 micron -0.4 micron；For ease of description, this sentences doped layer 50A
Outer ledge and the same side source electrode 610 edge distance difference for be illustrated.Optionally, doped layer 50A's is outer
The distance difference at the edge of the source electrode 610 of side edge and the same side is 0.32 micron；Optionally, the outer ledge of doped layer 50A
Distance difference with the edge of the source electrode 610 of the same side is 0.34 micron.This embodiment is carried out only for the side of active switch
Description, it is possible to understand that, the description of above-described embodiment is referred to for the other side of active switch, therefore not to repeat here.
By the way that the thickness control of active layer, doped layer in a certain range, can be reduced to the area with visible light reaction, and then reduce light
Leakage current increases the stability of switching device, improves display device and IS phenomenon occurs when reliability is tested.
Source electrode 610, drain electrode 620 are formed on doped layer 50A, and source electrode 610,620 formation process of draining may include penetrating
Frequency magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that source electrode
610, the formation process of drain electrode 620 can be selected and be adjusted according to practical situations and properties of product, not made herein
It is further to limit.Source electrode 610,620 material of draining can be the storehouse group of one or more of molybdenum, titanium, aluminium and copper
It closes；Select molybdenum, titanium, aluminium and copper that can guarantee good electric conductivity as source electrode 610,620 materials of drain electrode.The source of being appreciated that
Pole 610, drain 620 material can be selected and be adjusted according to practical situations and properties of product, do not make herein into
The restriction of one step.Source electrode 610,620 thickness of draining can be 3000 angstroms -4500 angstroms, optionally, source electrode 610, drain electrode 620
Thickness can be 3000 angstroms -4000 angstroms, optionally, source electrode 610, drain 620 thickness can be 4000 angstroms -4500 angstroms.It can be with
Understand, source electrode 610, drain 620 material can be identical or not identical with thickness, source electrode 610, drain 620 material and
Thickness can be selected and be adjusted according to practical situations and properties of product, be not further limited herein.
Channel region 80 is located at the middle part of doped layer 50A, and channel region 80 is through doped layer 50A and active layer is run through in part
40A.Source electrode 610 and drain electrode 620 are located in the two sides of channel region 80." running through " can be realized by photoetching or lithographic method,
Photosensitive photoresist is set to exist by exposure and imaging using the mask with a certain layer design configuration specifically, photoetching refers to
Three-dimensional relief pattern is formed on substrate.Etching refers to that under photoresist masking, the film layer for forming micrographics as needed is different, adopts
Selective etch is carried out in film layer with different etching substances and method.In this way, after removing photoresist, three dimensional design figure
It has been transferred in the related film layer of substrate.
Figure 11 is please referred to, is the structural schematic diagram of active switch in another embodiment.The active switch may include substrate
10, grid 20, gate insulating layer 30, active layer 40, doped layer 50, source electrode 610, drain electrode 620 and protective layer 90.Wherein, grid
20 are formed on substrate 10；Gate insulating layer 30 is formed on substrate 10, while gate insulating layer 30 covers grid 20；Active layer
40A is formed on gate insulating layer 30；Doped layer 50A is formed on active layer 40A；Source electrode 610, drain electrode 620 are formed in doping
Layer 50A on, protective layer 90 be formed in source electrode 610, drain electrode 620 on；One channel region 80 is located at the middle part of doped layer 50A, channel region
80 run through doped layer 50A and are partially through to active layer 40A, and source electrode 610 and drain electrode 620 are positioned at the two sides of channel region 80, simultaneously
Protective layer 90 covers channel region 80.
It is appreciated that for substrate 10, grid 20, gate insulating layer 30, active layer 40A, doped layer 50A, source electrode 610,
Material, formation process, composition, the thickness etc. of drain electrode 620, are referred to the description of aforementioned active switch embodiment, herein no longer
Further progress repeats.
Protective layer 90 mainly for the protection of switching device from polluting and damaging, specifically, protective layer 90 be also referred to as PV
(Passivation, passivation) layer, the material of protective layer 90 can be the combination of silicon nitride, silica or the two.It can manage
Solution, is not particularly limited the thickness of protective layer 90, those skilled in the art can be according to practical condition and properties of product
It is selected and is adjusted.
Above-mentioned active switch is manufactured by using the production method of aforementioned active switch, and the system of aforementioned active switch
Make method by using wet-etching technology twice and the active switch of dry etch process formation twice, active switch can be shortened
Processing time, and relative inexpensiveness.To the etching period of second metal layer when by controlling first time wet etching
Within 55 seconds to 75 seconds, i.e., when being performed etching to the two sides of second metal layer, so that the time of lateral erosion was at 55 seconds to 75
Second within, it is possible to increase the area of the second sub- metal layer two sides, it is subsequent using the second sub- metal layer be etch stop layer to active layer with
When doped layer performs etching, the Tail (tail) of generation will accordingly reduce, to reduce light leakage current, increase derailing switch
The stability of part improves display device and IS (image sticking, ghost) phenomenon occurs when reliability is tested；One
In embodiment, by be arranged protective layer, can protective film transistor from damage.
A kind of display device may include the aforementioned active switch embodiment, above-mentioned display device, due to actively opening
Pass is manufactured by using the production method of aforementioned active switch, and the production method of aforementioned active switch is by using twice
Wet-etching technology and twice dry etch process form active switch, when can shorten the processing procedure of active switch (thin film transistor (TFT))
Between, and relative inexpensiveness.To the etching period of second metal layer at 55 seconds when by controlling first time wet etching
To within 75 seconds, i.e., when being performed etching to the two sides of second metal layer so that the time of lateral erosion within 55 seconds to 75 seconds,
Can increase the area of the second sub- metal layer two sides, it is subsequent using the second sub- metal layer as etch stop layer to active layer and doped layer into
When row etching, the Tail (tail) of generation will accordingly reduce, to reduce light leakage current, increase the stabilization of switching device
Property.Optionally, by controlling to the etch period of the first metal layer within 100 seconds to 120 seconds, the grid to be formed can be made
Area it is larger, correspondingly, so that it may more the light impinged upon in active layer above Tail is blocked, so as to reduce active layer
Interior Tail reacts the leakage current to be formed with light, increases the stability of switching device, improves what display device was tested in reliability
When there is IS phenomenon.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
The limitation to claim therefore cannot be interpreted as.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the concept of this application, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of production method of active switch, which is characterized in that the production method of the active switch includes:
One substrate is provided, and forms the first metal layer on the substrate, and patterned process is carried out to the first metal layer,
Form grid；
Gate insulating layer, active film layer, doping film layer and second metal layer are sequentially formed on the grid；
It is coated with a layer photoresist in the second metal layer, and patterned process is carried out to the photoresist；
First time wet-etching technology is used to perform etching to form the second sub- metal layer the second metal layer；Wherein, right
The etching period of the second metal layer is -75 seconds 55 seconds；
First time dry etch process is used to perform etching to form active layer and doping the active film layer and doping film layer
Layer is simultaneously ashed the photoresist；
Second of wet-etching technology is used to perform etching to form source-drain electrode the described second sub- metal layer；
Second of dry etch process is used to perform etching the active layer and doped layer to form channel region, the channel region
Through the doped layer and partially it is through to the active layer.
2. the production method of active switch according to claim 1, which is characterized in that shape after the first time dry etching
At the active layer edge and the same side the described second sub- metal layer edge distance difference range be 0 micron-
1.65 micron.
3. the production method of active switch according to claim 1, which is characterized in that shape after the first time dry etching
At the doped layer edge and the same side the described second sub- metal layer edge distance difference range be 0 micron -0.4
Micron.
4. the production method of active switch according to claim 1, which is characterized in that the pattern for forming the grid
Changing processing is etching technics, wherein the etching period to the first metal layer is -120 seconds 100 seconds.
5. a kind of active switch, which is characterized in that use the production method of active switch according to any one of claims 1-4
It is manufactured, the active switch includes:
Substrate；
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the grid；
Active layer is formed on the gate insulating layer；
Doped layer is formed on the active layer；And
The source electrode being formed on the doped layer and drain electrode；
Wherein, a channel region is located at the middle part of the doped layer, and the channel region is through the doped layer and is partially through to institute
Active layer is stated, the source electrode and drain electrode are located at the two sides of the channel region.
6. active switch according to claim 5, which is characterized in that the edge of the active layer and the source of the same side
The distance difference range at pole or the edge of drain electrode is 0 micron -1.65 microns.
7. active switch according to claim 5, which is characterized in that the outer ledge of the doped layer and the institute of the same side
The distance difference range for stating the edge of source electrode or drain electrode is 0 micron -0.4 micron.
8. active switch according to claim 5, which is characterized in that the thickness range of the grid is 3000 angstrom -5000
Angstrom.
9. active switch according to claim 5, which is characterized in that the thickness range of the source-drain electrode be 3000 angstroms-
4500 angstroms.
10. a kind of display device, which is characterized in that including such as described in any item active switches of claim 5-9.
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Cited By (1)
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