CN109616417A - Active switch and preparation method thereof, display device - Google Patents
Active switch and preparation method thereof, display device Download PDFInfo
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- CN109616417A CN109616417A CN201811543287.7A CN201811543287A CN109616417A CN 109616417 A CN109616417 A CN 109616417A CN 201811543287 A CN201811543287 A CN 201811543287A CN 109616417 A CN109616417 A CN 109616417A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000008569 process Effects 0.000 claims abstract description 29
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000005516 engineering process Methods 0.000 claims abstract description 19
- 238000001039 wet etching Methods 0.000 claims abstract description 15
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 25
- 239000007789 gas Substances 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 178
- 239000010408 film Substances 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 239000000463 material Substances 0.000 description 16
- 239000010409 thin film Substances 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 description 10
- 239000011241 protective layer Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000008020 evaporation Effects 0.000 description 7
- 238000001704 evaporation Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 238000002207 thermal evaporation Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- 230000036961 partial effect Effects 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 230000008439 repair process Effects 0.000 description 4
- 239000003513 alkali Substances 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- -1 aluminium tin-oxide Chemical compound 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000002585 base Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RQIPKMUHKBASFK-UHFFFAOYSA-N [O-2].[Zn+2].[Ge+2].[In+3] Chemical compound [O-2].[Zn+2].[Ge+2].[In+3] RQIPKMUHKBASFK-UHFFFAOYSA-N 0.000 description 1
- HXFVOUUOTHJFPX-UHFFFAOYSA-N alumane;zinc Chemical compound [AlH3].[Zn] HXFVOUUOTHJFPX-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
- H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Thin Film Transistor (AREA)
Abstract
This application involves a kind of active switches and preparation method thereof, display device, this method comprises: providing a substrate, and deposit the first metal layer on the substrate, and form grid after patterned processing；Gate insulating layer, active layer, doped layer and source-drain electrode are sequentially formed on the grid；Wherein, the active layer, doped layer, source-drain electrode and a channel region are formed using wet-etching technology twice and twice dry etch process, the channel region is through the doped layer and is partially through to the active layer；The channel region is placed in preset atmosphere and is heated；Wherein, the first preset time first is heated to the channel region under predetermined power, finally adjusts the predetermined power and heats the second preset time in the atmosphere of ammonia.The application can effectively reduce the light leakage current of active switch device, improve IS phenomenon.
Description
Technical field
This application involves field of display technology, more particularly to a kind of active switch and preparation method thereof, display device.
Background technique
As the working performance to display panel have particularly significant effect switching device, be in display technology one it is non-
Want important Primary Component.With display technology iteration develop, higher performance, high image quality and large-sized display device at
For development trend, and directly affect the factor of user's viewing experience and shopping experience.For high-performance, it is desirable to display device
With higher performance, require have high performance switching device in display device from one aspect.
And in the processing procedure of common amorphous silicon switching device, it is all that (Back Channel Etching carries on the back ditch using BCE
Road etching) type structure, the relative inexpensiveness of this structure and relative to ES (Etching stop, etch stop layer) type knot
It is simpler for the technique of structure.But when carrying out back channel etching (N+cutting) using BCE type structure, active layer (is partly led
Body layer) it is usually destroyed and generates more dangling bonds (Dangling Bond) and weak bond (Weak Bond), weak bond is easy in light
According to lower decomposition, dangling bonds may cause the unstability of switching device, cause the leakage current of switching device to increase, and then cause to show
There is IS (image sticking, ghost) phenomenon when reliability is tested in showing device.
Summary of the invention
Based on this, it is necessary to be directed to and use switching device leakage current made of BCE type structure larger, and then display is caused to fill
It sets and the problem of IS phenomenon occurs when reliability test, a kind of active switch and preparation method thereof, display device are provided.
A kind of production method of active switch, the production method of the active switch include:
One substrate is provided, and deposits the first metal layer on the substrate, and the first metal layer is patterned
Processing forms grid；
Gate insulating layer, active layer, doped layer and source-drain electrode are sequentially formed on the grid；
Wherein, the active layer, doped layer, source and drain are formed using wet-etching technology twice and twice dry etch process
Pole and a channel region, the channel region is through the doped layer and is partially through to the active layer；
The channel region is placed in preset atmosphere and is heated；Wherein, first to institute under predetermined power
State channel region heat the first preset time, finally adjust the predetermined power and in the atmosphere of ammonia heating second it is default when
Between.
In one of the embodiments, it is described sequentially formed on the grid gate insulating layer, active layer, doped layer and
The step of source-drain electrode, comprising:
Gate insulating layer, active film layer, doping film layer and second metal layer are sequentially depositing on the grid；
It is coated with a layer photoresist in the second metal layer, and patterned process is carried out to the photoresist；
First time wet-etching technology is used to perform etching to form the second sub- metal layer the second metal layer；
Use first time dry etch process to the active film layer and doping film layer perform etching with formed active layer and
Doped layer is simultaneously ashed the photoresist；
Second of wet-etching technology is used to perform etching to form source-drain electrode the described second sub- metal layer；
Second of dry etch process is used to perform etching the active layer and doped layer to form channel region, the ditch
Road area is through the doped layer and is partially through to the active layer.
In one of the embodiments, first preset time be -90 seconds 1 second, second preset time be 1 second -
60 seconds.
In one of the embodiments, after second of dry etching the remaining active layer with a thickness of 300 angstroms-
900 angstroms.
Forming the doped layer in one of the embodiments, is the PH in deposition gases using depositing operation3And SiH4's
Gas flow ratio is 1.25-4.5.
The power bracket after the adjusting predetermined power is 6KW-16KW in one of the embodiments,.
A kind of active switch is manufactured using the production method of the thin film transistor (TFT) as described in aforementioned, and the active is opened
Pass includes:
Substrate；
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the grid；
Active layer is formed on the gate insulating layer；
Doped layer is formed on the active layer；And
The source electrode being formed on the doped layer and drain electrode；
Wherein, a channel region is located at the middle part of the doped layer, and the channel region is through the doped layer and partially runs through
To the active layer, the source electrode and drain electrode are positioned at the two sides of the channel region.
The thickness range of the grid is 3000 angstroms -5000 angstroms in one of the embodiments,.
The thickness range of the gate insulating layer is 3500 angstroms -4000 angstroms in one of the embodiments,.
A kind of display device, including the active switch as described in aforementioned.
The production method of above-mentioned active switch, dry etch process is formed by using wet-etching technology twice and twice
Active switch can shorten the processing time of active switch, and relative inexpensiveness.Further, by by channel region pre-
If heating the first preset time under power, then adjust predetermined power and continue in the atmosphere of ammonia heating second it is default when
Between, channel region damage as caused by etching can be repaired, while the weak bond in amorphous silicon can also be reduced, enhance active switch
Irradiation and irradiation stability reduce light leakage current, and then improve and the phenomenon that IS occur in the reliability test of display device.
Detailed description of the invention
Fig. 1 is the production method flow diagram of the active switch in an embodiment；
Fig. 2 is the structural schematic diagram of the active switch in an embodiment；
Fig. 3 is the partial structure diagram formed in Fig. 1 according to step S100；
Fig. 4 is the partial structure diagram formed in Fig. 1 according to step S200；
Fig. 5 is the partial structure diagram formed in Fig. 1 according to step S200；
Fig. 6 is the partial structure diagram formed in Fig. 1 according to step S200；
Fig. 7 is the partial structure diagram formed in Fig. 1 according to step S200；
Fig. 8 is the structural schematic diagram of the active switch in another embodiment.
Specific embodiment
The application in order to facilitate understanding is described more fully the application below with reference to relevant drawings.In attached drawing
Give the better embodiment of the application.But the application can realize in many different forms, however it is not limited to herein
Described embodiment.On the contrary, the purpose of providing these embodiments is that making to understand more disclosure of this application
Add thorough and comprehensive.
It should be noted that it can directly on the other element when element is referred to as " being fixed on " another element
Or there may also be elements placed in the middle.When an element is considered as " connection " another element, it, which can be, is directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " left side ",
" right side " and similar statement for illustrative purposes only, are not meant to be the only embodiment.
Unless otherwise defined, all technical and scientific terms used herein and the technical field for belonging to the application
The normally understood meaning of technical staff is identical.The term used in the description of the present application is intended merely to description tool herein
The purpose of the embodiment of body, it is not intended that in limitation the application.
Referring to Fig. 1, for the production method flow diagram of the active switch in an embodiment.The production of the active switch
Method may include step: S100-S300.
Step S100 provides a substrate, and deposits the first metal layer on the substrate, and to the first metal layer into
Row patterned process forms grid.
Specifically, it please assist refering to Fig. 3, substrate 10 can be glass substrate or plastic base, wherein glass substrate can be with
For no alkali borosilicate ultra-thin glass, no alkali borosilicate glass physical characteristic with higher, preferable corrosion resistance, compared with
High thermal stability and lower density and higher elasticity modulus.(Fig. 3 is not marked deposition the first metal layer on the substrate 10
Show) it can be rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.The
One metal layer (Fig. 3 is not indicated) can be the heap stack combination of one or more of molybdenum, titanium, aluminium and copper.Patterned process can
Required pattern is formed by photoetching treatment to be, that is, grid 20.The thickness range of grid 20 can be 3000 angstrom -5000
Angstrom, optionally, the thickness of grid 20 can be 3000 angstroms -4000 angstroms, further, the thickness of grid 20 can for 4000 angstroms -
5000 angstroms.It is appreciated that the thickness of grid 20 can be selected and be adjusted according to practical situations and properties of product,
This is not further limited.
Step S200 sequentially forms gate insulating layer, active layer, doped layer and source-drain electrode on the grid；Wherein, it adopts
The active layer, doped layer, source-drain electrode and a channel region are formed with wet-etching technology twice and twice dry etch process,
The channel region is through the doped layer and is partially through to the active layer.
Specifically, gate insulating layer 30, active film layer 40, doping film layer 50 and the second gold medal can be sequentially depositing on grid 20
Belong to layer (figure does not indicate).Wherein, depositing operation may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and wait
Plasma enhanced chemical vapor depositing operation.Then being coated with one layer of photoresist layer in second metal layer (figure does not indicate) top, (figure is not marked
Show), processing is patterned to photoresist layer (figure does not indicate) using one of light shield technique, obtains the photoresist with predetermined pattern
70.On this basis, first time wet-etching technology is used to perform etching to form second second metal layer (figure does not indicate)
Sub- metal layer 60, can refer to structure shown in Fig. 4.Then again using first time dry etch process to active film layer 40 and doping
Film layer 50 performs etching to form active layer 40A and doped layer 50A, while carrying out ashing processing to photoresist 70, obtains such as Fig. 5
Shown in structure, the ashing of photoresist just refers to be fallen photoresist as the target etch that is etched, generally use oxygen and photoetching
Glue reaction, generates volatile materials.Then use again second of wet-etching technology to the second sub- metal layer 60 perform etching with
Source electrode 610, drain electrode 620 are formed, can refer to Fig. 6.It is finally etching barrier layer with source electrode 610 and drain electrode 620, it is dry using second
Method etching technics performs etching doped layer 50A and active layer 40A, forms a channel region 80, can refer to Fig. 7, wherein channel region
80 run through doped layer 50A and are partially through to active layer 40A." partially running through " does not etch away positioned at the second groove all
In active layer part because active layer cannot be etched away all as conductive medium.It is appreciated that for " portion
Point " specific thickness, can make a choice and adjust according to practical condition and properties of product.Second metal layer (do not mark by figure
Show) source electrode 610 and drain electrode 620 are partitioned by channel region 80, source electrode 610 and drain electrode 620 are located at the two sides of channel region 80.
In one embodiment, the material of gate insulating layer 30 can be one of silica, silicon nitride or the two
Combination, i.e. gate insulating layer 30 can be silica, is also possible to silicon nitride, can also be the mixing of silica and silicon nitride
Object.
In one embodiment, by taking plasma reinforced chemical vapour deposition as an example.SiH can be used4Gas to be formed to deposit
Active layer 40A, using PH3And SiH4Gas to form doped layer 50A to deposit.Meanwhile the temperature for depositing doped layer 50A can be
300 DEG C -400 DEG C, optionally, the temperature for depositing doped layer 50A can be 300 DEG C -360 DEG C, and the temperature of deposition doped layer 50A can
Think 340 DEG C -360 DEG C.Further, when forming doped layer 50A, using depositing operation, meanwhile, it can be deposited by changing
PH in gas3And SiH4The mode of gas flow ratio form doped layer 50A.Further, " change " herein can be increase
It is also possible to reduce, illustratively, in the application, by PH in deposition gases3And SiH4Gas flow ratio increase to 1.25-
4.5, optionally, by PH in deposition gases3And SiH4Gas flow ratio increase to 4.1.Gas flow ratio before increase can be
1.23.The PH in " change " deposition gases3And SiH4Gas flow ratio before, the doped layer of the film transistor device of standard
Deposition gases in portion gas content are as follows: PH3Content be 11000sccm, SiH4Content be 24500sccm, H2Contain
Amount is 6700sccm, wherein the meaning of sccm is standard milliliters/minute.It is appreciated that standard thin film transistor device herein
Doped layer deposition gases in the content of portion gas can be not limited to the specific value that the application is previously mentioned, as long as ability
Common deposition gases flow is ok in domain.Other gases can also be contained in deposition gases, for example, Ar, N2And N2O.For
The flow-rate ratio of these types of gas is not further qualified, and those skilled in the art can carry out according to the performance and actual conditions of product
Selection and adjustment.Using change (increase) PH3And SiH4The mode of gas flow ratio can reduce threshold voltage shift, also may be used
Improve influence of the light leakage current to thin film transistor (TFT), while preferable IS (Image Sticking, ghost) effect can also be obtained.
In one embodiment, the thickness of remaining active layer can be 300 angstroms -900 angstroms after second of dry etching.Tool
Body, the thickness of remaining active layer here refers to the thickness of encircled portion in Fig. 7, that is to say the 40B in Fig. 7, remains here
The thickness of remaining active layer 40B can also be indicated with As Remain.The thickness of active layer 40B equally also will affect film crystal
The thickness of the stability of pipe, active layer 40B is thicker, the easier stability for influencing thin film transistor (TFT).In this application, pass through
The thickness control of remaining active layer 40B within 300 angstroms -900 angstroms, can be significantly improved light leakage current by secondary dry method etch technology
Influence to thin film transistor (TFT) stability.Further, the thickness of remaining active layer 40B can also be 400 angstroms -900 angstroms, optional
Ground, the thickness of remaining active layer 40B can be 400 angstroms -600 angstroms, and optionally, the thickness of remaining active layer 40B can also be 600
Angstroms -900 angstroms.It is appreciated that the thickness of remaining active layer 40B can be selected according to practical situations and properties of product
And adjustment, it is not further limited herein.For relatively common remaining active layer (As Remain), the application passes through drop
Low As Remain layers of thickness can improve influence of the light leakage current to thin film transistor (TFT), while enhanced film transistor device
Reliability." reliability " refer in the lab deliberately to some rugged environments of display panel, judges display surface with this
The stability of plate.
The channel region is placed in preset atmosphere and heats by step S300；Wherein, in predetermined power
It is lower that the first preset time first is heated to the channel region, it finally adjusts the predetermined power and heats the in the atmosphere of ammonia
Two preset times.
Specifically, after carrying out second of dry etching and forming channel region 80, it will cause the damage of channel region 80, simultaneously
More weak bond can be also generated at the interface of remaining active layer 40B, therefore, in order to repair the damage of channel region 80, and is reduced
The weak bond at the interface remaining active layer 40B.Channel region 80 can be placed in preset atmosphere and be heated.Specifically
, by taking plasma enhanced chemical vapor deposition technique as an example, 1s- first can be heated to channel region 80 under predetermined power
90s optionally first heats 45s；1s-80s can also be heated, optionally, first heats 40s.Then default function at this time is adjusted
Rate, and lead to ammonia to heating room, it is in channel region 80 in the atmosphere of ammonia and continues to heat 1s-60s, optionally, in ammonia
Atmosphere in continue heat 30s." adjusting " can be to be increasedd or decreased on the basis of predetermined power, and predetermined power here is
Refer to preset plasma power.Illustratively, for reducing, the application reduces after first heating 1s-90s to channel region 80
Plasma power at this time, while logical ammonia, make channel region 80 continue to heat 1s-60s in the atmosphere of ammonia.Wherein, reduce
Plasma power afterwards can be 6KW-16KW, and optionally, the plasma power after reduction can also be 6KW-11KW；It is optional
Ground.Plasma power after reduction can also be 11KW-16KW.It is appreciated that the feelings that plasma power after the decrease determines
Under condition, the specific value of predetermined power can be selected and be adjusted according to well-known to those having ordinary skill in the art or actual conditions
It is whole, it does not further limit herein.
Above-described embodiment can by using wet-etching technology twice and the active switch of dry etch process formation twice
Shorten the processing time of active switch, and relative inexpensiveness.Further, by heating channel region under predetermined power
Then first preset time reduces predetermined power and continues to heat the second preset time in the atmosphere of ammonia, can repair channel
Area is damaged as caused by etching, while can also reduce the weak bond in amorphous silicon, the irradiation and photograph of enhanced film transistor
Photostability reduces light leakage current；Further, by reducing As Remain layers of thickness, light leakage current can be improved to master
The influence of dynamic switch, and then improve and the phenomenon that IS occur in the reliability test of display device.
Further, the production method of active switch can also include: to be formed simultaneously protective layer using one of light shield technique
With correspond to the drain electrode above via hole.Further, then using one of light shield technique pixel electrode, the pixel are formed
Electrode passes through the via hole and the drain contact.Wherein, light shield technique is referred to having in aforementioned production method embodiment
Description is closed, is not repeated further herein.Pixel electrode can be indium tin oxide, indium-zinc oxide, aluminium tin-oxide, aluminium zinc
One of oxide, indium germanium zinc oxide are a variety of.
The production method of above-mentioned active switch forms active switch using 4 light shield techniques, compares 5 light shield technique saving
Processing time, reduces the production cost, while reducing a light shield technique.
The structural schematic diagram that Fig. 2 is the active switch in an embodiment is please referred to, which is opened using aforementioned active
The production method embodiment of pass is manufactured.The active switch may include: substrate 10, grid 20, and gate insulating layer 30 is active
Layer 40A, doped layer 50A and source electrode 610, drain electrode 620.Wherein, grid 20 is formed on substrate 10；Gate insulating layer 30 is formed in
On substrate 10, while gate insulating layer 30 covers grid 20；Active layer 40A is formed on gate insulating layer 30；Doped layer 50A shape
At on active layer 40A；Source electrode 610, drain electrode 620 are formed on doped layer 50A.One channel region 80 is located in doped layer 50A
Portion, channel region 80 is through doped layer 50A and is partially through to active layer 40A, and source electrode 610 and drain electrode 620 are located at channel region 80
Two sides.It is appreciated that the active switch in the present embodiment can regard thin film transistor (TFT) as.
Above-mentioned active switch is manufactured by using the production method of aforementioned active switch, and the system of aforementioned active switch
Make method by using wet-etching technology twice and the active switch of dry etch process formation twice, active switch can be shortened
The processing time of (thin film transistor (TFT)), and relative inexpensiveness.Further, by heating channel region under predetermined power
Then first preset time reduces predetermined power and continues to heat the second preset time in the atmosphere of ammonia, can repair channel
Area is damaged as caused by etching, while can also reduce the weak bond in amorphous silicon, enhancing active switch (thin film transistor (TFT))
Irradiation and irradiation stability reduce light leakage current；Further, by reducing As Remain layers of thickness, light can be improved
Influence of the leakage current to active switch (thin film transistor (TFT)), and then improve and showing for IS occur in the reliability test of display device
As.
Substrate 10 can be glass substrate or plastic base, wherein glass substrate can be the ultra-thin glass of alkali-free borosilicate
Glass, no alkali borosilicate glass physical characteristic with higher, preferable corrosion resistance, higher thermal stability and lower
Density and higher elasticity modulus.
Grid 20 is formed on substrate 10, wherein the formation process of grid 20 may include rf magnetron sputtering, heat steaming
Hair, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that the formation process of grid 20 can be with
It is selected and is adjusted according to practical situations and properties of product, be not further limited herein.The material of grid 20
It can be the heap stack combination of one or more of molybdenum, titanium, aluminium and copper；Select molybdenum, titanium, aluminium and copper can as 20 material of grid
To guarantee good electric conductivity.It is appreciated that the material of grid 20 can according to practical situations and properties of product into
Row selection and adjustment, are not further limited herein.The thickness range of grid 20 can be 3000 angstroms -5000 angstroms, optionally,
The thickness of grid 20 can be 3000 angstroms -4000 angstroms, and further, the thickness of grid 20 can be 4000 angstroms -5000 angstroms.It can be with
Understand, the thickness of grid 20 can be selected and be adjusted according to practical situations and properties of product, do not made herein into one
The restriction of step.
Gate insulating layer 30 is formed on substrate 10, and the formation process of gate insulating layer 30 may include that radio frequency magnetron splashes
It penetrates, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that gate insulating layer 30
Formation process can be selected and be adjusted according to practical situations and properties of product, do not limit further herein
It is fixed.The material of gate insulating layer 30 can be one of silica, silicon nitride or combination, i.e. gate insulating layer 30
It can be silica, be also possible to silicon nitride, can also be the mixture of silica and silicon nitride.It is appreciated that gate insulator
The material of layer 30 can be selected and be adjusted according to practical situations and properties of product, not limited further herein
It is fixed.The thickness of gate insulating layer 30 can be 3500 angstroms -4000 angstroms, and optionally, the thickness of gate insulating layer 30 can be 3500
Angstroms -3700 angstroms, further, the thickness of gate insulating layer 30 can be 3700 angstroms -4000 angstroms.It is appreciated that gate insulating layer
30 thickness can be selected and be adjusted according to practical situations and properties of product, be not further limited herein.
Active layer 40A is formed on gate insulating layer 30, and the formation process of active layer 40A may include that radio frequency magnetron splashes
It penetrates, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that the shape of active layer 40A
It can be selected and be adjusted according to practical situations and properties of product at technique, be not further limited herein.Have
The material of active layer 40A can be amorphous silicon, and active layer 40A is usually as conductive medium.The thickness of active layer 40A can be
550 angstroms -700 angstroms, optionally, active layer 40A with a thickness of 550 angstroms -600 angstroms, further, the thickness of active layer 40A can be with
It is 600 angstroms -700 angstroms.It is appreciated that the thickness of active layer 40A can be selected according to practical situations and properties of product
It selects and adjusts, be not further limited herein.
Doped layer 50A is formed on active layer 40A, the formation process of doped layer 50A may include rf magnetron sputtering,
Thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that the formation of doped layer 50A
Technique can be selected and be adjusted according to practical situations and properties of product, be not further limited herein.Doping
The thickness of layer 50A can be 400 angstroms, it will be understood that the thickness of doped layer 50A can be according to practical situations and product
It can be carried out selection and adjustment, be not further limited herein.Doped layer 50A can be carries out n-type doping in amorphous silicon layer,
Be also possible in amorphous silicon layer carry out p-type doping, optionally, doped layer 50A be n-type doping is carried out in amorphous silicon layer, meanwhile,
For N-type heavy doping, wherein doping way may include High temperature diffusion and ion implanting.High temperature diffusion is to pass through foreign atom
Gaseous sources or the diffusion of doped oxide or the surface for being deposited to silicon wafer, these impurity concentrations will be from surface to internal dullness
Decline, in High temperature diffusion, the distribution of impurity is mainly determined by high temperature with diffusion time.Ion implanting is i.e. by Doped ions
It is injected in semiconductor in the form of ion beam, impurity concentration has peak Distribution in semiconductor, in ion implanting, Impurity Distribution
Mainly determined by mass of ion and Implantation Energy.N-type doping mainly mixes pentavalent impurity element in semiconductor, such as: phosphorus,
Arsenic.Ion implanting is relative to the advantages of High temperature diffusion: 1, the ion injected is selected by mass analyzer to be chosen
The particle purity is high taken, energy is single, to ensure that doping concentration is not influenced by impurity source purity.In addition, injection process
It is carried out under cleaning, dry vacuum condition, various pollutions are preferably minimized level；2, it can accurately control and be injected into chip
Foreign atom number, implantation dosage is from 10 for adjusting threshold voltage11/cm2To forming the 10 of insulating buried layer17/cm2, range
It is wider.3, when ion implanting, substrate is generally kept under room temperature or temperature environment lower than 400 DEG C.Therefore, as silica,
Silicon nitride, aluminium and photoresist etc. may serve to the masking film alternatively adulterated, make the autoregistration masking skill in device manufacture
Art is more flexible.
Source electrode 610, drain electrode 620 are formed on doped layer 50A, and source electrode 610,620 formation process of draining may include penetrating
Frequency magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that source electrode
610, the formation process of drain electrode 620 can be selected and be adjusted according to practical situations and properties of product, not made herein
It is further to limit.Source electrode 610,620 material of draining can be the storehouse group of one or more of molybdenum, titanium, aluminium and copper
It closes；Select molybdenum, titanium, aluminium and copper that can guarantee good electric conductivity as source electrode 610,620 materials of drain electrode.The source of being appreciated that
Pole 610, drain 620 material can be selected and be adjusted according to practical situations and properties of product, do not make herein into
The restriction of one step.Source electrode 610,620 thickness of draining can be 3500 angstroms -5000 angstroms, optionally, source electrode 610, drain electrode 620
Thickness can be 3500 angstroms -4000 angstroms, further, source electrode 610, drain 620 thickness can be 4000 angstroms -5000 angstroms.
It is appreciated that source electrode 610, drain 620 material can be identical or not identical with thickness, source electrode 610, drain 620 material
Material and thickness can be selected and be adjusted according to practical situations and properties of product, be not further limited herein.
Channel region 80 is located at the middle part of doped layer 50A, and channel region 80 is through doped layer 50A and active layer is run through in part
40A.Source electrode 610 and drain electrode 620 are located in the two sides of channel region 80." running through " can be realized by photoetching or lithographic method,
Photosensitive photoresist is set to exist by exposure and imaging using the mask with a certain layer design configuration specifically, photoetching refers to
Three-dimensional relief pattern is formed on substrate.Etching refers to that under photoresist masking, the film layer for forming micrographics as needed is different, adopts
Selective etch is carried out in film layer with different etching substances and method.In this way, after removing photoresist, three dimensional design figure
It has been transferred in the related film layer of substrate.
Referring to Fig. 8, for the structural schematic diagram of active switch in another embodiment.The active switch may include substrate
10, grid 20, gate insulating layer 30, active layer 40, doped layer 50, source electrode 610, drain electrode 620 and protective layer 90.Wherein, grid
20 are formed on substrate 10；Gate insulating layer 30 is formed on substrate 10, while gate insulating layer 30 covers grid 20；Active layer
40A is formed on gate insulating layer 30；Doped layer 50A is formed on active layer 40A；Source electrode 610, drain electrode 620 are formed in doping
Layer 50A on, protective layer 90 be formed in source electrode 610, drain electrode 620 on；One channel region 80 is located at the middle part of doped layer 50A, channel region
80 run through doped layer 50A and are partially through to active layer 40A, and source electrode 610 and drain electrode 620 are positioned at the two sides of channel region 80, simultaneously
Protective layer 90 covers channel region 80.
It is appreciated that for substrate 10, grid 20, gate insulating layer 30, active layer 40A, doped layer 50A, source electrode 610,
Material, formation process, composition, the thickness etc. of drain electrode 620, are referred to the description of aforementioned active switch embodiment, herein no longer
Further progress repeats.
Protective layer 90 mainly for the protection of switching device from polluting and damaging, specifically, protective layer 90 be also referred to as PV
(Passivation, passivation) layer, the material of protective layer 90 can be the combination of silicon nitride, silica or the two.It can manage
Solution, is not particularly limited the thickness of protective layer 90, those skilled in the art can be according to practical condition and properties of product
It is selected and is adjusted.
Above-mentioned active switch is manufactured by using the production method of aforementioned active switch, and the system of aforementioned active switch
Make method by using wet-etching technology twice and the active switch of dry etch process formation twice, thin film transistor (TFT) can be shortened
Processing time, and relative inexpensiveness.Further, by channel region is heated under predetermined power first it is default when
Between, then reduce predetermined power and continue to heat the second preset time in the atmosphere of ammonia, channel region can be repaired due to etching
Caused by damage, while the weak bond in amorphous silicon can also be reduced, the irradiation and irradiation stability of enhanced film transistor, drop
Low light leakage current；Further, by reducing As Remain layers of thickness, light leakage current can be improved to thin film transistor (TFT)
It influences, and then improves and the phenomenon that IS occur in the reliability test of display device；It further, can by the way that protective layer is arranged
Protective film transistor is from damage.
A kind of display device may include the aforementioned active switch embodiment, above-mentioned display device, due to actively opening
Pass is manufactured by using the production method of aforementioned active switch, and the production method of aforementioned active switch is by using twice
Wet-etching technology and twice dry etch process form active switch, when can shorten the processing procedure of active switch (thin film transistor (TFT))
Between, and relative inexpensiveness.Further, by the way that channel region is heated the first preset time under predetermined power, then subtract
Small predetermined power simultaneously continues to heat the second preset time in the atmosphere of ammonia, can repair channel region damage as caused by etching
Wound, while the weak bond in amorphous silicon can also be reduced, the irradiation and irradiation stability of enhanced film transistor reduce light electric leakage
Stream；Further, by reducing As Remain layers of thickness, influence of the light leakage current to thin film transistor (TFT) can be improved, in turn
Improve and the phenomenon that IS occurs in the reliability test of display device.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
The limitation to claim therefore cannot be interpreted as.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the concept of this application, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of production method of active switch, which is characterized in that the production method of the active switch includes:
One substrate is provided, and deposits the first metal layer on the substrate, and patterned process is carried out to the first metal layer,
Form grid；
Gate insulating layer, active layer, doped layer and source-drain electrode are sequentially formed on the grid；
Wherein, use wet-etching technology twice and twice dry etch process formed the active layer, doped layer, source-drain electrode with
And a channel region, the channel region is through the doped layer and is partially through to the active layer；
The channel region is placed in preset atmosphere and is heated；Wherein, first to the ditch under predetermined power
The first preset time is heated in road area, finally adjusts the predetermined power and heats the second preset time in the atmosphere of ammonia.
2. the production method of active switch according to claim 1, which is characterized in that the successively shape on the grid
The step of at gate insulating layer, active layer, doped layer and source-drain electrode, comprising:
Gate insulating layer, active film layer, doping film layer and second metal layer are sequentially depositing on the grid；
It is coated with a layer photoresist in the second metal layer, and patterned process is carried out to the photoresist；
First time wet-etching technology is used to perform etching to form the second sub- metal layer the second metal layer；
First time dry etch process is used to perform etching to form active layer and doping the active film layer and doping film layer
Layer is simultaneously ashed the photoresist；
Second of wet-etching technology is used to perform etching to form source-drain electrode the described second sub- metal layer；
Second of dry etch process is used to perform etching the active layer and doped layer to form channel region, the channel region
Through the doped layer and partially it is through to the active layer.
3. the production method of active switch according to claim 1, which is characterized in that first preset time be 1 second-
90 seconds, second preset time was -60 seconds 1 second.
4. the production method of active switch according to claim 2, which is characterized in that remained after second of dry etching
The remaining active layer with a thickness of 300 angstroms -900 angstroms.
5. the production method of active switch according to claim 1, which is characterized in that forming the doped layer is using heavy
Accumulate technique, PH in deposition gases3And SiH4Gas flow ratio be 1.25-4.5.
6. the production method of active switch according to claim 1, which is characterized in that it is described adjust the predetermined power it
Power bracket afterwards is 6KW-16KW.
7. a kind of active switch, which is characterized in that use the production method of active switch as claimed in any one of claims 1 to 6
It is manufactured, the active switch includes:
Substrate；
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the grid；
Active layer is formed on the gate insulating layer；
Doped layer is formed on the active layer；And
The source electrode being formed on the doped layer and drain electrode；
Wherein, a channel region is located at the middle part of the doped layer, and the channel region is through the doped layer and is partially through to institute
Active layer is stated, the source electrode and drain electrode are located at the two sides of the channel region.
8. active switch according to claim 7, which is characterized in that the thickness range of the grid is 3000 angstrom -5000
Angstrom.
9. active switch according to claim 7, which is characterized in that the thickness range of the gate insulating layer is 3500
Angstroms -4000 angstroms.
10. a kind of display device, which is characterized in that including such as described in any item active switches of claim 7-9.
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| CN201811543287.7A CN109616417A (en) | 2018-12-17 | 2018-12-17 | Active switch and preparation method thereof, display device |
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| CN201811543287.7A CN109616417A (en) | 2018-12-17 | 2018-12-17 | Active switch and preparation method thereof, display device |
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| CN115377208A (en) * | 2021-05-20 | 2022-11-22 | 合肥京东方显示技术有限公司 | Thin film transistor, manufacturing method thereof, array substrate, display panel and device |
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