CN109103105A - Thin film transistor (TFT) and preparation method thereof, display device - Google Patents
Thin film transistor (TFT) and preparation method thereof, display device Download PDFInfo
- Publication number
- CN109103105A CN109103105A CN201810837308.XA CN201810837308A CN109103105A CN 109103105 A CN109103105 A CN 109103105A CN 201810837308 A CN201810837308 A CN 201810837308A CN 109103105 A CN109103105 A CN 109103105A
- Authority
- CN
- China
- Prior art keywords
- amorphous silicon
- silicon layer
- layer
- tft
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 75
- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 123
- 238000000034 method Methods 0.000 claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000007789 gas Substances 0.000 claims description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 22
- 238000001312 dry etching Methods 0.000 claims description 16
- 229910018503 SF6 Inorganic materials 0.000 claims description 12
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 11
- 239000000460 chlorine Substances 0.000 claims description 11
- 229910052801 chlorine Inorganic materials 0.000 claims description 11
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 11
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 11
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 10
- 229910000077 silane Inorganic materials 0.000 claims description 9
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 239000003085 diluting agent Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000005234 chemical deposition Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000014759 maintenance of location Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 21
- 239000000463 material Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 230000006872 improvement Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000005286 illumination Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000003550 marker Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000016768 molybdenum Nutrition 0.000 description 1
- -1 silicon Alkane Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a kind of thin film transistor (TFT) and its manufacturing methods, display device, and wherein method includes: offer substrate；Grid is formed on the substrate；Gate insulating layer is formed on the substrate, and the gate insulating layer is made to cover the grid；Amorphous silicon layer is formed on the gate insulating layer；N+ type doped amorphous silicon layer is formed on the amorphous silicon layer；Wherein, the ratio of control doping gas and silicon source is 0.82~1.54 or 1.74~4.1；Source-drain electrode metal layer is formed on the N+ type doped amorphous silicon layer；And the source-drain electrode metal layer, the N+ type doped amorphous silicon layer and the amorphous silicon layer are performed etching, to obtain source electrode and drain electrode.The preparation method of above-mentioned thin film transistor (TFT) can be effectively improved the image retention problem using the display device of the thin film transistor (TFT).
Description
Technical field
The present invention relates to technical field of semiconductors, fill more particularly to a kind of thin film transistor (TFT) and preparation method thereof, display
It sets.
Background technique
Traditional amorphous silicon film transistor (a-Si TFT) processing procedure generally use BCE (Back Channel Etching,
Carry on the back channel etching) type structure.The infrastructure cost wants low compared to ES (Etching Stop, etch stopper) type structure and technique is simple
It is single.But since Back Channel interface state is poor, the leakage current of TFT is larger, easily causes the image retention of display screen
(Image Sticking, IS) problem.
Summary of the invention
Based on this, it is necessary to aiming at the problem that traditional thin film transistor (TFT) is easy to cause image retention to display device, mention
For a kind of thin film transistor (TFT) and its manufacturing method, display device.
A kind of preparation method of thin film transistor (TFT), comprising:
Substrate is provided；
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate, and the gate insulating layer is made to cover the grid；
Amorphous silicon layer is formed on the gate insulating layer；
N+ type doped amorphous silicon layer is formed on the amorphous silicon layer；Wherein, the ratio of control doping gas and silicon source is
0.82~1.54 or 1.74~4.1；
Source-drain electrode metal layer is formed on the N+ type doped amorphous silicon layer；And
The source-drain electrode metal layer, the N+ type doped amorphous silicon layer and the amorphous silicon layer are performed etching, to obtain
Source electrode and drain electrode.
The preparation method of above-mentioned thin film transistor (TFT), when forming N+ type doped amorphous silicon layer by the way that gas and silicon source will be adulterated
Ratio is controlled 0.82~1.54 or 1.74~4.1, it can be ensured that the thin film transistor (TFT) that is finally prepared is under light illumination
Stability is preferable, has lesser leakage current, so as to be effectively improved the image for the display device for using the thin film transistor (TFT)
Residue problem.
The ratio of the doping gas and silicon source is 0.82~1.23 or 2.46~4.1 in one of the embodiments,.
The ratio of the doping gas and silicon source is 2.46~2.79 or 3.28~4.1 in one of the embodiments,.
The doping gas is hydrogen phosphide in one of the embodiments, and the silicon source is silane.
It is described in the step of forming N+ type doped amorphous silicon layer on the amorphous silicon layer in one of the embodiments,
Diluent gas can be passed through；The flow of the diluent gas be 24000 milliliters per minute~25000 milliliters per minute；The silicon source
Flow be 6200 milliliters per minute~7200 milliliters per minute.
It is described in the step of forming N+ type doped amorphous silicon layer on the amorphous silicon layer in one of the embodiments,
The N+ type doped amorphous silicon layer is formed on the amorphous silicon layer using plasma enhanced chemical vapor chemical deposition.
It is described to the source-drain electrode metal layer, the N+ type doped amorphous silicon layer and described in one of the embodiments,
The step of amorphous silicon layer performs etching are as follows:
Mask plate is formed on the source-drain electrode metal layer；And
Use twice wet etching and twice dry etch process to the source-drain electrode metal by exposure mask of the mask plate
Layer, the N+ type doped amorphous silicon layer and the amorphous silicon layer perform etching；Wherein, in second dry etching, control is penetrated
Frequency source power is 2 kilowatts~5 kilowatts, and RF bias power is 7 kilowatts~3 kilowatts, and etch period is 35 seconds~50 seconds, channel region
The layer semiconductor thickness of top is 400 angstroms~700 angstroms.
In one of the embodiments, in second dry etching, etching gas includes chlorine and sulfur hexafluoride, chlorine
Ratio with sulfur hexafluoride is 1:20~1:50.
A kind of thin film transistor (TFT), comprising:
Substrate；
The grid being formed on the substrate；
It is formed on the substrate and covers the gate insulating layer of the grid；
The amorphous silicon layer being formed on the gate insulating layer；
The N+ type doped amorphous silicon layer being formed on the amorphous silicon layer；And
It is formed on the gate insulating layer and connects with the two sides of the amorphous silicon layer and the N+ type doped amorphous silicon layer
The source electrode and drain electrode of touching；
Wherein, the N+ type doped amorphous silicon layer use ratio for 0.82~1.54 or 1.74~4.1 doping gas and
Silane is prepared.
A kind of display device, including display panel, the array substrate in the display panel include such as previous embodiment institute
The thin film transistor (TFT) stated.
Detailed description of the invention
Fig. 1 is the preparation method of the thin film transistor (TFT) in an embodiment；
Fig. 2 is the device architecture schematic diagram completed after step S120；
Fig. 3 is the device architecture schematic diagram completed after step S130；
Fig. 4 is the device architecture schematic diagram completed after step S140；
Fig. 5 is the device architecture schematic diagram completed after step S150；
Fig. 6 is the device architecture schematic diagram completed after step S160；
Fig. 7 is the device architecture schematic diagram completed after step S170；
Fig. 8 a is the flow chart of a specific embodiment of step S170；
Fig. 8 b is the flow chart of a specific embodiment of the step S720 in Fig. 8 a；
Fig. 9 is that deposition forms the structural schematic diagram after photoresist layer on source-drain electrode metal layer；
Figure 10 is the device architecture schematic diagram completed after step S710；
Figure 11 is the device architecture schematic diagram completed after step S722；
Figure 12 is the device architecture schematic diagram completed after step S724；
Figure 13 is the device architecture schematic diagram completed after step S726；
Figure 14 is the cut-off current of the thin film transistor (TFT) with different amorphous silicon residual thickness and homogeneity with voltage
Change curve；
Figure 15 is that cut-off current size of the thin film transistor (TFT) under different voltages in different embodiments corresponds to table.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
In the description of the present invention, it is to be understood that, term " center ", " transverse direction ", "upper", "lower" "left", "right",
The orientation or positional relationship of the instructions such as "vertical", "horizontal", "top", "bottom", "inner" and "outside" is side based on the figure
Position or positional relationship, are merely for convenience of description of the present invention and simplification of the description, rather than the device or member of indication or suggestion meaning
Part must have a particular orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.This
Outside, term " first ", " second " etc. are used for description purposes only, and should not be understood as indicating or implying relative importance or hidden
The quantity of indicated technical characteristic is indicated containing ground.The feature of " first ", " second " that limit as a result, can be expressed or imply
Including one or more this feature.
In the present description and drawings, the reference marker N and P for distributing to layer or region indicate that these layers or region wrap respectively
Include a large amount of electronics or hole.Further, the concentration of the reference marker+and-expression dopant of distributing to N or P is higher or lower than
The concentration not being assigned in this way in the layer of label.In the description and attached drawing of preferred embodiment below, similar component point
Equipped with omitting its redundant description at similar reference marker and this.
Fig. 1 is the flow chart of the preparation method of the thin film transistor (TFT) in an embodiment.Referring to Fig. 1, this method includes following
Step:
Step S110, provides substrate.
Substrate can be prepared using the known material in this fields such as glass or plastics.In the present embodiment, with
Prepared on substrate device side be it is upper, under opposite side is.
Step S120, forms grid on substrate.
Grid can be prepared using physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) technique.
In the present embodiment, grid can be prepared using magnetron sputtering technique.Specifically, the knot of flood is first deposited on substrate
Then structure is patterned this layer of structure and required gate structure is finally prepared.The material of grid can be aluminium, copper
The combination of one or more of equal conductive materials.Fig. 2 is the structural schematic diagram completed after step S120.In Fig. 2,910 tables
Show substrate, 920 indicate grid.
Step S130, forms gate insulating layer on substrate, and gate insulating layer is made to cover grid.
Fig. 3 is the structural schematic diagram completed after step S130.The material of gate insulating layer 930 can be silica or nitrogen
SiClx.The material of gate insulating layer 930 may be the combination of silica or silicon nitride.It is appreciated that gate insulating layer 930
It can also be prepared using the known material of other skilled in the art.Gate insulating layer 930 can be enhanced using plasma
Chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD) successive sedimentation is formed.
Step S140, forms amorphous silicon layer on gate insulating layer.
Fig. 4 is the structural schematic diagram completed after step S140.Amorphous silicon (amorphous silicon, a-Si) is also known as nothing
Shape silicon, is a kind of form of elemental silicon.Amorphous silicon does not have complete diamond structure cell, and purity is not high, but its fusing point, close
Degree and hardness are significantly lower than crystalline silicon.Amorphous silicon layer (a-Si layers) 940 is used as active layer, can equally be enhanced using plasma
Chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD) successive sedimentation is formed.
Step S150 forms N+ type doped amorphous silicon layer on amorphous silicon layer.
Fig. 5 is the structural schematic diagram completed after step S150.Wherein, N+ type doped amorphous silicon layer 950 is formed in amorphous silicon
940 top of layer.In the present embodiment, using plasma enhanced chemical vapor chemical deposition (Plasma Enhanced Chemical
Vapor Deposition, PECVD) successive sedimentation forms N+ type doped amorphous silicon layer 940, and during the deposition process, controls
The ratio for adulterating gas and silicon source is 0.82~1.54 or 1.74~4.1.Ratio by that will adulterate gas and silicon source controls
0.82~1.54 or 1.74~4.1, it can be ensured that finally formed thin film transistor (TFT) has preferable stability under light illumination.
In one embodiment, doping gas is hydrogen phosphide (PH3), silicon source is silane (SiH4).In the present embodiment, it is depositing
In the process, it can be passed through diluent gas such as hydrogen (H simultaneously2), but for traditional processing procedure, it can't be to diluent gas
And the flow of silicon source adjusts, and adjust the flow of doping gas only to reach the effect for the ratio for changing doping gas and silicon source
Fruit.In one embodiment, control diluent gas flow be 24000 milliliters per minute~25000 milliliters per minute；Control silicon source
Flow be 6200 milliliters per minute~7200 milliliters per minute.The N+ type doped amorphous silicon layer 950 and amorphous silicon layer 940 of formation
The semiconductor layer of thin film transistor (TFT) is collectively formed.
Step S160 forms source-drain electrode metal layer on N+ type doped amorphous silicon layer.
Source-drain electrode metal layer can equally use physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) work
Skill is prepared.For example, source-drain electrode metal layer can be prepared using magnetron sputtering technique.Fig. 6 is after completing step S160
Device architecture schematic diagram.Source-drain electrode metal layer 970 can be prepared using conductive materials such as aluminium, copper and molybdenums.
Step S170 performs etching source-drain electrode metal layer, N+ type doped amorphous silicon layer and amorphous silicon layer, to obtain source electrode
And drain electrode.
Thin film transistor (TFT) includes active area and passive region, and wherein passive region surrounds active area.It is thin for being arranged in active area
The structures such as the source-drain electrode of film transistor.In etching process, the source above the passive region and channel region by thin film transistor (TFT) is needed
Drain metal layer removal, and only retain the metal layer of source drain region.It is also desirable to by above the passive region of thin film transistor (TFT)
Semiconductor layer removal, that is, by passive region N+ type doped amorphous silicon layer 950 and amorphous silicon layer 940 etch away.This
Outside, it is also necessary to the N+ type doped amorphous silicon layer 950 above the channel region of thin film transistor (TFT) be etched completely, and to above channel region
940 part of amorphous silicon layer removal so that channel region above there are amorphous silicon residual thickness.
Fig. 7 is the structural schematic diagram completed after step S170.Wherein, 970 be source-drain electrode metal layer.In the present embodiment,
Groove body is formed on N+ type doped amorphous silicon layer 2950 and amorphous silicon layer 940 to form thin film transistor (TFT) below present groove body
Channel 960.Source S and drain D are separately positioned on the two sides of groove body.
The preparation method of above-mentioned thin film transistor (TFT), when forming N+ type doped amorphous silicon layer by the way that gas and silicon source will be adulterated
Ratio is controlled 0.82~1.54 or 1.74~4.1, it can be ensured that the thin film transistor (TFT) that is finally prepared is under light illumination
Stability is preferable, has lesser leakage current, so as to be effectively improved the image for the display device for using the thin film transistor (TFT)
Residue problem.
In one embodiment, in step S150, during the deposition process, control doping gas and silicon source ratio be 0.82~
1.23 or 2.46~4.1.In another embodiment, in step S150, during the deposition process, control doping gas and silicon source
Ratio is 2.46~2.79 or 3.69~4.1.For example, during the deposition process, the ratio that can control doping gas and silicon source is
3.28 2.46.In other examples, the ratio that can control doping gas and silicon source is 2.79 or 3.69, another
In embodiment, the ratio that can control doping gas and silicon source is 0.82 or 1.23.
For the beneficial effect that the thin film transistor (TFT) that the preparation method of above-mentioned thin film transistor (TFT) is prepared is better described, under
It is obtained behind panel burning attached 24 hours of the thin film transistor (TFT) with different proportion (ratio of doping gas and silicon source) respective
Image retention (IS) grade.Same ratio uses two samples and is tested, and adulterating gas and selecting is hydrogen phosphide, and silicon source is silicon
Alkane, test result is as follows:
1) when hydrogen phosphide and silicon source ratio are 2.46, IS result is respectively L1S2 and L1S1；
2) when hydrogen phosphide and silicon source ratio are 2.79, IS result is respectively L1S1 and L0S0；
3) when hydrogen phosphide and silicon source ratio are 3.28, IS result is respectively L0S0 and L0S0；
4) when hydrogen phosphide and silicon source ratio are 0.82, IS result is respectively L1S2 and L1S1.
In IS grade, the subsequent number the big, indicates that IS is poorer.Therefore it can be seen that above-mentioned side according to the above results
The thin film transistor (TFT) that method is prepared can achieve the purpose that image retention (IS) problem for improving display device.
In one embodiment, include the following steps in step S170, as shown in Figure 8 a.
Step S710 forms patterned photoresist layer on source-drain electrode metal layer.
Firstly, depositing the photoresist layer 90 of a flood on source-drain electrode metal layer, as shown in Figure 9.Photoresist layer uses photoresist
It is formed.Secondly, being exposed using gray level mask plate or half rank mask plate to the substrate for being coated with photoresist layer, develop formation packet
The photoresist layer of photoresist reserved area, half reserved area of photoresist and photoresist removal area is included, as shown in Figure 10.In Figure 10, grayscale
Mask plate 80 includes complete opaque area 84, semi-opaque region 86 and complete transparent area 82.Wherein, opaque area 84 completely corresponds to
Photoresist reserved area, namely the source electrode and drain electrode region of the active area corresponding to thin film transistor (TFT)；Semi-opaque region 86 corresponds to light
Half reserved area of photoresist, namely corresponding to the channel region of thin film transistor (TFT), complete transparent area 82 then corresponds to photoresist and removes area,
Correspond to the passive region of thin film transistor (TFT).
Step S720 uses twice wet etching and twice dry etch process to source-drain electrode metal by exposure mask of photoresist layer
Layer, N+ type doped amorphous silicon layer and amorphous silicon layer perform etching.
It completes after step S728 and removes the device architecture schematic diagram after photoresist layer referring to Fig. 7.Twice wet etching and
Twice dry etching (2Wet 2Dry, abbreviation 2W2D) can be realized using traditional technique.In the present embodiment, mainly pass through
Second dry etching process is improved, to realize the improvement to thin-film transistor performance, and then reaches to improve to use and be somebody's turn to do
The Image sticking problems of the display device of thin film transistor (TFT).Second dry etching is mainly to the semiconductor layer above channel region
It performs etching.Specifically, during second dry etching, control RF source power is 2 kilowatts~5 kilowatts, radio-frequency bias
Power is 7 kilowatts~3 kilowatts, and etch period is 35 seconds~50 seconds.It, can be with by controlling second dry etching process
The thickness T of semiconductor layer is controlled at 700 angstroms hereinafter, so as to reduce the cut-off current of thin film transistor (TFT), and then improves and make
With the figure residue problem of the display panel of the thin film transistor (TFT).Specifically, amorphous silicon residual thickness T is smaller, corresponding thin
The cut-off current of film transistor is then smaller, is asked to be effectively improved using the image residue of the display device of the thin film transistor (TFT)
Topic.By being adjusted within the above range to source power, bias power and etch period, amorphous silicon residual can be made thick
Degree T reaches 700 angstroms hereinafter, such as 600 angstroms or 500 angstroms.For example, in one embodiment, RF source power can be arranged
It is 4 kilowatts, RF bias power is set as 4 kilowatts, and etch period is set as 46 seconds, and corresponding amorphous silicon residual thickness can at this time
To reach the 550 Izods right side.
In one embodiment, in second dry etching, using chlorine (Cl2) and sulfur hexafluoride (SF6) it is used as etching gas.
Also, the ratio of chlorine and sulfur hexafluoride is in 1:20~1:50.It is controlled by the ratio to chlorine and sulfur hexafluoride, it can be with
Ensure the homogeneity of amorphous silicon residual layer, and then ensure thin film transistor (TFT) throughout there is uniform cut-off current.Implement one
In example, the ratio of chlorine and sulfur hexafluoride is 1:25 or 1:35 or 1:40.Pass through the ratio to chlorine and sulfur hexafluoride
It adjusts, may be implemented to control the homogeneity of amorphous silicon residual thickness within ± 200 angstroms.It in one embodiment, can will be non-
The homogeneity of crystal silicon residual thickness is controlled in ± 125 angstroms, ± 100 angstroms, even ± 75 angstroms.
In one embodiment, step S720, also 2W2D technical process is included the steps that in as shown in Figure 8 b.Specifically,
Including following sub-step:
Step S722 carries out first of wet process quarter to source-drain electrode metal layer using wet-etching technology using photoresist layer as exposure mask
Erosion, removal photoresist remove the source-drain electrode metal layer below area.
Figure 11 is the device architecture schematic diagram completed after step S722.First of wet etching process can remove photoresist and go
Except the source-drain electrode metal layer 970 of (namely passive region) below area, and retain the source-drain electrode metal layer 970 of active area.First wet
Method etching process can't perform etching such as N+ type doped amorphous silicon layer 950 of other layers other than source-drain electrode metal layer 970.Tool
Body etching process belong to any technique commonly known, this place does not repeat.
Step S724, using photoresist layer as exposure mask using dry etch process to N+ type doped amorphous silicon layer and amorphous silicon layer into
First of dry etching of row, removal photoresist remove N+ type doped amorphous silicon layer and amorphous silicon layer below area.
Figure 12 is the device architecture schematic diagram completed after step S724.First of dry etching process can remove photoresist and go
Except the N+ type doped amorphous silicon layer 950 and amorphous silicon layer 940 of (namely passive region) below area, and retain the N+ type doping of active area
Amorphous silicon layer 950 and amorphous silicon layer 940.First of dry etching process can't be to the gate insulator of 940 lower section of amorphous silicon layer
Layer 930 performs etching.Specifically etching process belongs to any technique commonly known, this place does not repeat.
Step S726 carries out second wet process quarter to source-drain electrode metal layer using wet-etching technology using photoresist layer as exposure mask
Erosion removes residual photoresist and source-drain electrode metal layer below half reserved area of photoresist.
Figure 13 is the device architecture schematic diagram completed after step S726.Second wet etching process can remove photoresist half
Remaining photoresist layer 90 and source-drain electrode metal layer 970 below reserved area (namely above channel region), so that only existing
Source electrode and drain electrode region remains with source-drain electrode metal layer 970.Second dry etching process can't be to source-drain electrode metal layer 970
Such as N+ type doped amorphous silicon layer 950 of other layers in addition performs etching.Specifically etching process belongs to any technique commonly known,
This place does not repeat.
Step S728, using photoresist layer as exposure mask using dry etch process to N+ type doped amorphous silicon layer and amorphous silicon layer into
Row second dry etching removes the N+ type doped amorphous silicon layer and portion of amorphous silicon layer of half reserved area of photoresist.
Second dry etching process by the agency of in front.
For the beneficial effect that the thin film transistor (TFT) that the preparation method of above-mentioned thin film transistor (TFT) is prepared is better described, under
Face combines the test result under different specific embodiments to be illustrated.Figure 14 is with different amorphous silicon residual thickness and uniform
The cut-off current Ioff of the thin film transistor (TFT) of property with voltage change curve.In the present embodiment, it is with amorphous silicon residual thickness T
The thin film transistor (TFT) of (700 angstroms ± 150 angstroms) is illustrated as a control group (STD).In the present embodiment, amorphous silicon residual is prepared
Parameter required for thin film transistor (TFT) with a thickness of (700 angstroms ± 150 angstroms) includes: that RF source power is 3 kilowatts, and bias power is
5 kilowatts, etch period is 40 seconds, and the ratio of chlorine and sulfur hexafluoride is 1:40.Prepare amorphous silicon residual thickness be (700 angstroms ±
125 angstroms) thin film transistor (TFT) required for parameter include: RF source power be 4 kilowatts, bias power be 4 kilowatts, etch period
It is 40 seconds, the ratio of chlorine and sulfur hexafluoride is 1:35.In Figure 14, abscissa is voltage, and ordinate is cut-off current；L1 is non-
Crystal silicon residual thickness is the current voltage curves of the thin film transistor (TFT) of (700 ± 125) angstrom；L2 is that amorphous silicon residual thickness is
The current voltage curves of the thin film transistor (TFT) of (600 ± 125) angstrom；L1 is that amorphous silicon residual thickness is (500 ± 125) angstrom
The current voltage curves of thin film transistor (TFT).It can be seen from the figure that amorphous silicon residual thickness is smaller and homogeneity is better,
Then the cut-off current of corresponding thin film transistor (TFT) is smaller, so as to bring preferably image residue improvement.Figure 15 is not
Table is corresponded to cut-off current size of the thin film transistor (TFT) in embodiment under different voltages.In Figure 15, I (- 20V) indicates voltage
Electric current when for -20V, I (- 6V) indicate that electric current when voltage is -6V, I (20V) indicate electric current when voltage is 20V.From Figure 15
In it can also be seen that L3 be located at each curve bottom namely amorphous silicon residual be (500 angstroms ± 125 angstroms) thin film transistor (TFT)
With lesser cut-off current namely its can bring preferable image residue improvement.
In order to more intuitively illustrate thin film transistor (TFT) that the preparation method of above-mentioned thin film transistor (TFT) is prepared beneficial under
Ditch obtains respective image retention after burning attached 24 hours to the panel with the thin film transistor (TFT) in different embodiments below
(IS) grade.It wherein, is not that the thin film transistor (TFT) in the same embodiment is adopted caused by accidentalia for proof result
It is tested with two samples, test result is as follows:
1) for amorphous silicon residual thickness at (500 angstroms ± 125 angstroms), IS result is respectively L0S0 and L2S5；
2) for amorphous silicon residual thickness at (700 angstroms ± 150 angstroms), IS result is respectively L3S4 and L5S6.
In IS grade, the subsequent number the big, indicates that IS is poorer.Therefore it can be seen that amorphous silicon according to the above results
Residual thickness its image residue grade at (500 angstroms ± 125 angstroms) is significantly lower than image of the thickness at (700 angstroms ± 150 angstroms)
Residue Grade namely its with better image residue improvement.It is appreciated that after source electrode and drain electrode is prepared also
The preparation for forming passivation layer in device surface, aperture being carried out to passivation layer and carries out electrode (ITO) etc. is needed, to finally obtain
The thin film transistor (TFT).
One embodiment of the invention also provides a kind of thin film transistor (TFT), and method described in aforementioned any embodiment is used to prepare
It obtains.Specifically, the thin film transistor (TFT) in an embodiment includes substrate 910, the grid being formed on substrate 910 920, is formed in
On substrate 910 and covers the gate insulating layer 930 of grid 920, the amorphous silicon layer 940 being formed on gate insulating layer 930, formed
In the N+ type doped amorphous silicon layer 950 on amorphous silicon layer 940 and be formed on gate insulating layer 930 and and amorphous silicon layer
The source S and drain D that the two sides of 940 and N+ type doped amorphous silicon layer 950 are in contact, referring to Fig. 7.
Substrate 910 can be prepared using the known material in this fields such as glass or plastics.In the present embodiment, with base
Prepared on plate 910 device side be it is upper, under opposite side is.The material of grid 920 can be in the conductive materials such as aluminium or copper
One or more kinds of combinations.The material of gate insulating layer 930 can be silicon nitride or silica, or silicon nitride
With the combination of silica.It is appreciated that gate insulating layer 930 can also using the known material of other skilled in the art come
Preparation.
In the present embodiment, N+ type doped amorphous silicon layer 240 uses ratio to mix for 0.82~1.54 or 1.74~4.1
Miscellaneous gas and silane are prepared.In one embodiment, N+ type doped amorphous silicon layer 940 can use ratio for 3.28 or 2.46
Doping gas and silane be prepared.In other examples, N+ type doped amorphous silicon layer 940 can use ratio for
2.79,3.69 or 4.1 doping gas and silane are prepared.In another embodiment, N+ type doped amorphous silicon layer 940 can
To use ratio to be prepared for 0.82 or 1.23 doping gas and silane.Therefore the thin film transistor (TFT) have under light illumination compared with
Good stability, so as to improve the Image sticking problems of panel.
In one embodiment, the amorphous silicon residual thickness T above the channel region of thin film transistor (TFT) 960 700 angstroms with
Under, such as 600 angstroms or 500 angstroms etc., homogeneity can control within ± 200 angstroms.It in one embodiment, can be by amorphous
The homogeneity of silicon residual thickness is controlled in ± 125 angstroms, ± 100 angstroms, even ± 75 angstroms.By residual to the amorphous silicon above channel region
Thickness and homogeneity is stayed to carry out the Image sticking problems for the display panel that control can be effectively improved using the thin film transistor (TFT),
Specific beneficial effect has been described above in aforementioned preparation process.
One embodiment of the invention also provides a kind of display device comprising display panel.Display panel includes array substrate,
Thin film transistor (TFT) in the array substrate is using thin film transistor (TFT) described in aforementioned any embodiment, so as to improve display dress
The image retention problem set.Display panel can be LCD, OLED, QLED and plasma panel etc..Display panel can be with plane
Type panel may be curved face type panel.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of preparation method of thin film transistor (TFT) characterized by comprising
Substrate is provided；
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate, and the gate insulating layer is made to cover the grid；
Amorphous silicon layer is formed on the gate insulating layer；
N+ type doped amorphous silicon layer is formed on the amorphous silicon layer；Wherein, control doping gas and silicon source ratio be 0.82~
1.54 or 1.74~4.1；
Source-drain electrode metal layer is formed on the N+ type doped amorphous silicon layer；And
The source-drain electrode metal layer, the N+ type doped amorphous silicon layer and the amorphous silicon layer are performed etching, to obtain source electrode
And drain electrode.
2. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that the ratio of the doping gas and silicon source
Example is 0.82~1.23 or 2.46~4.1.
3. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that the ratio of the doping gas and silicon source
Example is 2.46~2.79 or 3.28~4.1.
4. the preparation method of any thin film transistor (TFT) according to claim 1~3, which is characterized in that the doping gas is
Hydrogen phosphide, the silicon source are silane.
5. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that described on the amorphous silicon layer
In the step of forming N+ type doped amorphous silicon layer, diluent gas can be passed through；The flow of the diluent gas is 24000 milliliters every point
Clock~25000 milliliter are per minute；The flow of the silicon source be 6200 milliliters per minute~7200 milliliters per minute.
6. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that described on the amorphous silicon layer
In the step of forming N+ type doped amorphous silicon layer, formed on the amorphous silicon layer using plasma enhanced chemical vapor chemical deposition
The N+ type doped amorphous silicon layer.
7. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that described to the source-drain electrode metal
The step of layer, the N+ type doped amorphous silicon layer and the amorphous silicon layer perform etching are as follows:
Patterned photoresist layer is formed on the source-drain electrode metal layer；And
Use twice wet etching and twice dry etch process to the source-drain electrode metal layer, institute by exposure mask of the photoresist layer
It states N+ type doped amorphous silicon layer and the amorphous silicon layer performs etching；Wherein, in second dry etching, radio frequency source function is controlled
Rate is 2 kilowatts~5 kilowatts, and RF bias power is 7 kilowatts~3 kilowatts, and etch period is 35 seconds~50 seconds, above channel region
Layer semiconductor thickness is 400 angstroms~700 angstroms.
8. the preparation method of thin film transistor (TFT) according to claim 7, which is characterized in that in second dry etching,
Etching gas includes chlorine and sulfur hexafluoride, and the ratio of chlorine and sulfur hexafluoride is 1:20~1:50.
9. a kind of thin film transistor (TFT) characterized by comprising
Substrate；
The grid being formed on the substrate；
It is formed on the substrate and covers the gate insulating layer of the grid；
The amorphous silicon layer being formed on the gate insulating layer；
The N+ type doped amorphous silicon layer being formed on the amorphous silicon layer；And
It is formed in and is in contact with the two sides of the amorphous silicon layer and the N+ type doped amorphous silicon layer on the gate insulating layer
Source electrode and drain electrode；
Wherein, the N+ type doped amorphous silicon layer use ratio for 0.82~1.54 or 1.74~4.1 doping gas and silane
It is prepared.
10. a kind of display device, including display panel, which is characterized in that the array substrate in the display panel includes as weighed
Benefit require 9 described in thin film transistor (TFT).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810837308.XA CN109103105A (en) | 2018-07-26 | 2018-07-26 | Thin film transistor (TFT) and preparation method thereof, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810837308.XA CN109103105A (en) | 2018-07-26 | 2018-07-26 | Thin film transistor (TFT) and preparation method thereof, display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109103105A true CN109103105A (en) | 2018-12-28 |
Family
ID=64847550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810837308.XA Pending CN109103105A (en) | 2018-07-26 | 2018-07-26 | Thin film transistor (TFT) and preparation method thereof, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109103105A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111129037A (en) * | 2019-12-25 | 2020-05-08 | Tcl华星光电技术有限公司 | TFT array substrate and manufacturing method thereof |
| WO2021128462A1 (en) * | 2019-12-26 | 2021-07-01 | Tcl华星光电技术有限公司 | Tft array substrate and manufacturing method therefor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917199A (en) * | 1998-05-15 | 1999-06-29 | Ois Optical Imaging Systems, Inc. | Solid state imager including TFTS with variably doped contact layer system for reducing TFT leakage current and increasing mobility and method of making same |
| TW200915573A (en) * | 2007-09-29 | 2009-04-01 | Chunghwa Picture Tubes Ltd | Thin film transistor, pixel structure and fabricating methods thereof |
| CN102007597A (en) * | 2008-04-17 | 2011-04-06 | 应用材料股份有限公司 | Low temperature thin film transistor process, device property, and device stability improvement |
-
2018
- 2018-07-26 CN CN201810837308.XA patent/CN109103105A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917199A (en) * | 1998-05-15 | 1999-06-29 | Ois Optical Imaging Systems, Inc. | Solid state imager including TFTS with variably doped contact layer system for reducing TFT leakage current and increasing mobility and method of making same |
| TW200915573A (en) * | 2007-09-29 | 2009-04-01 | Chunghwa Picture Tubes Ltd | Thin film transistor, pixel structure and fabricating methods thereof |
| CN102007597A (en) * | 2008-04-17 | 2011-04-06 | 应用材料股份有限公司 | Low temperature thin film transistor process, device property, and device stability improvement |
Non-Patent Citations (2)
| Title |
|---|
| 张定涛 等: "大尺寸TFT-LCD ECCP刻蚀工艺低耗整合", 《液晶与显示》 * |
| 闫方亮 等: "a-Si厚度对TFT开关特性的影响", 《现代显示》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111129037A (en) * | 2019-12-25 | 2020-05-08 | Tcl华星光电技术有限公司 | TFT array substrate and manufacturing method thereof |
| US11374026B2 (en) | 2019-12-25 | 2022-06-28 | Tcl China Star Optoelectronics Technology Co., Ltd. | TFT array substrate and manufacturing method thereof |
| WO2021128462A1 (en) * | 2019-12-26 | 2021-07-01 | Tcl华星光电技术有限公司 | Tft array substrate and manufacturing method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Lee et al. | 42.2: World's largest (15‐inch) XGA AMLCD panel using IGZO oxide TFT | |
| CN105226015B (en) | A kind of tft array substrate and preparation method thereof | |
| CN106531692A (en) | Array substrate and preparation method therefor, and display apparatus | |
| TWI538218B (en) | Thin film transistor | |
| CN109065632A (en) | Thin film transistor (TFT) and its manufacturing method, display device | |
| US5576229A (en) | Method of fabricating a thin-film transistor and liquid-crystal display apparatus | |
| CN106783871A (en) | A kind of array base palte, display panel and preparation method | |
| KR101498136B1 (en) | Thin Film Transistor having polysilicon active layer, method of manufacturing thereof and array substrate | |
| CN103762244A (en) | Thin film transistor, manufacturing method of thin film transistor, thin film transistor array substrate and liquid crystal panel | |
| CN104362179A (en) | Thin-film transistor, manufacturing method of thin-film transistor, array substrate and display device | |
| US8067768B2 (en) | Thin-film transistor display panel including an oxide active layer and a nitrogen oxide passivation layer, and method of fabricating the same | |
| WO2020062426A1 (en) | Array substrate and preparation method therefor, and display device | |
| CN109103105A (en) | Thin film transistor (TFT) and preparation method thereof, display device | |
| CN102651399B (en) | Microcrystal amorphous silicon composite thin film transistor and manufacturing method thereof | |
| CN107507839A (en) | A kind of array base palte and its manufacture method | |
| CN110098126A (en) | The production method and thin film transistor (TFT) and display device of a kind of thin film transistor (TFT) | |
| US10629746B2 (en) | Array substrate and manufacturing method thereof | |
| CN109148597A (en) | Thin film transistor (TFT) and preparation method thereof | |
| CN106783734B (en) | A kind of low temperature polycrystalline silicon array substrate and preparation method thereof | |
| CN109119484A (en) | The manufacturing method of thin film transistor (TFT) and thin film transistor (TFT) | |
| JPH08242005A (en) | Amorphous silicon thin film transistor and its manufacture | |
| US11469329B2 (en) | Active switch, manufacturing method thereof and display device | |
| CN106449656A (en) | Array substrate and manufacturing method thereof and display panel and display device | |
| CN109873037A (en) | Thin film transistor (TFT) and preparation method thereof, display device | |
| CN109616417A (en) | Active switch and preparation method thereof, display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181228 |
|
| RJ01 | Rejection of invention patent application after publication |