CN109148375A - Film transistor device manufacturing method and film transistor device - Google Patents
Film transistor device manufacturing method and film transistor device Download PDFInfo
- Publication number
- CN109148375A CN109148375A CN201810945342.9A CN201810945342A CN109148375A CN 109148375 A CN109148375 A CN 109148375A CN 201810945342 A CN201810945342 A CN 201810945342A CN 109148375 A CN109148375 A CN 109148375A
- Authority
- CN
- China
- Prior art keywords
- electrode
- film transistor
- type semiconductor
- transistor device
- semiconductor active
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 99
- 238000002161 passivation Methods 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 73
- 239000010949 copper Substances 0.000 claims description 44
- 239000010936 titanium Substances 0.000 claims description 44
- 239000000377 silicon dioxide Substances 0.000 claims description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 26
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 26
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 26
- 239000004411 aluminium Substances 0.000 claims description 26
- 229910052782 aluminium Inorganic materials 0.000 claims description 26
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 26
- 229910052802 copper Inorganic materials 0.000 claims description 26
- 229910052750 molybdenum Inorganic materials 0.000 claims description 26
- 239000011733 molybdenum Substances 0.000 claims description 26
- 229910052719 titanium Inorganic materials 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 239000000203 mixture Substances 0.000 claims description 18
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 16
- 229910052738 indium Inorganic materials 0.000 claims description 16
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 16
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052733 gallium Inorganic materials 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 8
- 229910052725 zinc Inorganic materials 0.000 claims description 8
- 239000011701 zinc Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- QELJHCBNGDEXLD-UHFFFAOYSA-N nickel zinc Chemical compound [Ni].[Zn] QELJHCBNGDEXLD-UHFFFAOYSA-N 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims 3
- 238000007254 oxidation reaction Methods 0.000 claims 3
- 238000009413 insulation Methods 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- GRPQBOKWXNIQMF-UHFFFAOYSA-N indium(3+) oxygen(2-) tin(4+) Chemical group [Sn+4].[O-2].[In+3] GRPQBOKWXNIQMF-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000005669 field effect Effects 0.000 abstract description 9
- 239000010408 film Substances 0.000 description 36
- 239000012212 insulator Substances 0.000 description 17
- 229910004205 SiNX Inorganic materials 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000005240 physical vapour deposition Methods 0.000 description 12
- 239000010409 thin film Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 230000000295 complement effect Effects 0.000 description 5
- 239000011265 semifinished product Substances 0.000 description 5
- 229910003978 SiClx Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- -1 IGZO) Chemical compound 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 description 1
- KBEVZHAXWGOKCP-UHFFFAOYSA-N zinc oxygen(2-) tin(4+) Chemical compound [O--].[O--].[O--].[Zn++].[Sn+4] KBEVZHAXWGOKCP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Abstract
The present invention discloses a kind of film transistor device manufacturing method comprising: once electrode setting steps, one first source drain setting steps, a passivation layer setting steps, a top electrode setting steps, one second source drain setting steps and a transparent electrode setting steps.Through the above method manufacture film transistor device using N-type Metal-Insulator-Semi-Conductor as driving element, p-type Metal-Insulator-Semi-Conductor be used as compensating element, with increase film transistor device output electric current with raising film transistor device field-effect mobility.
Description
Technical field
The invention relates to a kind of thin film transistor (TFT) (Thin Film Transistor, TFT) device making methods, especially
It is about a kind of film transistor device manufacturing method and film transistor device, with N-type Metal-Insulator-Semi-Conductor (N-
Metal Insulator Semiconductor, N-MIS) it is used as driving element, p-type Metal-Insulator-Semi-Conductor (P-Metal
Insulator Semiconductor, P-MIS) it is used as compensating element, it can be to the electric property of entire film transistor device
It is adjusted, to increase the output electric current of film transistor device and improve the field-effect mobility of film transistor device.
Background technique
Usual N-type semiconductor material has good field-effect mobility (Field Effect Mobility), and extensive
Applied to thin film transistor (TFT) (the Thin Film in liquid crystal display panel (Liquid Crystal Display, LCD)
Transistor, TFT) device production.
Relative to N-type semiconductor material, P-type material has lower field-effect mobility, usually will not be individually using work
For the active layer material of TFT device, however complementary type TFT (Complementary can be formed together with N-type semiconductor material
TFT) structure adjusts the electric property of TFT using its complementary conductive mechanism.
Currently, metal oxide semiconductor material, as indium gallium zinc (Indium Gallium Zinc Oxide,
IGZO), indium gallium zinc-tin (Indium Gallium Zinc Oxide Tin, IGZTO), indium gallium (Indium
Gallium Oxide, IGO) etc., because preparation temperature is low, there is biggish electron mobility and excellent uniformity and surface
The characteristics such as flatness, the TFT device for being widely used in LCD and active matrix (Active Matrix LCD, AMLCD) etc. are answered
In.
However, above-mentioned material and architectural characteristic can be integrated there is no any known technology at present and produced ideal
TFT device.
Summary of the invention
The present invention provides a kind of film transistor device manufacturing method and film transistor device, with N-type metal-insulator
Semiconductor (N-Metal Insulator Semiconductor, N-MIS) is used as driving element, p-type Metal-Insulator-Semi-Conductor
(P-Metal Insulator Semiconductor, P-MIS) is used as compensating element, can be to entire film transistor device
Electric property be adjusted, with increase film transistor device output electric current and improve film transistor device field-effect
Mobility solves the problems, such as that the field-effect mobility of existing film transistor device is bad whereby.
The main purpose of the present invention is to provide a kind of film transistor device manufacturing methods comprising:
Electrode setting steps once, including be arranged electrode on a glass substrate, and formed one covering it is described under
The first grid insulating layer of electrode is on the glass substrate；
One first source drain setting steps, including one N-type semiconductor active layer of setting is in the first grid insulating layer
On, and one first source electrode and one first drain electrode are set on the first grid insulating layer, wherein first source electrode and described
First drain electrode connects the N-type semiconductor active layer so that a N-type Metal-Insulator-Semi-Conductor is collectively formed；
One passivation layer setting steps, including one first passivation layer of setting is in the N-type semiconductor active layer, first source
On pole and first drain electrode；
One top electrode setting steps, including a top electrode is set on first passivation layer, and be arranged described in a covering
The second grid insulating layer of top electrode is on first passivation layer；
One second source drain setting steps, including through setting at least one first via hole in first passivation layer and
On the second grid insulating layer, a P-type semiconductor active layer is set on the second grid insulating layer, and be arranged one the
Two source electrodes and one second drain electrode are on the second grid insulating layer, wherein second source electrode and the second drain electrode connection institute
P-type semiconductor active layer is stated so that a p-type Metal-Insulator-Semi-Conductor is collectively formed, and second drain electrode and first drain electrode are logical
At least one first via hole is crossed to be connected；And
One transparent electrode setting steps, including one second passivation layer of setting is in the P-type semiconductor active layer, described second
On source electrode and second drain electrode, through setting at least one second via hole on second passivation layer, and it is transparent to be arranged one
Electrode is connected wherein the transparent electrode passes through at least one second via hole with the second drain electrode on second passivation layer
It connects.
In an embodiment of the present invention, the lower electrode is aluminium (Al), molybdenum (Mo), copper (Cu) or titanium (Ti), passes through physics
Vapour deposition process and formed, and the lower thickness of electrode isThe first grid insulating layer is silica
(SiOx) or the mixture of silicon nitride (SiNx) and silica (SiOx), pass through plasma auxiliary chemical vapor deposition method
And it is formed, and the first grid thickness of insulating layer is
In an embodiment of the present invention, first source electrode and it is described first drain electrode be aluminium (Al), molybdenum (Mo), copper (Cu) or
Titanium (Ti), and first source electrode and it is described first drain electrode with a thickness of
In an embodiment of the present invention, the N-type semiconductor active layer is indium gallium zinc (Indium Gallium
Zinc Oxide, IGZO), it is formed by physical vaporous deposition, and the N-type semiconductor active layer is with a thickness of being less than
In an embodiment of the present invention, first passivation layer is silica (SiOx) or silicon nitride (SiNx) and oxygen
The mixture of SiClx (SiOx), is formed by plasma auxiliary chemical vapor deposition method, and the thickness of first passivation layer
It is about
In an embodiment of the present invention, described to power on extremely aluminium (Al), molybdenum (Mo), copper (Cu) or titanium (Ti), pass through physics
Vapour deposition process and formed, and the top electrode with a thickness ofThe second grid insulating layer is silica
(SiOx) or the mixture of silicon nitride (SiNx) and silica (SiOx), pass through plasma auxiliary chemical vapor deposition method
And it is formed, and the second grid thickness of insulating layer is
In an embodiment of the present invention, the P-type semiconductor active layer is zinc oxide (ZnO) or nickel zinc (NiO), is passed through
Physical vaporous deposition and formed, and the P-type semiconductor active layer thickness is less than
In an embodiment of the present invention, second source electrode and it is described second drain electrode be aluminium (Al), molybdenum (Mo), copper (Cu) or
Titanium (Ti), and second source electrode and it is described second drain electrode with a thickness of
In an embodiment of the present invention, the transparent electrode is tin indium oxide (Indium Tin Oxide, ITO).
Another object of the present invention is to provide a kind of film transistor devices comprising:
One glass substrate；
Electrode once is arranged on the glass substrate；
One first grid insulating layer is arranged on the glass substrate, and covers the lower electrode；
One N-type semiconductor active layer is arranged on the first grid insulating layer；
One first source electrode and one first drain electrode, be arranged on the first grid insulating layer, wherein first source electrode and
First drain electrode connects the N-type semiconductor active layer so that a N-type Metal-Insulator-Semi-Conductor is collectively formed；
One first passivation layer, setting is in the N-type semiconductor active layer, first source electrode and first drain electrode；
One top electrode is arranged on first passivation layer；
One second grid insulating layer is arranged on first passivation layer, and covers the top electrode；
At least one first via hole, through setting on first passivation layer and the second grid insulating layer；
One P-type semiconductor active layer is arranged on the second grid insulating layer；
One second source electrode and one second drain electrode, be arranged on the second grid insulating layer, wherein second source electrode and
Second drain electrode connects the P-type semiconductor active layer so that a p-type Metal-Insulator-Semi-Conductor, and second leakage is collectively formed
Pole is connected with first drain electrode by least one first via hole；
One second passivation layer, setting is in the P-type semiconductor active layer, second source electrode and second drain electrode；
At least one second via hole, through setting on second passivation layer；And
One transparent electrode is arranged on second passivation layer, wherein the transparent electrode passes through described at least one second
Via hole is connected with the second drain electrode.
In an embodiment of the present invention, the lower electrode is aluminium (Al), molybdenum (Mo), copper (Cu) or titanium (Ti), and it is described under
Thickness of electrode isThe first grid insulating layer is silica (SiOx) or silicon nitride (SiNx) and oxygen
The mixture of SiClx (SiOx), and the first grid thickness of insulating layer is
In an embodiment of the present invention, the N-type semiconductor active layer is indium gallium zinc (Indium Gallium
Zinc Oxide, IGZO), and the N-type semiconductor active layer is with a thickness of being less than
In an embodiment of the present invention, first source electrode and it is described first drain electrode be aluminium (Al), molybdenum (Mo), copper (Cu) or
Titanium (Ti), and first source electrode and it is described first drain electrode with a thickness of
In an embodiment of the present invention, first passivation layer is silica (SiOx) or silicon nitride (SiNx) and oxygen
The mixture of SiClx (SiOx), and the thickness of first passivation layer is about
In an embodiment of the present invention, described to power on extremely aluminium (Al), molybdenum (Mo), copper (Cu) or titanium (Ti), pass through physics
Vapour deposition process and formed, and the top electrode with a thickness ofThe second grid insulating layer is silica
(SiOx) or the mixture of silicon nitride (SiNx) and silica (SiOx), and the second grid thickness of insulating layer is
In an embodiment of the present invention, the P-type semiconductor active layer is zinc oxide (ZnO) or nickel zinc (NiO), and institute
P-type semiconductor active layer thickness is stated to be less than
In an embodiment of the present invention, second source electrode and it is described second drain electrode be aluminium (Al), molybdenum (Mo), copper (Cu) or
Titanium (Ti), and second source electrode and it is described second drain electrode with a thickness of
In an embodiment of the present invention, the transparent electrode is tin indium oxide (Indium Tin Oxide, ITO).
Compared with prior art, film transistor device manufacturing method of the invention and film transistor device have
Following advantages: bottom of the present invention uses N-type semiconductor active layer to make N-type Metal-Insulator-Semi-Conductor (N-Metal
Insulator Semiconductor, N-MIS), and top uses P-type semiconductor active layer partly to lead to make p-type metal-insulator
Body (P-Metal Insulator Semiconductor, P-MIS), forms complementary film transistor device whereby, described
Film transistor device can increase the output electric current of film transistor device and improve field-effect mobility.
For above content of the invention can be clearer and more comprehensible, preferred embodiment is cited below particularly, Bing cooperates institute's accompanying drawings, makees
Detailed description are as follows:
Detailed description of the invention
Fig. 1 is thin film transistor (TFT) device corresponding to the lower electrode setting steps of film transistor device manufacturing method of the present invention
Part semi-finished product side sectional view.
Fig. 2 is the crystalline substance of film corresponding to the first source drain setting steps of film transistor device manufacturing method of the present invention
Body tube device semi-finished product side sectional view.
Fig. 3 is thin film transistor (TFT) device corresponding to the passivation layer setting steps of film transistor device manufacturing method of the present invention
Part semi-finished product side sectional view.
Fig. 4 is thin film transistor (TFT) device corresponding to the top electrode setting steps of film transistor device manufacturing method of the present invention
Part semi-finished product side sectional view.
Fig. 5 is the crystalline substance of film corresponding to the second source drain setting steps of film transistor device manufacturing method of the present invention
Body tube device semi-finished product side sectional view.
Fig. 6 is thin film transistor (TFT) corresponding to the transparent electrode setting steps of film transistor device manufacturing method of the present invention
Device finished product side sectional view.
Fig. 7 is the step flow chart of film transistor device manufacturing method of the present invention.
Specific embodiment
Please refer to Fig. 7, thin film transistor (TFT) (Thin Film Transistor Film, TFT) device manufacturing method of the present invention
Method comprising: once electrode setting steps S01, one first source drain setting steps S02, a passivation layer setting steps S03,
One top electrode setting steps S04, one second source drain setting steps S05 and a transparent electrode setting steps S06.
Please refer to Fig. 1, the lower electrode setting steps S01 include be arranged electrode B G on a glass substrate GL, and
And the first grid insulating layer GI1 of a covering lower electrode B G is formed on the glass substrate GL.
Preferably, the lower electrode B G is aluminium (Al), molybdenum (Mo), copper (Cu) or titanium (Ti), passes through physical vapour deposition (PVD)
(Physical Vapor Deposition, PVD) method and formed, and the lower electrode B G with a thickness ofIt is described
First grid insulating layer GI1 is the mixture of silica (SiOx) or silicon nitride (SiNx) and silica (SiOx), is passed through
Gas ions assistant chemical vapor deposition (Plasma-enhanced Chemical Vapor Deposition, PECVD) method and shape
At, and the first grid insulating layer GI1 with a thickness of
Referring to figure 2., the first source drain setting steps S02 includes one N-type semiconductor active layer N of setting described
On first grid insulating layer GI1, and one first source S 1 and one first drain D 1 are set in the first grid insulating layer GI1
On, wherein first source S 1 and first drain D 1 connect the N-type semiconductor active layer N so that a N-type is collectively formed
Metal-Insulator-Semi-Conductor (N-Metal Insulator Semiconductor, N-MIS).
Preferably, the N-type semiconductor active layer N be indium gallium zinc (Indium Gallium Zinc Oxide,
IGZO), formed by physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) method, and the N-type semiconductor
Active layer N is with a thickness of being less than
In an embodiment of the present invention, first source S 1 and first drain D 1 are aluminium (Al), molybdenum (Mo), copper
(Cu) or titanium (Ti), and first source S 1 and first drain D 1 with a thickness ofPreferably, described
One source drain setting steps S02 further comprises etching the aluminium (Al), molybdenum (Mo), copper by yellow light technique and etching technics
(Cu) or titanium (Ti) and form first source S 1 and first drain D 1.
Referring to figure 3., the passivation layer setting steps S03 includes one first passivation layer PV1 of setting in the N-type semiconductor
In active layer N, first source S 1 and first drain D 1.Preferably, the first passivation layer PV1 is silica
(SiOx) or the mixture of silicon nitride (SiNx) and silica (SiOx), pass through plasma auxiliary chemical vapor deposition method
And it is formed, and the thickness of the first passivation layer PV1 is about
Referring to figure 4., the top electrode setting steps S04 includes one top electrode TG of setting in the first passivation layer PV1
On, and the second grid insulating layer GI2 of a covering top electrode TG is set on the first passivation layer PV1.
Preferably, the top electrode TG is aluminium (Al), molybdenum (Mo), copper (Cu) or titanium (Ti), passes through physical vaporous deposition
And formed, and the top electrode TG with a thickness ofThe second grid insulating layer GI2 be silica (SiOx),
Or the mixture of silicon nitride (SiNx) and silica (SiOx), it is formed by plasma auxiliary chemical vapor deposition method,
And the second grid insulating layer GI2 with a thickness of
Referring to figure 5., the second source drain setting steps S05 includes through setting at least one first via hole V1 in institute
It states on the first passivation layer PV1 and second grid insulating layer GI2, a P-type semiconductor active layer P is set in the second gate
On the insulating layer GI2 of pole, and one second source S 2 and one second drain D 2 are set on the second grid insulating layer GI2,
Described in the second source S 2 and second drain D 2 to connect the P-type semiconductor active layer P exhausted a p-type metal is collectively formed
Edge semiconductor (P-Metal Insulator Semiconductor, P-MIS), and second drain D 2 and first leakage
Pole D1 is connected by at least one first via hole V1.
Preferably, the P-type semiconductor active layer P is zinc oxide (ZnO) or nickel zinc (NiO), is sunk by physical vapor
Area method and formed, and the P-type semiconductor active layer P thickness is less thanPreferably, second source S 2 and described
Second drain D 2 is aluminium (Al), molybdenum (Mo), copper (Cu) or titanium (Ti), and second source S 2 and 2 thickness of the second drain D
For
Preferably, the second source drain setting steps S05 further comprises being lost by yellow light technique and etching technics
It carves the aluminium (Al), molybdenum (Mo), copper (Cu) or titanium (Ti) and forms second source S 2 and second drain D 2.
Fig. 6 is please referred to, the transparent electrode setting steps S06 includes that one second passivation layer PV2 of setting is partly led in the p-type
In body active layer P, second source S 2 and second drain D 2, through setting at least one second via hole V2 described second
On passivation layer PV2, and a transparent electrode IT is set on the second passivation layer PV2, wherein the transparent electrode IT passes through
At least one second via hole V2 is connected with the second drain D 2.Preferably, the second passivation layer PV2 is silica
(SiOx) or the mixture of silicon nitride (SiNx) and silica (SiOx), pass through plasma auxiliary chemical vapor deposition method
And it is formed, and the thickness of the second passivation layer PV2 is about
Please be again referring to Fig. 6, film transistor device of the invention includes: a glass substrate GL, once electrode B G, one first
Gate insulating layer GI1, a N-type semiconductor active layer N, one first source S 1 and one first drain D 1, one first passivation layer PV1,
One top electrode TG, a second grid insulating layer GI2, at least one first via hole V1, a P-type semiconductor active layer P, one second source electrode
S2 and one second drain D 2, one second passivation layer PV2, at least one second via hole V2 and a transparent electrode IT.
The lower electrode B G is arranged on the glass substrate GL.The lower electrode B G is aluminium (Al), molybdenum (Mo), copper (Cu)
Or titanium (Ti), and the lower electrode B G with a thickness of
The first grid insulating layer GI1 is arranged on the glass substrate GL, and covers the lower electrode B G.Described
One gate insulating layer GI1 is the mixture of silica (SiOx) or silicon nitride (SiNx) and silica (SiOx), and described
One gate insulating layer GI1 with a thickness of
The N-type semiconductor active layer N is arranged on the first grid insulating layer GI1.The N-type semiconductor active layer
N is indium gallium zinc (Indium Gallium Zinc Oxide, IGZO), and the N-type semiconductor active layer N is with a thickness of small
In
First source S 1 and first drain D 1 are arranged on the first grid insulating layer GI1, wherein described
First source S 1 and first drain D 1 connect the N-type semiconductor active layer N and are partly led so that a N-type metal-insulator is collectively formed
Body (N-Metal Insulator Semiconductor, N-MIS).First source S 1 and first drain D 1 are aluminium
(Al), molybdenum (Mo), copper (Cu) or titanium (Ti), and first source S 1 and first drain D 1 with a thickness of
The first passivation layer PV1 is arranged in the N-type semiconductor active layer N, first source S 1 and described first
In drain D 1.The first passivation layer PV1 is the mixing of silica (SiOx) or silicon nitride (SiNx) and silica (SiOx)
Object, and the thickness of the first passivation layer PV1 is about
The top electrode TG is arranged on the first passivation layer PV1.The top electrode TG is aluminium (Al), molybdenum (Mo), copper
(Cu) or titanium (Ti), formed by physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) method, and it is described on
Electrode TG with a thickness of
The second grid insulating layer GI2 is arranged on the first passivation layer PV1, and covers the top electrode TG.Institute
State the mixture that second grid insulating layer GI2 is silica (SiOx) or silicon nitride (SiNx) and silica (SiOx), and institute
State second grid insulating layer GI2 with a thickness of
At least one first via hole V1 is through setting in the first passivation layer PV1 and the second grid insulating layer
On GI2.
The P-type semiconductor active layer P is arranged on the second grid insulating layer GI2.The P-type semiconductor active layer
P is zinc oxide (ZnO) or nickel zinc (NiO), and the P-type semiconductor active layer P thickness is less than
Second source S 2 and second drain D 2 are arranged on the second grid insulating layer GI2, wherein described
Second source S 2 and second drain D 2 connect the P-type semiconductor active layer P and are partly led so that a p-type metal-insulator is collectively formed
Body (P-Metal Insulator Semiconductor, P-MIS), and second drain D 2 and first drain D 1 are logical
At least one first via hole V1 is crossed to be connected.Second source S 2 and second drain D 2 are aluminium (Al), molybdenum (Mo), copper
(Cu) or titanium (Ti), and second source S 2 and second drain D 2 with a thickness of
The second passivation layer PV2 is arranged in the P-type semiconductor active layer P, second source S 2 and described second
In drain D 2.The second passivation layer PV2 is the mixing of silica (SiOx) or silicon nitride (SiNx) and silica (SiOx)
Object, and the thickness of the second passivation layer PV2 is about
At least one second via hole V2 is through setting on the second passivation layer PV2.
The transparent electrode IT is arranged on the second passivation layer PV2, wherein the transparent electrode IT by it is described extremely
Few one second via hole V2 is connected with the second drain D 2.The transparent electrode IT be tin indium oxide (Indium Tin Oxide,
ITO)。
Compared with prior art, film transistor device manufacturing method of the invention and film transistor device have
Following advantages: bottom of the present invention uses N-type semiconductor active layer N to make N-type Metal-Insulator-Semi-Conductor (N-Metal
Insulator Semiconductor, N-MIS), and top uses P-type semiconductor active layer P to make p-type metal-insulator half
Conductor (P-Metal Insulator Semiconductor, P-MIS), forms complementary film transistor device, institute whereby
The output electric current of film transistor device can be increased and improve field-effect mobility by stating film transistor device.
Claims (18)
1. a kind of film transistor device manufacturing method characterized by comprising
Electrode setting steps once, including electrode once is set and and forms a covering lower electrode on a glass substrate
First grid insulating layer on the glass substrate；
One first source drain setting steps, including a N-type semiconductor active layer is set on the first grid insulating layer, and
One first source electrode and one first drain electrode are set on the first grid insulating layer, wherein first source electrode and first leakage
Pole connects the N-type semiconductor active layer so that a N-type Metal-Insulator-Semi-Conductor is collectively formed；
One passivation layer setting steps, including setting one first passivation layer the N-type semiconductor active layer, first source electrode and
In first drain electrode；
One top electrode setting steps, including one top electrode of setting power on first passivation layer, and described in one covering of setting
The second grid insulating layer of pole is on first passivation layer；
One second source drain setting steps, including through setting at least one first via hole in first passivation layer and described
On second grid insulating layer, a P-type semiconductor active layer is set on the second grid insulating layer, and one second source is set
Pole and one second drain electrode are on the second grid insulating layer, wherein second source electrode and second drain electrode connect the P
Type semiconductor active layer is to be collectively formed a p-type Metal-Insulator-Semi-Conductor, and second drain electrode passes through with first drain electrode
At least one first via hole is connected；And
One transparent electrode setting steps, including one second passivation layer of setting is in the P-type semiconductor active layer, second source electrode
And in second drain electrode, through setting at least one second via hole on second passivation layer, and a transparent electrode is set
On second passivation layer, it is connected wherein the transparent electrode passes through at least one second via hole with the second drain electrode.
2. film transistor device manufacturing method as described in claim 1, it is characterised in that: the lower electrode is aluminium, molybdenum, copper
Or titanium, it is formed by physical vaporous deposition, and the lower thickness of electrode isThe first grid insulation
Layer is the mixture of silica (SiOx) or silicon nitride and silica, passes through plasma auxiliary chemical vapor deposition method
It is formed, and the first grid thickness of insulating layer is
3. film transistor device manufacturing method as described in claim 1, it is characterised in that: first source electrode and described
One drain electrode be aluminium, molybdenum, copper or titanium, and first source electrode and it is described first drain electrode with a thickness of
4. film transistor device manufacturing method as described in claim 1, it is characterised in that: the N-type semiconductor active layer
It for indium gallium zinc, is formed by physical vaporous deposition, and the N-type semiconductor active layer is with a thickness of being less than
5. film transistor device manufacturing method as described in claim 1, it is characterised in that: first passivation layer is oxidation
The mixture of silicon or silicon nitride and silica is formed by plasma auxiliary chemical vapor deposition method, and described first
The thickness of passivation layer is about
6. film transistor device manufacturing method as described in claim 1, it is characterised in that: described to power on extremely aluminium, molybdenum, copper
Or titanium, formed by physical vaporous deposition, and the top electrode with a thickness ofThe second grid insulation
Layer is the mixture of silica or silicon nitride and silica, is formed by plasma auxiliary chemical vapor deposition method, and
The second grid thickness of insulating layer is
7. film transistor device manufacturing method as described in claim 1, it is characterised in that: the P-type semiconductor active layer
It for zinc oxide or nickel zinc, is formed by physical vaporous deposition, and the P-type semiconductor active layer thickness is less than
8. film transistor device manufacturing method as described in claim 1, it is characterised in that: second source electrode and described
Two drain electrode be aluminium, molybdenum, copper or titanium, and second source electrode and it is described second drain electrode with a thickness of
9. film transistor device manufacturing method as described in claim 1, it is characterised in that: the transparent electrode is indium oxide
Tin.
10. a kind of film transistor device, it is characterised in that: include:
One glass substrate；
Electrode once is arranged on the glass substrate；
One first grid insulating layer is arranged on the glass substrate, and covers the lower electrode；
One N-type semiconductor active layer is arranged on the first grid insulating layer；
One first source electrode and one first drain electrode, are arranged on the first grid insulating layer, wherein first source electrode and described
First drain electrode connects the N-type semiconductor active layer so that a N-type Metal-Insulator-Semi-Conductor is collectively formed；
One first passivation layer, setting is in the N-type semiconductor active layer, first source electrode and first drain electrode；
One top electrode is arranged on first passivation layer；
One second grid insulating layer is arranged on first passivation layer, and covers the top electrode；
At least one first via hole, through setting on first passivation layer and the second grid insulating layer；
One P-type semiconductor active layer is arranged on the second grid insulating layer；
One second source electrode and one second drain electrode, are arranged on the second grid insulating layer, wherein second source electrode and described
Second drain electrode connects the P-type semiconductor active layer to be collectively formed a p-type Metal-Insulator-Semi-Conductor, and second drain electrode with
First drain electrode is connected by least one first via hole；
One second passivation layer, setting is in the P-type semiconductor active layer, second source electrode and second drain electrode；
At least one second via hole, through setting on second passivation layer；And
One transparent electrode is arranged on second passivation layer, wherein the transparent electrode passes through at least one second via hole
It is connected with the second drain electrode.
11. film transistor device as claimed in claim 10, it is characterised in that: the lower electrode be aluminium, molybdenum, copper or titanium,
And the lower thickness of electrode isThe first grid insulating layer is silica or silicon nitride and silica
Mixture, and the first grid thickness of insulating layer is
12. film transistor device as claimed in claim 10, it is characterised in that: the N-type semiconductor active layer is oxidation
Indium gallium zinc, and the N-type semiconductor active layer is with a thickness of being less than
13. film transistor device as claimed in claim 10, it is characterised in that: first source electrode and first drain electrode
For aluminium, molybdenum, copper or titanium, and first source electrode and first drain electrode with a thickness of
14. film transistor device as claimed in claim 10, it is characterised in that: first passivation layer be silica or
It is the mixture of silicon nitride Yu silica, and the thickness of first passivation layer is about
15. film transistor device as claimed in claim 10, it is characterised in that: it is described to power on extremely aluminium, molybdenum, copper or titanium,
And the top electrode with a thickness ofThe second grid insulating layer is silica or silicon nitride and silica
Mixture, and the second grid thickness of insulating layer is
16. film transistor device as claimed in claim 10, it is characterised in that: the P-type semiconductor active layer is oxidation
Zinc or nickel zinc, and the P-type semiconductor active layer thickness is less than
17. film transistor device as claimed in claim 10, it is characterised in that: second source electrode and second drain electrode
For aluminium, molybdenum, copper or titanium, and second source electrode and second drain electrode with a thickness of
18. film transistor device as claimed in claim 10, it is characterised in that: the transparent electrode is tin indium oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810945342.9A CN109148375A (en) | 2018-08-20 | 2018-08-20 | Film transistor device manufacturing method and film transistor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810945342.9A CN109148375A (en) | 2018-08-20 | 2018-08-20 | Film transistor device manufacturing method and film transistor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109148375A true CN109148375A (en) | 2019-01-04 |
Family
ID=64790059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810945342.9A Pending CN109148375A (en) | 2018-08-20 | 2018-08-20 | Film transistor device manufacturing method and film transistor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109148375A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110438472A (en) * | 2019-06-27 | 2019-11-12 | 惠科股份有限公司 | Production method, thin film transistor (TFT) and the display panel of indium gallium zinc oxide film |
| CN112216706A (en) * | 2020-11-13 | 2021-01-12 | 武汉华星光电技术有限公司 | Driving backboard and light-emitting substrate |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937875A (en) * | 2010-08-17 | 2011-01-05 | 友达光电股份有限公司 | Complementary metal-oxide-semiconductor (CMOS) transistor and manufacturing method thereof |
| CN103178060A (en) * | 2011-12-23 | 2013-06-26 | 上海中科联和显示技术有限公司 | Field effect transistor complementary inverter and production method thereof |
| TW201338102A (en) * | 2012-03-14 | 2013-09-16 | Wintek Corp | Active device and active device array substrate |
| JP2014225491A (en) * | 2013-05-15 | 2014-12-04 | 猛英 白土 | Semiconductor device |
| CN105470310A (en) * | 2016-01-21 | 2016-04-06 | 京东方科技集团股份有限公司 | Thin-film transistor and fabrication method thereof, array substrate and display device |
| CN105742309A (en) * | 2016-02-29 | 2016-07-06 | 深圳市华星光电技术有限公司 | Complementary thin film transistor and fabrication method thereof |
| CN107210189A (en) * | 2015-01-22 | 2017-09-26 | 追踪有限公司 | P-type oxide semiconductor and thin film transistor (TFT) application based on tin |
| US20170323930A1 (en) * | 2016-05-03 | 2017-11-09 | Tsinghua University | Method for making three dimensional complementary metal oxide semiconductor carbon nanotube thin film transistor circui |
-
2018
- 2018-08-20 CN CN201810945342.9A patent/CN109148375A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937875A (en) * | 2010-08-17 | 2011-01-05 | 友达光电股份有限公司 | Complementary metal-oxide-semiconductor (CMOS) transistor and manufacturing method thereof |
| CN103178060A (en) * | 2011-12-23 | 2013-06-26 | 上海中科联和显示技术有限公司 | Field effect transistor complementary inverter and production method thereof |
| TW201338102A (en) * | 2012-03-14 | 2013-09-16 | Wintek Corp | Active device and active device array substrate |
| JP2014225491A (en) * | 2013-05-15 | 2014-12-04 | 猛英 白土 | Semiconductor device |
| CN107210189A (en) * | 2015-01-22 | 2017-09-26 | 追踪有限公司 | P-type oxide semiconductor and thin film transistor (TFT) application based on tin |
| CN105470310A (en) * | 2016-01-21 | 2016-04-06 | 京东方科技集团股份有限公司 | Thin-film transistor and fabrication method thereof, array substrate and display device |
| CN105742309A (en) * | 2016-02-29 | 2016-07-06 | 深圳市华星光电技术有限公司 | Complementary thin film transistor and fabrication method thereof |
| US20170323930A1 (en) * | 2016-05-03 | 2017-11-09 | Tsinghua University | Method for making three dimensional complementary metal oxide semiconductor carbon nanotube thin film transistor circui |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110438472A (en) * | 2019-06-27 | 2019-11-12 | 惠科股份有限公司 | Production method, thin film transistor (TFT) and the display panel of indium gallium zinc oxide film |
| CN110438472B (en) * | 2019-06-27 | 2021-08-31 | 惠科股份有限公司 | Manufacturing method of indium gallium zinc oxide thin film, thin film transistor and display panel |
| CN112216706A (en) * | 2020-11-13 | 2021-01-12 | 武汉华星光电技术有限公司 | Driving backboard and light-emitting substrate |
| CN112216706B (en) * | 2020-11-13 | 2022-07-29 | 武汉华星光电技术有限公司 | Driving backboard and light-emitting substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101681483B1 (en) | Thin film transistor array substrate and method of manufacturing the same | |
| CN106558593A (en) | The preparation method of array base palte, display floater, display device and array base palte | |
| CN106531692A (en) | Array substrate and preparation method therefor, and display apparatus | |
| CN104584200B (en) | Thin film transistor (TFT) and display device | |
| US9741752B1 (en) | Method for manufacturing TFT substrate | |
| WO2018010214A1 (en) | Method for manufacturing metal oxide thin film transistor array substrate | |
| WO2016176881A1 (en) | Manufacturing method for dual-gate tft substrate, and structure of dual-gate tft substrate | |
| KR20100027377A (en) | Thin film transistor array substrate and method of fabricating the same | |
| WO2016165187A1 (en) | Manufacturing method for dual-gate oxide semiconductor tft substrate, and structure of dual-gate oxide semiconductor tft substrate | |
| CN105514120B (en) | A kind of double grid tft array substrate and its manufacturing method and display device | |
| CN105161503A (en) | Amorphous silicon semiconductor thin film transistor (TFT) backboard structure | |
| US10121883B2 (en) | Manufacturing method of top gate thin-film transistor | |
| US8748222B2 (en) | Method for forming oxide thin film transistor | |
| CN103762244A (en) | Thin film transistor, manufacturing method of thin film transistor, thin film transistor array substrate and liquid crystal panel | |
| CN106356306A (en) | Top gate type thin film transistor and production method thereof | |
| WO2016033836A1 (en) | Manufacturing method and structure of oxide semiconductor tft substrate | |
| US10170506B2 (en) | LTPS array substrate and method for producing the same | |
| CN109148375A (en) | Film transistor device manufacturing method and film transistor device | |
| CN107464851A (en) | A kind of gallium nitride film transistor and its manufacture method | |
| US10629746B2 (en) | Array substrate and manufacturing method thereof | |
| JP7030285B2 (en) | Semiconductor device, display device, manufacturing method of semiconductor device and manufacturing method of display device | |
| CN105702622B (en) | The production method and low temperature polycrystalline silicon TFT substrate of low temperature polycrystalline silicon TFT substrate | |
| CN108598096B (en) | TFT array substrate and manufacturing method thereof | |
| TWI518430B (en) | Display panel and display device using the same | |
| US10224406B2 (en) | Array substrate including vertical TFT, and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190104 |
|
| RJ01 | Rejection of invention patent application after publication |