CN108598096B - TFT array substrate and manufacturing method thereof - Google Patents
TFT array substrate and manufacturing method thereof Download PDFInfo
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- CN108598096B CN108598096B CN201810622177.3A CN201810622177A CN108598096B CN 108598096 B CN108598096 B CN 108598096B CN 201810622177 A CN201810622177 A CN 201810622177A CN 108598096 B CN108598096 B CN 108598096B
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The invention provides a TFT array substrate and a manufacturing method thereof. The source electrode, the drain electrode, the first grid electrode and the second grid electrode of the TFT array substrate are all formed on the insulating layer, namely are positioned on the same plane, so that the source electrode, the drain electrode, the first grid electrode and the second grid electrode can be simultaneously manufactured by adopting the same photomask, the production cost and the production time are saved, equivalent capacitors can be formed between the first grid electrode and the source electrode and between the second grid electrode and the drain electrode, the threshold voltage and the subthreshold swing amplitude of a TFT device can be effectively and properly regulated and controlled by regulating the distance between the first grid electrode and the source electrode and the distance between the second grid electrode and the drain electrode, and the electrical performance of the TFT device is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a TFT array substrate and a manufacturing method thereof.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have advantages of high image quality, power saving, thin body, and wide application range, and thus are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices.
Most of the existing liquid crystal display devices in the market are backlight liquid crystal displays (lcds), which include a liquid crystal display panel and a backlight module (backlight module). The liquid crystal display panel has the working principle that liquid crystal molecules are placed in two parallel glass substrates, a plurality of vertical and horizontal fine electric wires are arranged between the two glass substrates, the liquid crystal molecules are controlled to change directions by electrifying or not, and light rays of the backlight module are transmitted out to generate pictures.
Compared with the traditional TFT screen, an Active Matrix Organic Light Emitting Diode (AMOLED) AMOLED screen is more and more popular among users due to its advantages of fast response speed, self-luminescence, excellent display effect and lower power consumption. Active Matrix Liquid Crystal Display (AMLCD) is widely used in military, telecommunication, electric power, petroleum, chemical industry, metallurgy, machinery, numerical control, medical, traffic, instrumentation, aerospace, and various field control and monitoring fields due to its vibration resistance, electromagnetic interference resistance, stable image quality, and wide temperature range. However, the conventional single gate device structure has a limitation in application to large-area resolution such as AMOLED screens and AMLCDs due to its low mobility.
In order to meet the requirement of large area and high resolution, a double-gate device structure is generally adopted to improve the mobility, and compared with a single-gate device structure, the double-gate device structure has the advantages that a top gate and a bottom gate are not in the same plane, so that one photomask is additionally used in production and manufacturing, the production cost is high, and the production time is long.
Disclosure of Invention
The invention aims to provide a TFT array substrate, which can be used for manufacturing a source electrode, a drain electrode, a first grid electrode and a second grid electrode simultaneously by adopting the same photomask so as to save the production cost and the production time and improve the electrical performance of a TFT device.
Another objective of the present invention is to provide a method for manufacturing a TFT array substrate, which can simultaneously manufacture a source electrode, a drain electrode, a first gate electrode and a second gate electrode by using the same photomask, so as to save the production cost and the production time and improve the electrical performance of the TFT device.
In order to achieve the above object, the present invention first provides a TFT array substrate, which includes a substrate, a conductive layer disposed on the substrate, an insulating layer disposed on the conductive layer, an active layer disposed on the insulating layer, a source electrode and a drain electrode disposed on the insulating layer and contacting with two ends of the active layer, and a first gate electrode and a second gate electrode disposed on the insulating layer and surrounding the source electrode and the drain electrode, respectively;
the first grid and the second grid are respectively contacted with the conductive layer through a first via hole and a second via hole which penetrate through the insulating layer;
the source electrode, the drain electrode, the first grid electrode and the second grid electrode are simultaneously manufactured by adopting the same photomask.
The TFT array substrate further comprises a protective layer covering the active layer, the insulating layer, the source electrode, the drain electrode, the first grid electrode and the second grid electrode, and a pixel electrode arranged on the protective layer; the pixel electrode is in contact with the drain electrode through a third through hole penetrating through the protective layer.
The conducting layer is made of one or more of molybdenum, copper and aluminum; the thickness of the conductive layer is
The insulating layer is made of one or a combination of two of silicon oxide and silicon nitride; the thickness of the insulating layer is
The active layer is made of IGZO; the thickness of the active layer is less than
The source electrode, the drain electrode, the first grid electrode and the second grid electrode are made of one or more of aluminum, copper, molybdenum and titanium; the thicknesses of the source electrode, the drain electrode, the first grid electrode and the second grid electrode are all
The protective layer is made of one or the combination of two of silicon oxide and silicon nitride; the thickness of the protective layer is
The pixel electrode is made of ITO.
The active layer comprises a channel region, and a source contact region and a drain contact region which are respectively positioned at two sides of the channel region; the source electrode is contacted with a source electrode contact region; the drain is in contact with a drain contact region.
The distance between the first grid and the source is smaller than the width of the channel region; the distance between the second grid and the drain is smaller than the width of the channel region.
The width of the channel region is 3-5 um.
The invention provides a manufacturing method of a TFT array substrate, which comprises the following steps:
step S1, providing a substrate, and sequentially forming a conductive layer and an insulating layer on the substrate by adopting a physical vapor deposition method;
step S2, depositing on the insulating layer by using a physical vapor deposition method to form an oxide semiconductor layer, and patterning the oxide semiconductor layer by using yellow light and etching processes to obtain an active layer on the insulating layer and a first via hole and a second via hole which penetrate through the insulating layer and are respectively located on two sides of the active layer;
step S3, depositing a metal layer on the insulating layer and the active layer, and patterning the metal layer through the same mask by using yellow light and etching processes to form a source electrode and a drain electrode on the insulating layer and in contact with two ends of the active layer, and a first gate electrode and a second gate electrode on the insulating layer and around the source electrode and the drain electrode, respectively; the first grid and the second grid are respectively contacted with the conductive layer through a first via hole and a second via hole;
step S4, forming a protection layer covering the active layer, the insulation layer, the source electrode, the drain electrode, the first gate electrode and the second gate electrode by using a chemical vapor deposition method;
step S5, digging a hole on the protective layer by adopting a photoetching process to form a third through hole which penetrates through the protective layer and exposes the drain electrode; depositing a transparent conducting layer on the protective layer, patterning the transparent conducting layer to form a pixel electrode, and annealing the pixel electrode; the pixel electrode is in contact with the drain electrode through a third via hole.
The conducting layer is made of one or more of molybdenum, copper and aluminum; the thickness of the conductive layer is
The insulating layer is made of one or a combination of two of silicon oxide and silicon nitride; the thickness of the insulating layer is
The active layer is made of IGZO; the thickness of the active layer is less than
The source electrode, the drain electrode, the first grid electrode and the second grid electrode are made of one or more of aluminum, copper, molybdenum and titanium; the thicknesses of the source electrode, the drain electrode, the first grid electrode and the second grid electrode are all
The protective layer is made of one or the combination of two of silicon oxide and silicon nitride; the thickness of the protective layer is
The pixel electrode is made of ITO;
the temperature of the annealing treatment is 200-450 ℃.
The active layer comprises a channel region, and a source contact region and a drain contact region which are respectively positioned at two sides of the channel region; the source electrode is contacted with a source electrode contact region; the drain electrode is in contact with the drain electrode contact region;
the distance between the first grid and the source is smaller than the width of the channel region; the distance between the second grid and the drain is smaller than the width of the channel region; the width of the channel region is 3-5 um.
The invention has the beneficial effects that: the source electrode, the drain electrode, the first grid electrode and the second grid electrode of the TFT array substrate are all formed on the insulating layer, namely are positioned on the same plane, so that the source electrode, the drain electrode, the first grid electrode and the second grid electrode can be simultaneously manufactured by adopting the same photomask to save the production cost and the production time, equivalent capacitors can be formed between the first grid electrode and the source electrode and between the second grid electrode and the drain electrode, and the threshold voltage and the subthreshold swing amplitude of a TFT device can be effectively and properly regulated and controlled by regulating the distance between the first grid electrode and the source electrode and the distance between the second grid electrode and the drain electrode, so that the electrical performance of the TFT device is improved. According to the manufacturing method of the TFT array substrate, the source electrode, the drain electrode, the first grid electrode and the second grid electrode can be simultaneously manufactured by adopting the same photomask so as to save production cost and production time, equivalent capacitors can be formed between the first grid electrode and the source electrode and between the second grid electrode and the drain electrode, and by adjusting the distance between the first grid electrode and the source electrode and the distance between the second grid electrode and the drain electrode, the threshold voltage and the sub-threshold swing amplitude of a TFT device can be effectively and properly regulated and controlled, and the electrical performance of the TFT device is improved.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic structural diagram of a TFT array substrate according to the present invention;
FIG. 2 is a flow chart of a method for fabricating a TFT array substrate according to the present invention;
FIG. 3 is a schematic diagram of step S1 of the method for fabricating a TFT array substrate according to the present invention;
FIG. 4 is a schematic diagram of a step S2 of a method for fabricating a TFT array substrate according to the present invention;
FIG. 5 is a schematic diagram of step S3 of the method for fabricating a TFT array substrate according to the present invention;
FIG. 6 is a schematic diagram of step S4 of the method for fabricating a TFT array substrate according to the present invention;
fig. 7 is a schematic diagram of step S5 of the method for manufacturing the TFT array substrate of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention provides a TFT array substrate, which includes a substrate 10, a conductive layer 20 disposed on the substrate 10, an insulating layer 30 disposed on the conductive layer 20, an active layer 40 disposed on the insulating layer 30, a source 51 and a drain 52 disposed on the insulating layer 30 and respectively contacting two ends of the active layer 40, and a first gate 53 and a second gate 54 disposed on the insulating layer 30 and respectively located at peripheries of the source 51 and the drain 52;
the first gate 53 and the second gate 54 are in contact with the conductive layer 20 through a first via hole 31 and a second via hole 32, respectively, which penetrate the insulating layer 30;
the source 51, the drain 52, the first gate 53 and the second gate 54 are simultaneously formed using the same mask.
It should be noted that the source 51, the drain 52, the first gate 53 and the second gate 54 of the present invention are all formed on the insulating layer 30, i.e. located on the same plane, so that the source 51, the drain 52, the first gate 53 and the second gate 54 can be simultaneously fabricated by using the same mask to save the production cost and the production time, and an equivalent capacitor is formed between the first gate 53 and the source 51 and between the second gate 54 and the drain 52, and by adjusting the distance between the first gate 53 and the source 51 and the distance between the second gate 54 and the drain 52, the threshold voltage and the sub-threshold swing of the TFT device can be effectively and properly adjusted and controlled, thereby improving the electrical performance of the TFT device.
Specifically, the TFT array substrate further includes a protective layer 60 covering the active layer 40, the insulating layer 30, the source electrode 51, the drain electrode 52, the first gate electrode 53 and the second gate electrode 54, and a pixel electrode 70 disposed on the protective layer 60; the pixel electrode 70 contacts the drain electrode 52 through a third via hole 61 penetrating the protective layer 60.
Specifically, the material of the conductive layer 20 is one or more of molybdenum, copper and aluminum, that is, the conductive layer 20 may be a single metal thin film layer or a composite metal thin film layer formed by combining multiple metal thin film layers; the thickness of the conductive layer 20 is
The insulating layer 30 is made of one or a combination of silicon oxide and silicon nitride, that is, the insulating layer 30 may be a single silicon oxide layer or a silicon nitride layer, or may be a composite layer formed by a silicon oxide layer and a silicon nitride layer; the thickness of the insulating layer 30 is
Specifically, the active layer 40 is made of Indium Gallium Zinc Oxide (IGZO); the thickness of the active layer 40 is less than
Specifically, the source 51, the drain 52, the first gate 53 and the second gate 54 are made of one or more of aluminum, copper, molybdenum and titanium; the source 51, the drain 52, the first gate 53 and the second gate 54 are all thick
Specifically, the material of the protective layer 60 is one or a combination of two of silicon oxide and silicon nitride, that is, the protective layer 60 may be a single silicon oxide layer or a silicon nitride layer, or may be a composite layer formed by a silicon oxide layer and a silicon nitride layer; the thickness of the protective layer 60 is
The pixel electrode 70 is made of Indium Tin Oxide (ITO).
Specifically, the active layer 40 includes a channel region 41 and a source contact region 42 and a drain contact region 43 respectively located at two sides of the channel region 41; the source electrode 51 is in contact with the source contact region 42; the drain electrode 52 is in contact with the drain contact region 43.
Preferably, the distance between the first gate 53 and the source 51 is smaller than the width of the channel region 41; the distance between the second gate 54 and the drain 52 is smaller than the width of the channel region 41, which is beneficial to improving the electrical performance of the TFT device.
Preferably, the width of the channel region 41 is 3-5 um.
Referring to fig. 2, based on the TFT array substrate, the present invention further provides a method for manufacturing the TFT array substrate, including the following steps:
step S1, please refer to fig. 3, providing a substrate 10, and sequentially forming a conductive layer 20 and an insulating layer 30 on the substrate 10 by using a physical vapor deposition method;
step S2, please refer to fig. 4, depositing an oxide semiconductor layer on the insulating layer 30 by using a physical vapor deposition method, and patterning the oxide semiconductor layer by using a yellow light and an etching process to obtain an active layer 40 on the insulating layer 30 and a first via hole 31 and a second via hole 32 penetrating the insulating layer 30 and respectively located at two sides of the active layer 40;
step S3, please refer to fig. 5, a metal layer is deposited on the insulating layer 30 and the active layer 40, and is patterned by photolithography and etching processes through the same mask, so as to form a source electrode 51 and a drain electrode 52 on the insulating layer 30 and respectively contacting two ends of the active layer 40, and a first gate electrode 53 and a second gate electrode 54 on the insulating layer 30 and respectively surrounding the source electrode 51 and the drain electrode 52; the first gate 53 and the second gate 54 are in contact with the conductive layer 20 through the first via 31 and the second via 32, respectively;
step S4, please refer to fig. 6, in which a protective layer 60 covering the active layer 40, the insulating layer 30, the source 51, the drain 52, the first gate 53 and the second gate 54 is formed by a chemical vapor deposition method;
step S5, please refer to fig. 7, a photolithography process is performed to dig a hole in the protection layer 60, and a third via hole 61 penetrating through the protection layer 60 and exposing the drain 52 is formed; depositing a transparent conductive layer on the protective layer 60, performing patterning on the transparent conductive layer to form a pixel electrode 70, and performing annealing on the pixel electrode 70; the pixel electrode 70 is in contact with the drain electrode 52 via a third via hole 61.
It should be noted that, in the present invention, the source 51, the drain 52, the first gate 53 and the second gate 54 are simultaneously fabricated by using the same mask, so that the source 51, the drain 52, the first gate 53 and the second gate 54 are all formed on the insulating layer 30, i.e. located on the same plane, to save the production cost and the production time, and an equivalent capacitor is formed between the first gate 53 and the source 51 and between the second gate 54 and the drain 52, and by adjusting the distance between the first gate 53 and the source 51 and the distance between the second gate 54 and the drain 52, the threshold voltage and the sub-threshold swing of the TFT device can be effectively and properly adjusted and controlled, thereby improving the electrical performance of the TFT device.
Specifically, the TFT array substrate further includes a protective layer 60 covering the active layer 40, the insulating layer 30, the source electrode 51, the drain electrode 52, the first gate electrode 53 and the second gate electrode 54, and a pixel electrode 70 disposed on the protective layer 60; the pixel electrode 70 contacts the drain electrode 52 through a third via hole 61 penetrating the protective layer 60.
Specifically, the temperature of the annealing treatment is 200-450 ℃.
Specifically, the material of the conductive layer 20 is one or more of molybdenum, copper and aluminum, that is, the conductive layer 20 may be a single metal thin film layer or a composite metal thin film layer formed by combining multiple metal thin film layers; the thickness of the conductive layer 20 is
The insulating layer 30 is made of one or a combination of silicon oxide and silicon nitride, that is, the insulating layer 30 may be a single silicon oxide layer or a silicon nitride layer, or may be a composite layer formed by a silicon oxide layer and a silicon nitride layer; the thickness of the insulating layer 30 is
Specifically, the active layer 40 is made of indium gallium zinc oxide; the thickness of the active layer 40 is less than
Specifically, the source 51, the drain 52, the first gate 53 and the second gate 54 are made of one or more of aluminum, copper, molybdenum and titanium; the source 51, the drain 52, the first gate 53 and the second gate 54 are all thick
Specifically, the material of the protective layer 60 is oxygenOne or a combination of two of silicon oxide and silicon nitride, that is, the protective layer 60 may be a single silicon oxide layer or a silicon nitride layer, or may be a composite layer formed by a silicon oxide layer and a silicon nitride layer; the thickness of the protective layer 60 is
The material of the pixel electrode 70 is indium tin oxide.
Specifically, the active layer 40 includes a channel region 41 and a source contact region 42 and a drain contact region 43 respectively located at two sides of the channel region 41; the source electrode 51 is in contact with the source contact region 42; the drain electrode 52 is in contact with the drain contact region 43.
Preferably, the distance between the first gate 53 and the source 51 is smaller than the width of the channel region 41; the distance between the second gate 54 and the drain 52 is smaller than the width of the channel region 41, which is beneficial to improving the electrical performance of the TFT device.
In summary, the source, the drain, the first gate and the second gate of the TFT array substrate of the present invention are all formed on the insulating layer, i.e. located on the same plane, so that the source, the drain, the first gate and the second gate can be simultaneously fabricated by using the same mask to save the production cost and the production time, and an equivalent capacitor can be formed between the first gate and the source and between the second gate and the drain, and by adjusting the distance between the first gate and the source and the distance between the second gate and the drain, the threshold voltage and the sub-threshold swing of the TFT device can be effectively and properly adjusted and controlled, and the electrical performance of the TFT device can be improved. According to the manufacturing method of the TFT array substrate, the source electrode, the drain electrode, the first grid electrode and the second grid electrode can be simultaneously manufactured by adopting the same photomask so as to save production cost and production time, equivalent capacitors can be formed between the first grid electrode and the source electrode and between the second grid electrode and the drain electrode, and by adjusting the distance between the first grid electrode and the source electrode and the distance between the second grid electrode and the drain electrode, the threshold voltage and the sub-threshold swing amplitude of a TFT device can be effectively and properly regulated and controlled, and the electrical performance of the TFT device is improved.
As described above, it will be apparent to those skilled in the art that various other changes and modifications can be made based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.
Claims (8)
1. The TFT array substrate is characterized by comprising a substrate base plate (10), a conducting layer (20) arranged on the substrate base plate (10), an insulating layer (30) arranged on the conducting layer (20), an active layer (40) arranged on the insulating layer (30), a source electrode (51) and a drain electrode (52) which are arranged on the insulating layer (30) and are respectively contacted with two ends of the active layer (40), and a first grid electrode (53) and a second grid electrode (54) which are arranged on the insulating layer (30) and are respectively positioned at the periphery of the source electrode (51) and the drain electrode (52);
the first gate (53) and the second gate (54) are in contact with the conductive layer (20) through a first via (31) and a second via (32) respectively, which penetrate the insulating layer (30);
the source electrode (51), the drain electrode (52), the first grid electrode (53) and the second grid electrode (54) are manufactured simultaneously by adopting the same photomask;
the active layer (40) comprises a channel region (41) and a source contact region (42) and a drain contact region (43) which are respectively positioned at two sides of the channel region (41); the source electrode (51) is in contact with a source contact region (42); the drain (52) is in contact with a drain contact region (43);
the distance between the first gate (53) and the source (51) is smaller than the width of the channel region (41); the distance between the second gate (54) and the drain (52) is less than the width of the channel region (41).
2. The TFT array substrate of claim 1, further comprising a protective layer (60) covering the active layer (40), the insulating layer (30), the source electrode (51), the drain electrode (52), the first gate electrode (53), and the second gate electrode (54), and a pixel electrode (70) disposed on the protective layer (60); the pixel electrode (70) is in contact with the drain electrode (52) through a third via hole (61) penetrating the protective layer (60).
3. The TFT array of claim 1The substrate is characterized in that the material of the conductive layer (20) is one or more of molybdenum, copper and aluminum; the thickness of the conductive layer (20) is
The material of the insulating layer (30) is one or the combination of two of silicon oxide and silicon nitride; the thickness of the insulating layer (30) is
The material of the active layer (40) is IGZO; the thickness of the active layer (40) is less than
The source electrode (51), the drain electrode (52), the first grid electrode (53) and the second grid electrode (54) are made of one or more of aluminum, copper, molybdenum and titanium; the source (51), the drain (52), the first gate (53) and the second gate (54) are all thick
4. The TFT array substrate according to claim 2, wherein the protective layer (60) is made of one or a combination of silicon oxide and silicon nitride; the thickness of the protective layer (60) is
The pixel electrode (70) is made of ITO.
5. The TFT array substrate according to claim 1, wherein the channel region (41) has a width of 3 to 5 μm.
6. A manufacturing method of a TFT array substrate is characterized by comprising the following steps:
step S1, providing a substrate (10), and sequentially forming a conductive layer (20) and an insulating layer (30) on the substrate (10) by adopting a physical vapor deposition method;
step S2, depositing an oxide semiconductor layer on the insulating layer (30) by adopting a physical vapor deposition method, and patterning the oxide semiconductor layer through yellow light and etching processes to obtain an active layer (40) on the insulating layer (30) and a first via hole (31) and a second via hole (32) which penetrate through the insulating layer (30) and are respectively positioned on two sides of the active layer (40);
step S3, depositing a metal layer on the insulating layer (30) and the active layer (40), patterning the metal layer through the same mask by using photolithography and etching processes, forming a source electrode (51) and a drain electrode (52) on the insulating layer (30) and contacting with two ends of the active layer (40), and a first gate electrode (53) and a second gate electrode (54) on the insulating layer (30) and surrounding the source electrode (51) and the drain electrode (52); the first gate (53) and the second gate (54) are in contact with the conductive layer (20) through a first via (31) and a second via (32), respectively;
step S4, forming a protective layer (60) covering the active layer (40), the insulating layer (30), the source electrode (51), the drain electrode (52), the first grid electrode (53) and the second grid electrode (54) by using a chemical vapor deposition method;
step S5, digging a hole on the protective layer (60) by adopting a photoetching process to form a third through hole (61) which penetrates through the protective layer (60) and exposes the drain electrode (52); depositing a transparent conductive layer on the protective layer (60), patterning the transparent conductive layer to form a pixel electrode (70), and annealing the pixel electrode (70); the pixel electrode (70) is in contact with the drain electrode (52) through a third via hole (61);
the active layer (40) comprises a channel region (41) and a source contact region (42) and a drain contact region (43) which are respectively positioned at two sides of the channel region (41); the source electrode (51) is in contact with a source contact region (42); the drain (52) is in contact with a drain contact region (43);
the distance between the first gate (53) and the source (51) is smaller than the width of the channel region (41); the distance between the second gate (54) and the drain (52) is less than the width of the channel region (41).
7. The method for manufacturing the TFT array substrate according to claim 6, wherein the material of the conductive layer (20) is one or more of molybdenum, copper and aluminum; the thickness of the conductive layer (20) is
The material of the insulating layer (30) is one or the combination of two of silicon oxide and silicon nitride; the thickness of the insulating layer (30) is
The material of the active layer (40) is IGZO; the thickness of the active layer (40) is less than
The source electrode (51), the drain electrode (52), the first grid electrode (53) and the second grid electrode (54) are made of one or more of aluminum, copper, molybdenum and titanium; the source (51), the drain (52), the first gate (53) and the second gate (54) are all thick
The material of the protective layer (60) is one or the combination of two of silicon oxide and silicon nitride; the thickness of the protective layer (60) is
The pixel electrode (70) is made of ITO;
the temperature of the annealing treatment is 200-450 ℃.
8. The method of fabricating the TFT array substrate of claim 6, wherein the width of the channel region (41) is 3 to 5 μm.
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| CN101887186A (en) * | 2009-05-15 | 2010-11-17 | 乐金显示有限公司 | Array substrate for dislay device and method of fabricating the same |
| CN105070764A (en) * | 2015-08-31 | 2015-11-18 | 深圳市华星光电技术有限公司 | TFT, array substrate, display device, and preparation method of TFT |
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| CN101887186A (en) * | 2009-05-15 | 2010-11-17 | 乐金显示有限公司 | Array substrate for dislay device and method of fabricating the same |
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