CN103178060A - Field effect transistor complementary inverter and production method thereof - Google Patents
Field effect transistor complementary inverter and production method thereof Download PDFInfo
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- CN103178060A CN103178060A CN2011104408444A CN201110440844A CN103178060A CN 103178060 A CN103178060 A CN 103178060A CN 2011104408444 A CN2011104408444 A CN 2011104408444A CN 201110440844 A CN201110440844 A CN 201110440844A CN 103178060 A CN103178060 A CN 103178060A
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Abstract
The invention relates to a field effect transistor complementary inverter which comprises a substrate, an N type field effect transistor and a P type field effect transistor which is arranged to pair the N type field effect transistor. The N type field effect transistor and the P type field effect transistor share a gate electrode as an input terminal of the complementary inverter; a drain electrode of the N type field effect transistor and a drain electrode of the P type field effect transistor are connected to be served as an output terminal of the complementary inverter; the substrate is provided with a plurality of vertically distributed device layers; and the N type field effect transistor and the P type field effect transistor are respectively located on different device layers. Accordingly the field effect transistor complementary inverter has the advantages of further reducing the occupied area of the complementary inverter and accordingy being capable of improving the integration level of an integrated circuit. The invention also discloses a production method of the field effect transistor complementary inverter.
Description
Technical field
The present invention relates to a kind of thin-film transistor, more particularly, relate to field-effect transistor complementary inverter and preparation method thereof.
Background technology
Complementary metal-oxide semiconductor (MOS) (CMOS) inverter is the core cell that consists of digital integrated circuit.For realize on chip more function and faster speed need to be on one chip integrated more transistor, this just requires to reduce transistorized size and the occupied area of wire, so on chip, transistorized size was reduced to nanoscale (size of present high-end chip has reached the 26nm rank) fast from micron order in recent years, can bring larger difficulty to the manufacturing of chip when the live width of integrated circuit is following to 10nm, so only dependence reduces size and increases integrated level and will can not continue too of a specified duration.This just forces the future development of integrated circuit to the many device layers of solid.
Usually, complementary inverter comprises that the PMOS transistor that is installed on together on substrate and nmos pass transistor are with complementation function each other, and nmos pass transistor is connected drain electrode with PMOS and connects and to make output, input is made in their grid connection, the nmos pass transistor source ground, the PMOS transistor source meets supply voltage VDD, thereby this complementary inverter has two transistorized areas occupied.
In order to reduce the area occupied of complementary inverter, existing design is the public grid that adopts PMOS transistor and nmos pass transistor to share, and this layout can reduce certain area occupied.Popularizing due to complementary inverter in design of electronic circuits, the area occupied that further reduces complementary inverter is present expectation place.
Summary of the invention
The object of the present invention is to provide a kind of FET logic inverter of further reduction complementary inverter area occupied.
For achieving the above object, technical scheme of the present invention is as follows:
A kind of field-effect transistor complementary inverter, comprise: substrate, n type field effect transistor, the p type field effect transistor that arranges in pairs with this n type field effect transistor, this n type field effect transistor and p type field effect transistor share a gate electrode and as the input of this complementary inverter, and the drain electrode of this n type field effect transistor is connected drain electrode and is connected output as this complementary inverter with p type field effect transistor; This substrate is provided with the device layer of a plurality of vertical distribution, and this n type field effect transistor and p type field effect transistor lay respectively at different device layers, is respectively the first device layer and the second device layer.
Adopt the complementary inverter of said structure, owing to n type field effect transistor and p type field effect transistor being arranged in the different components layer of vertical distribution, form n type field effect transistor and be positioned at the vertical layout that p type field effect transistor top or p type field effect transistor are positioned at the n type field effect transistor top, thereby further reduced the area occupied of complementary inverter, be of value to the integrated level that improves circuit.
As the further improvement of the above-mentioned field-effect transistor complementary inverter of the present invention, the field-effect transistor on the first device layer is different with the substrate area that field-effect transistor on the second device layer takies.Thereby can arrange on the device layer at the less transistor place of area occupied that other transistor is to realize other functions of integrated circuit.
A kind of preferred version as the above-mentioned field-effect transistor complementary inverter of the present invention: this first device layer and the second device layer are provided with at least one through hole, are filled with metal material in this through hole with the drain electrode that connects described n type field effect transistor and the drain electrode of p type field effect transistor.
Another kind of scheme as the above-mentioned field-effect transistor complementary inverter of the present invention: on this second device layer, transistorized drain electrode is crossed described a plurality of device layer to downward-extension, is communicated with transistorized drain electrode on described the first device layer.
The invention also discloses a kind of method for preparing the field-effect transistor complementary inverter, comprise the steps: to form source electrode, drain electrode, active layer and the gate insulation layer of the first device layer field-effect transistor on substrate; Form the gate electrode that the first device layer field-effect transistor and the second device layer field-effect transistor share; Form gate insulation layer, active layer, source electrode and the drain electrode of the second device layer field-effect transistor; The drain electrode that is communicated with this first, second device layer field-effect transistor.
Description of drawings
Fig. 1 is the structural representation of an embodiment of field-effect transistor complementary inverter of the present invention;
Fig. 2 is the structural representation of another embodiment of field-effect transistor complementary inverter of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
According to one embodiment of present invention, as shown in Figure 1, the n type field effect transistor and the p type field effect transistor that form the field-effect transistor complementary inverter are distributed in two different device layers, and n type field effect transistor is formed on the top of p type field effect transistor or the top that p type field effect transistor is formed on n type field effect transistor; The first device layer and the second device layer are provided with through hole 107, and the drain electrode 102 of the first device layer field-effect transistor and the drain electrode 112 of the second device layer field-effect transistor are connected with metal material by through hole 107.In addition, n type field effect transistor and p type field effect transistor share a gate electrode layer 106, and the gate electrode layer that shares is clipped in the middle of the gate insulation layer 105,115 of n type field effect transistor and p type field effect transistor.
The drain electrode 102 of n type field effect transistor and p type field effect transistor, 112 is connected as the output (Vout) of complementary inverter with metal material by through hole 107, the gate electrode 106 that n type field effect transistor and p type field effect transistor share is as the input (Vin) of complementary inverter, the source electrode of p type field effect transistor connects input power as VDD, and the source ground of n type field effect transistor is as GND.
The metal material that is filled with in above-mentioned through hole is one or more in silver (Ag), aluminium (Al), copper (Cu), caesium (Cs), molybdenum (Mo), tungsten (W).
The further improved execution mode according to the present invention, the area that on Area Ratio the first device layer that on the second device layer, field-effect transistor takies, field-effect transistor takies is little, thereby the transistor that can arrange other at the second device layer is to realize other functions of integrated circuit.Otherwise, effectively same.
Fig. 2 shows an alternative embodiment of the invention, n type field effect transistor and p type field effect transistor lamination are distributed in two device layers, and n type field effect transistor is formed on the top of p type field effect transistor or the top that p type field effect transistor is formed on n type field effect transistor; The drain electrode 112 of the second device layer field-effect transistor is crossed a plurality of device layers to downward-extension, is communicated with and becomes one with transistorized drain electrode 102 on the first device layer, becomes the output (Vout) of complementary inverter.The gate electrode 106 that n type field effect transistor and p type field effect transistor share is as the input (Vin) of complementary inverter, and the source electrode of p type field effect transistor connects input power as VDD, and the source ground of n type field effect transistor is as GND.
The area that on Area Ratio the first device layer that on the second device layer, field-effect transistor takies, field-effect transistor takies is little, thereby the transistor that can arrange other at the second device layer is to realize other functions of integrated circuit.Otherwise, effectively same.
According to an aspect of the present invention, substrate 101 materials can be any one in silicon chip, glass, plastics or pottery, the active layer material of n type field effect transistor and p type field effect transistor can be that a kind of material can be also that the compound of multiple material or stack consist of, the source of n type field effect transistor and p type field effect transistor, drain electrode can be a kind of materials, lamination or the chemical combination that can be also 2 kinds or multiple material form, and can be also that the doping of semi-conducting material consists of.
N type field effect transistor active layer material used is zinc oxide (ZnO), indium oxide (In
2O
3), the method preparation by sputter or chemical vapour deposition (CVD) of amorphous silicon hydride (a-Si), polysilicon, Graphene, germanium, GaAs, perhaps organic material C
60, C
70, fluoro CuPc (F
16CuPc), fluoro Phthalocyanine Zinc (F
16ZnPc), fluoro FePC (F
16FePc), fluoro Cobalt Phthalocyanine (F
16CoPc), chloro CuPc (Cl
16CuPc), chloro Phthalocyanine Zinc (Cl
16ZnPc), chloro FePC (Cl
16FePc), chloro Cobalt Phthalocyanine (Cl
16CoPc), one or more in fluoro six thiophene (DFH-6T), chloro six thiophene (DCIH-6T).Organic material can be by the method preparation of vacuum evaporation or solution spin coating.
p type field effect transistor active layer material used is organic material CuPc (CuPc), Phthalocyanine Zinc (ZnPc), Nickel Phthalocyanine (NiPc), Cobalt Phthalocyanine (CoPc), free base phthalocyanine (H2Pc), phthalocyanine platinum (PtPc), phthalocyanine plumbous (PbPc), vanadyl phthalocyanine (VOPc), titanyl phthalocyanine (TiOPc), pentacene (pentacene), anthracene, aphthacene, rubrene, six biphenyl (p-6P) or inorganic material zinc oxide (ZnO), polysilicon, Graphene, germanium, one or more in GaAs.Organic material is by the method preparation of vacuum evaporation or solution spin coating, and inorganic material is by the method preparation of chemical vapour deposition (CVD) or sputter.
Field-effect transistor gate electrode 106 material used is one or more in gold (Au), silver (Ag), aluminium (Al), copper (Cu), caesium (Cs), molybdenum (Mo), tungsten (W), tantalum (Ta), tin indium oxide (ITO), polysilicon, graphite, can be by chemical vapour deposition (CVD), sputter, evaporation or electric plating method preparation.
The gate insulation layer 105 of n type field effect transistor and p type field effect transistor, 115 materials are inorganic material Ta
2O
5, Al
2O
3, SiO
2, TiO
2, SiN
xPerhaps one or more in polymeric material polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyvinylpyrrolidine copper (PVP), polystyrene (PS), polymethyl methacrylate (PMMA) and poly-ethyl propylene acid esters (PCA).Inorganic material can be by the method preparation of chemical vapour deposition (CVD), and organic material is by the method preparation of spin coating.
The source of above-mentioned field-effect transistor, drain electrode 102,103,112,113 materials used are one or more in gold (Au), silver (Ag), aluminium (Al), copper (Cu), caesium (Cs), molybdenum (Mo), tungsten (W), tantalum (Ta), tin indium oxide (ITO), polysilicon, graphite, can be by chemical vapour deposition (CVD), sputter, evaporation or electric plating method preparation.
A kind of preparation method of field-effect transistor complementary inverter of the present invention is as follows:
Select thin glass as substrate 101, and clean up, oven dry;
Adopt magnetically controlled sputter method to prepare the thick aluminium of 50nm (Al), serve as source, the drain electrode layer of the first device layer field-effect transistor, and adopt the method for photoetching to define and etch source, drain electrode 102,103 and the figure of wire;
Adopt the method for magnetron sputtering to prepare the thick ZnO film of 40nm as the first device layer field-effect transistor active layer 104;
Adopt the method for PECVD to prepare the thick SiNx of 200nm as the first device layer field-effect transistor gate insulation layer 105;
Adopt the method for magnetron sputtering to prepare the thick Al film of 50nm as the first device layer and the shared gate electrode layer of the second device layer field-effect transistor.And define and etch the gate electrode 106 of N-type and p type field effect transistor and the shape that goes between by the method for photoetching;
Adopt the method for PECVD to prepare the thick SiNx of 200nm as the second device layer field-effect transistor gate insulation layer 115;
Adopt the method for vacuum evaporation to prepare the thick pentacene thin film of 30nm, as the second device layer field-effect transistor active layer 114;
The method of employing vacuum evaporation prepares the copper after 50nm, as source, the drain electrode layer of the second device layer field-effect transistor;
The method of employing photoetching defines position and the shape of the through hole 107 that connects the upper and lower two device layer transistor leakage utmost points, 1 micron of through-hole diameter, and via depth terminates in the first transistorized drain electrode layer 102 of device layer, then photoresist lift off is fallen; Adopt the method for PECVD to deposit the metal material tungsten that filling vias is used, through hole 107 is filled up;
Adopt the method for photoetching to define the figure of upper and lower two device layer transistor area, and successively etch the two-layer transistorized shape in up and down;
Adopt the method for photoetching to define and etch the second device layer transistorized source, drain electrode figure 112,113.
Above-described is only the preferred embodiments of the present invention; described embodiment limits scope of patent protection of the present invention; therefore the equivalent structure done of every utilization specification of the present invention and accompanying drawing content changes, and in like manner all should be included in protection scope of the present invention.
Claims (9)
1. field-effect transistor complementary inverter comprises:
Substrate, n type field effect transistor, the p type field effect transistor that arranges in pairs with this n type field effect transistor, this n type field effect transistor and p type field effect transistor share a gate electrode and as the input of this complementary inverter, and the drain electrode of this n type field effect transistor is connected drain electrode and is connected output as this complementary inverter with p type field effect transistor;
It is characterized in that: this substrate is provided with the device layer of a plurality of vertical distribution, and this n type field effect transistor and p type field effect transistor lay respectively at different device layers, is respectively the first device layer and the second device layer.
2. field-effect transistor complementary inverter as claimed in claim 1, is characterized in that, the field-effect transistor on described the first device layer is different with the substrate area that field-effect transistor on the second device layer takies.
3. field-effect transistor complementary inverter as claimed in claim 1, it is characterized in that, described the first device layer and the second device layer are provided with at least one through hole, are filled with metal material in this through hole with the drain electrode that connects described n type field effect transistor and the drain electrode of p type field effect transistor.
4. field-effect transistor complementary inverter as claimed in claim 3, is characterized in that, the metal material that is filled with in through hole is one or more in Ag, Al, Cu, Cs, Mo, W.
5. field-effect transistor complementary inverter as claimed in claim 1, is characterized in that, on described the second device layer, the drain electrode of field-effect transistor is crossed described a plurality of device layer to downward-extension, is communicated with the drain electrode of field-effect transistor on described the first device layer.
6. field-effect transistor complementary inverter as described in any one in claim 1 to 5, is characterized in that, described gate electrode is arranged on the centre of the gate insulation layer of the gate insulation layer of described n type field effect transistor and p type field effect transistor by double team.
7. field-effect transistor complementary inverter as described in any one in claim 1 to 5, is characterized in that, described baseplate material can be any one in silicon chip, glass, plastics or pottery.
8. a method of making field-effect transistor complementary inverter claimed in claim 1, comprise the steps:
1) form source electrode, drain electrode, active layer and the gate insulation layer of the first device layer field-effect transistor on substrate;
2) form the gate electrode that the first device layer field-effect transistor and the second device layer field-effect transistor share;
3) form gate insulation layer, active layer, source electrode and the drain electrode of the second device layer field-effect transistor;
4) be communicated with the drain electrode of this first, second device layer field-effect transistor.
9. the method for manufacturing field-effect transistor complementary inverter as claimed in claim 8, it is characterized in that, described step 4) specifically comprise in: adopt the method for photoetching to form through hole on this first device layer and the second device layer, then stripping photoresist, adopt the method deposition of PECVD to fill the metal material that this through hole is used at last.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Cited By (7)
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| CN103812501A (en) * | 2014-02-13 | 2014-05-21 | 清华大学 | Phase inverter |
| CN106057153A (en) * | 2016-07-20 | 2016-10-26 | 武汉华星光电技术有限公司 | Inverter structure and display panel thereof |
| CN109148375A (en) * | 2018-08-20 | 2019-01-04 | 深圳市华星光电技术有限公司 | Film transistor device manufacturing method and film transistor device |
| CN109285948A (en) * | 2018-11-27 | 2019-01-29 | 哈尔滨理工大学 | A kind of organic transistor with lateral high-order structures |
| CN110060998A (en) * | 2019-04-29 | 2019-07-26 | 厦门天马微电子有限公司 | A kind of inverter cricuit structure, gate driving circuit and display panel |
| CN110808247A (en) * | 2019-10-18 | 2020-02-18 | 华东师范大学 | Complementary vertical ring gate field effect transistor capable of realizing function of phase inverter |
| CN113644907A (en) * | 2021-08-31 | 2021-11-12 | 复旦大学 | D latch constructed by common gate complementary field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103812501A (en) * | 2014-02-13 | 2014-05-21 | 清华大学 | Phase inverter |
| CN103812501B (en) * | 2014-02-13 | 2017-02-15 | 清华大学 | Phase inverter |
| CN106057153A (en) * | 2016-07-20 | 2016-10-26 | 武汉华星光电技术有限公司 | Inverter structure and display panel thereof |
| CN106057153B (en) * | 2016-07-20 | 2018-11-23 | 武汉华星光电技术有限公司 | Inverter structure and its display panel |
| CN109148375A (en) * | 2018-08-20 | 2019-01-04 | 深圳市华星光电技术有限公司 | Film transistor device manufacturing method and film transistor device |
| CN109285948A (en) * | 2018-11-27 | 2019-01-29 | 哈尔滨理工大学 | A kind of organic transistor with lateral high-order structures |
| CN110060998A (en) * | 2019-04-29 | 2019-07-26 | 厦门天马微电子有限公司 | A kind of inverter cricuit structure, gate driving circuit and display panel |
| CN110808247A (en) * | 2019-10-18 | 2020-02-18 | 华东师范大学 | Complementary vertical ring gate field effect transistor capable of realizing function of phase inverter |
| CN113644907A (en) * | 2021-08-31 | 2021-11-12 | 复旦大学 | D latch constructed by common gate complementary field effect transistor |
| CN113644907B (en) * | 2021-08-31 | 2023-07-07 | 复旦大学 | D-latch built with common-gate complementary field effect transistors |
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