CN106057153B - Inverter structure and its display panel - Google Patents
Inverter structure and its display panel Download PDFInfo
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- CN106057153B CN106057153B CN201610573440.5A CN201610573440A CN106057153B CN 106057153 B CN106057153 B CN 106057153B CN 201610573440 A CN201610573440 A CN 201610573440A CN 106057153 B CN106057153 B CN 106057153B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides a kind of inverter structure and its display panel, the inverter structure includes the first transistor and second transistor, wherein, the first transistor is made of the first source electrode, the first source region, the first channel region, the first drain region, the first drain electrode and first gate electrode；Second transistor is made of the second source electrode, the second source region, the second channel region, the second drain region, the second drain electrode and the second gate electrode.Inverter structure provided by the invention is due to being equipped with the first drain region and the second drain region, first drain region and the second drain region are mutually matched and are arranged in the same row, the height and area of inverter structure can be reduced, to reach the height and area that reduce display panel, so as to save the cost.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of inverter structures and its display panel.
Background technique
Phase inverter is the phasing back 180 degree of input signal, inverter circuit can be mainly used in analog circuit,
Such as audio amplifier circuit, clock oscillator circuit etc..In the route design of liquid crystal display panel, also often to use anti-
Phase device circuit.
Currently, low temperature polycrystalline silicon (LTPS) semiconductor thin-film transistor route design in, the structure of phase inverter be by
NTFT and PTFT are individually designed, therefore the height of phase inverter and area will affect height and the face of entire liquid crystal display panel
Product, to increase cost.
Summary of the invention
The present invention provides a kind of inverter structure and its display panel, to solve the height of phase inverter and face in the prior art
Product influences the technical issues of height and the area of liquid crystal display panel are to increase cost.
In order to solve the above technical problems, one technical scheme adopted by the invention is that：A kind of inverter structure is provided, it is described
Inverter structure includes：
Polysilicon layer, wherein the polysilicon layer include the first source region, the first drain region, the first channel region,
Second source region, the second drain region and the second channel region, first drain region and second drain region phase
Mutually matching and setting in the same row, and region composed by first drain region and second drain region with it is described
First source region and second source region are opposite respectively, first channel region be located at first source region with
Between region composed by first drain region and second drain region, and second channel region is positioned at described
Between region composed by second source region and first drain region and second drain region；
Gate metal layer, including first gate electrode and the second gate electrode, wherein first gate electrode setting is described the
On one channel region, and second gate electrode be arranged on second channel region, and the first gate electrode with it is described
Second gate electrode is electrically connected using the input terminal as the phase inverter；
First source electrode is arranged on first source region；
Second source electrode is arranged on second source region；
Drain metal layer, including the first drain electrode and the second drain electrode, wherein first drain electrode setting is described the
On one drain region, and second drain electrode is arranged on second drain region, and first drain electrode and described
Second drain electrode is electrically connected using the output end as the phase inverter；
Wherein, first source electrode, first source region, first channel region, first drain region
Domain, first drain electrode and the first gate electrode constitute the first transistor；And second source electrode, second source electrode
Region, second channel region, second drain region, second drain electrode and second gate electrode constitute second
Transistor.
An embodiment according to the present invention, first drain region and second drain region are respectively strip knot
Structure, and first drain region and second drain region arrangement are in the same row.
An embodiment according to the present invention, first drain region include the first main part and the first extension, institute
The width for stating the first extension is less than the width of first main part, and first extension is main from described first
Body portion extends close to the edge of first channel region to the direction of second drain region；
Second drain region includes the second main part and the second extension, the width of second extension
Less than the width of second main part, and second extension from second main part close to second ditch
The edge in road region extends to the direction of first drain region；
Wherein, first main part and second main part are at least partly staggeredly opposite, and described first prolongs
The extending direction of extending portion point and second extension is relative to each other.
An embodiment according to the present invention, the inverter structure further comprise：
Interlayer dielectric layer, setting the polysilicon layer and the gate metal layer, the first source electrode, the second source electrode and
Between the drain metal layer.
An embodiment according to the present invention, first source electrode are connected to first source electrode by least one hole
Region, first drain electrode are connected to first drain region by least one hole；Second source electrode is logical
It crosses at least one hole and is connected to second source region, second drain electrode is connected to by least one hole
Second drain region.
An embodiment according to the present invention, first drain electrode and second drain electrode integrate.
An embodiment according to the present invention, the first transistor is first kind transistor, and the second transistor is
Second Type transistor, and the first kind transistor is different with the type of the Second Type transistor.
An embodiment according to the present invention, the first transistor is P-type TFT, and the second transistor is N
Type thin film transistor (TFT).
An embodiment according to the present invention, first source region are P-doped zone domain, and first drain region is P
Type doped region；And second source region is n-type doping region, second drain region is n-type doping region.
Another technical solution used in the present invention is：A kind of display panel is provided, the display panel includes above-mentioned institute
The inverter structure stated.
The beneficial effects of the invention are as follows：It is in contrast to the prior art, inverter structure provided by the invention is due to setting
There are the first drain region and the second drain region, the first drain region and the second drain region are mutually matched and are arranged in same a line
In, it is possible to reduce the height and area of inverter structure, to reach the height and area for reducing display panel, to save into
This.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, wherein：
Fig. 1 is the layout design schematic diagram of inverter structure first embodiment provided by the invention；
Fig. 2 is the circuit diagram of inverter structure first embodiment provided by the invention；
Fig. 3 is the layout design schematic diagram of inverter structure second embodiment provided by the invention；
Fig. 4 is the layout design schematic diagram of inverter structure second embodiment provided by the invention；
Fig. 5 is the structural schematic diagram of one embodiment of display panel provided by the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that the described embodiments are merely a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, Fig. 1 is the layout design schematic diagram of inverter structure first embodiment provided by the invention.
As shown in Figure 1, the inverter structure 100 includes polysilicon layer 110, gate metal layer 120 and drain metal layer
130, wherein gate metal layer 120 and drain metal layer 130 can be set in same layer, also can be set in different layers.
Wherein, polysilicon layer 110 include the first source region 101, the first drain region 103, the first channel region 102,
Second source region 104, the second drain region 106 and the second channel region 105, the first drain region 103 and the second drain region
Domain 106 is mutually matched and is arranged in the same row, and region composed by the first drain region 103 and the second drain region 106
Opposite respectively with the first source region 101 and the second source region 104, the first channel region 102 is located at the first source region 101
Between region composed by the first drain region 103 and the second drain region 106, and the second channel region 105 is located at second
Between region composed by source region 104 and the first drain region 103 and the second drain region 106.
Gate metal layer 120 includes first gate electrode 121 and the second gate electrode 122, wherein first gate electrode 121 is arranged
On the first channel region 102, and the second gate electrode 122 be arranged on the second channel region 105, and first gate electrode 121 with
Second gate electrode 122 is electrically connected using the input terminal In as phase inverter 100.
First source electrode 111 is arranged on the first source region 101, and the first source electrode 111 is connect with high potential VGH；The
Two source electrodes 112 are arranged on the second source region 104, and the second source electrode 112 is connect with low potential VGL.
Drain metal layer 130 includes the first drain electrode 131 and the second drain electrode 132, wherein the setting of the first drain electrode 131
On the first drain region 103, and the second drain electrode 132 is arranged on the second drain region 106, and 131 He of the first drain electrode
Second drain electrode 132 is electrically connected using the output end Out as phase inverter 100.
Wherein, the first source electrode 111, the first source region 101, the first channel region 102, the first drain region 103,
One drain electrode 131 and first gate electrode 121 constitute the first transistor 150 (being represented by dotted lines)；And the second source electrode 112, second
Source region 104, the second channel region 105, the second drain region 106, the second drain electrode 132 and the second gate electrode 122 are constituted
Second transistor 160 (is represented by dotted lines), and phase inverter 100 is made of the first transistor 150 and second transistor 160, specific electricity
Road figure is shown in Fig. 2.
Inverter structure 100 provided by the invention is due to being equipped with the first drain region 103 and the second drain region 106, and the
One drain region 103 and the second drain region 106 are mutually matched and are arranged in the same row, it is possible to reduce inverter structure 100
Height and area, thus reach reduce display panel height and area, so as to save the cost.
In the present embodiment, the first drain electrode 131 and the second drain electrode 132 integrate；First source electrode 111 and
Two source electrodes 112 can be arranged with the first drain electrode 131 and the second drain electrode 132 in same layer.Wherein, the first drain region
103 and second drain region 106 be respectively strip structure, and the first drain region 103 and the second drain region 106 are arranged in
With in a line, arrangement architecture can be divided into left-right situs.
The first transistor 150 is first kind transistor, and second transistor 160 is Second Type transistor, and first
Type of transistor is different with the type of Second Type transistor；Specifically, the first transistor 150 is P-type TFT, and the
Two-transistor 160 is N-type TFT.
Specifically, the first source region 101 is P-doped zone domain, the first drain region 103 is P-doped zone domain, p-type
Doped region is incorporation trivalent impurity element, such as boron, gallium；And the second source region 104 is n-type doping region, the second drain region
Domain 106 is n-type doping region, and n-type doping region is incorporation pentavalent impurity element, such as phosphorus, arsenic.
Further, inverter structure 100 includes interlayer dielectric layer (not shown), and interlayer dielectric layer is arranged in polysilicon layer
Between 110 and gate metal layer 120, the first source electrode 111, the second source electrode 112 and drain metal layer 130.Specifically, interlayer
Dielectric layer can be set between polysilicon layer 110 and gate metal layer 120；Interlayer dielectric layer can be set in gate metal layer
Between 120 and drain metal layer 130；Interlayer dielectric layer setting can between the first source electrode 111 and the second source electrode 112,
I.e. interlayer dielectric layer can be set between the different layers, also can be set between same layer electrode, to play isolation and insulation
Effect.
Referring to Fig. 3, Fig. 3 is the layout design schematic diagram of inverter structure second embodiment provided by the invention.
As shown in figure 3, the first drain region 203 include the first main part 2031 and the first extension 2032, first
The width of extension 2032 is less than the width of the first main part 2031, and the first extension 2032 is from the first main part
2031 extend close to the edge of the first channel region 202 to the direction of the second drain region 206；Second drain region 206 packet
The second main part 2061 and the second extension 2062 are included, the width 2062 of the second extension is less than the second main part
2061 width, and the second extension 2062 from the second main part 2061 close to the edge of the second channel region 205 to
The direction of first drain region 203 extends；Wherein, the first main part 2031 is at least partly interlocked with the second main part 2061
Relatively, and the extending direction of the first extension 2032 and the second extension 2062 is relative to each other.The domain of second embodiment
Design not only reduces the height and area of inverter structure 200, it can also be ensured that the channel of the first transistor and second transistor
The effective width in region.
Referring to Fig. 4, Fig. 4 is the layout design schematic diagram of inverter structure 3rd embodiment provided by the invention.
As shown in figure 4, the first source electrode 311 is connected to the first source region 301 by least one hole 307, the
One drain electrode 331 is connected to the first drain region 303 by least one hole 307；Second source electrode 312 passes through at least one
A hole 307 and be connected to the second source region 304, the second drain electrode 332 is connected to second by least one hole 307
Drain region 306.
Referring to Fig. 5, Fig. 5 is the structural schematic diagram of one embodiment of display panel provided by the invention.
As shown in figure 5, the display panel 40 includes multiple above-mentioned inverter structures 300, the setting of inverter structure 300 exists
In the route design of 40 peripheral circuit of display panel.
Wherein, the structure of inverter structure 300 is seen above, and it is no longer repeated herein.
In conclusion it should be readily apparent to one skilled in the art that inverter structure provided by the invention is due to being equipped with the first leakage
Polar region domain and the second drain region, the first drain region and the second drain region are mutually matched and are arranged in the same row, can be with
The height and area of inverter structure are reduced, to reach the height and area for reducing display panel, so as to save the cost.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills
Art field, is included within the scope of the present invention.
Claims (8)
1. a kind of inverter structure, which is characterized in that the inverter structure includes：
Polysilicon layer, wherein the polysilicon layer includes the first source region, the first drain region, the first channel region, second
Source region, the second drain region and the second channel region, first drain region and mutual of second drain region
Match and be arranged in the same row, and region and described first composed by first drain region and second drain region
Source region and second source region are opposite respectively, first channel region be located at first source region with it is described
Between region composed by first drain region and second drain region, and second channel region is located at described second
Between region composed by source region and first drain region and second drain region, wherein first leakage
Polar region domain includes the first main part and the first extension, and the width of first extension is less than first main part
Point width, and first extension from first main part close to the edge of first channel region to institute
The direction for stating the second drain region extends；
Second drain region includes the second main part and the second extension, and the width of second extension is less than
The width of second main part, and second extension from second main part close to second channel region
The edge in domain extends to the direction of first drain region；
Wherein, first main part and second main part are at least partly staggeredly opposite, and first extension
Divide and the extending direction of second extension is relative to each other；
Gate metal layer, including first gate electrode and the second gate electrode, wherein the first gate electrode is arranged in first ditch
On road region, and second gate electrode is arranged on second channel region, and the first gate electrode and described second
Gate electrode is electrically connected using the input terminal as the phase inverter；
First source electrode is arranged on first source region；
Second source electrode is arranged on second source region；
Drain metal layer, including the first drain electrode and the second drain electrode, wherein the first drain electrode setting is in first leakage
On polar region domain, and second drain electrode is arranged on second drain region, and first drain electrode and described second
Drain electrode is electrically connected using the output end as the phase inverter；
Wherein, first source electrode, first source region, first channel region, first drain region, institute
It states the first drain electrode and the first gate electrode constitutes the first transistor；And second source electrode, second source region,
Second channel region, second drain region, second drain electrode and second gate electrode constitute the second crystal
Pipe.
2. inverter structure according to claim 1, which is characterized in that the inverter structure further comprises：
Interlayer dielectric layer, setting is in the polysilicon layer and the gate metal layer, the first source electrode, the second source electrode and described
Between drain metal layer.
3. inverter structure according to claim 2, which is characterized in that first source electrode passes through at least one hole
And it is connected to first source region, first drain electrode is connected to first drain region by least one hole
Domain；Second source electrode is connected to second source region by least one hole, and second drain electrode passes through
At least one hole and be connected to second drain region.
4. inverter structure according to claim 1, which is characterized in that first drain electrode and second drain electrode
It integrates.
5. inverter structure according to claim 1, which is characterized in that the first transistor is first kind crystal
Pipe, and the second transistor is Second Type transistor, and the first kind transistor and the Second Type transistor
Type it is different.
6. inverter structure according to claim 5, which is characterized in that the first transistor is P-type TFT,
And the second transistor is N-type TFT.
7. inverter structure according to claim 6, which is characterized in that first source region is P-doped zone domain,
First drain region is P-doped zone domain；And second source region is n-type doping region, second drain region
Domain is n-type doping region.
8. a kind of display panel, which is characterized in that the display panel includes the phase inverter as described in claim 1 to 7 is any
Structure.
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| CN201610573440.5A CN106057153B (en) | 2016-07-20 | 2016-07-20 | Inverter structure and its display panel |
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| CN201610573440.5A CN106057153B (en) | 2016-07-20 | 2016-07-20 | Inverter structure and its display panel |
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| CN106057153B true CN106057153B (en) | 2018-11-23 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536668A (en) * | 2003-05-08 | 2004-10-13 | �Ѵ���ɷ�����˾ | Complementary metal oxide semiconductor phase reverser |
| CN103178060A (en) * | 2011-12-23 | 2013-06-26 | 上海中科联和显示技术有限公司 | Field effect transistor complementary inverter and production method thereof |
| CN103812501A (en) * | 2014-02-13 | 2014-05-21 | 清华大学 | Phase inverter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100652424B1 (en) * | 2005-08-12 | 2006-12-01 | 삼성전자주식회사 | Cmos inverter cell |
| KR101167202B1 (en) * | 2005-11-24 | 2012-07-24 | 매그나칩 반도체 유한회사 | Mos transistor and cmos inverter, and method for manufacturing the same |
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- 2016-07-20 CN CN201610573440.5A patent/CN106057153B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536668A (en) * | 2003-05-08 | 2004-10-13 | �Ѵ���ɷ�����˾ | Complementary metal oxide semiconductor phase reverser |
| CN103178060A (en) * | 2011-12-23 | 2013-06-26 | 上海中科联和显示技术有限公司 | Field effect transistor complementary inverter and production method thereof |
| CN103812501A (en) * | 2014-02-13 | 2014-05-21 | 清华大学 | Phase inverter |
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