CN101320181B - Display device and method of manufacturing the same - Google Patents
Display device and method of manufacturing the same Download PDFInfo
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- CN101320181B CN101320181B CN2008100986443A CN200810098644A CN101320181B CN 101320181 B CN101320181 B CN 101320181B CN 2008100986443 A CN2008100986443 A CN 2008100986443A CN 200810098644 A CN200810098644 A CN 200810098644A CN 101320181 B CN101320181 B CN 101320181B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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Abstract
The invention provides a display device capable of reducing resistive leakage current of a bottom-grid TFT element using a polycrystalline semiconductor. The inventive semiconductor device is sequentially superposed on a surface of an insulating substrate with a grid electrode, a grid insulating film, a semiconductor layer, a source electrode and a drain electrode, and also includes the TFT element, the TFT element is composed of an active layer composed of polycrystalline semiconductor using the semiconductor layer, and contact layers that are respectively located between the active layer and the source electrode as well as between the active layer and the drain electrode; the source electrode and the drain electrode respectively include a first face opposite to an intersected face of the active layer and the grid insulating layer, and a second face opposite to an etched side face of the active layer, the contact layers are disposed between the active layer and the first faces of the source electrode and drain electrode, and the entire regions are disposed between the active layer and the second faces of the source electrode and drain electrode.
Description
Technical field
The present invention relates to semiconductor devices and manufacturing approach thereof, especially relate to the TFT LCD panel that effectively is applicable to built-in drive circuit and the technology of manufacturing approach thereof.
Background technology
In the past, the TFT element was widely used in the semiconductor devices such as IC chip, LCD panel such as CPU, storer.
The structure of above-mentioned TFT element is that the surperficial laminated at insulated substrate has gate electrode, grid (utmost point) dielectric film, semiconductor layer (semiconductor film), source electrode and drain electrode; The difference of lamination order according to them is broadly divided into top gate type TFT element and bottom gate type TFT element.The structure of above-mentioned top gate type TFT element is: observe then for the TFT element of gate insulating film and gate electrode is arranged in the semiconductor layer laminated from above-mentioned insulated substrate.The structure of above-mentioned bottom gate type TFT element is: observe then for the TFT element of gate insulating film and semiconductor layer is arranged in the gate electrode laminated from above-mentioned insulated substrate.
Above-mentioned LCD panel in the above-mentioned semiconductor device is between a pair of substrate, to have enclosed liquid crystal material and the display board that constitutes, and a substrate in the above-mentioned a pair of substrate for example is formed with multi-strip scanning signal wire, multiple bar chart image signal line, is configured to rectangular a plurality of TFT elements and is configured to rectangular pixel electrode etc. on the surface of insulated substrates such as glass substrate.
In addition; In LCD panel with above-mentioned TFT element; Normally be used to generate the drive IC that the driving circuit of the sweep signal that puts on above-mentioned multi-strip scanning signal wire, the driving circuit that is used to generate the picture signal that puts on above-mentioned multiple bar chart image signal line for example are formed on shaped like chips in the past, semiconductor package parts such as COF that this drive IC is installed, TCP and the substrate that is formed with said scanning signals line etc. (below be called the TFT substrate) are connected.
But; Following such structure is for example also arranged: formed above-mentioned each driving circuit in the outside, viewing area of above-mentioned TFT substrate (insulated substrate) with said scanning signals line etc., promptly in above-mentioned LCD panel (TFT substrate), be built-in with above-mentioned each driving circuit in LCD panel in recent years.
In addition, in above-mentioned semiconductor device, in the time of forming the TFT element of bottom gate type, in the past active layers that were to use the such amorphous semiconductor of amorphous silicon (a-Si) for example as semiconductor layer more.But, in semiconductor devices in recent years,, for example use the such poly semiconductor of polysilicon (poly-Si) to increase gradually as the situation of the active layer of semiconductor layer for the high speed that reaches work etc.
Summary of the invention
In the time of will forming bottom gate type TFT element on the insulated substrate surface, form gate electrode and gate insulating film on the surface of insulated substrate.Then; Second semiconductor film that forms first semiconductor film that the active layer as semiconductor layer plays a role successively and play a role as the contact layer (diffusion layer) of first semiconductor layer; Then above-mentioned each semiconductor film is carried out etching, form the semiconductor layer of island.Then, formed after the conducting film, this conducting film is carried out etching and forms source electrode and drain electrode.Then, utilize the etching that source electrode and drain electrode are made mask, make second semiconductor film that is laminated on first semiconductor film (active layer) with between between source electrode and the active layer and the contact layer between drain electrode and active layer separate.
But; In the bottom gate type TFT element that forms with such order, there is following problem: if the active layer of semiconductor layer is a poly semiconductor; Then for example when this TFT element is cut-off state, the resistive electric leakage rheology of then between drain electrode and source electrode, flowing through is big.
The object of the present invention is to provide a kind of technology of resistive leakage current of the bottom gate type TFT element that reduces to use poly semiconductor.
Above-mentioned and other purposes and new feature of the present invention will be able to clear through the record and the accompanying drawing of this instructions.
Below, representative technical scheme among diagrammatic illustration the present invention.
Display device of the present invention has insulated substrate, is formed with the TFT element on the insulated substrate surface.The TFT element has gate electrode, gate insulating film, semiconductor layer, source electrode and drain electrode.Semiconductor layer by the active layer that constitutes with poly semiconductor and respectively between between active layer and the source electrode and the contact layer between active layer and the drain electrode constitute.Source electrode and drain electrode have first relative and second relative with the etched facet of active layer of interface with the same gate insulating film of active layer respectively.Contact layer is between between source electrode and drain electrode first and the active layer and between source electrode and drain electrode second and the active layer.
Source electrode and drain electrode second with active layer between get involved the insulation course different with gate insulating film arranged.
Display device has insulated substrate, stacks gradually gate electrode, gate insulating film, semiconductor layer, source electrode and drain electrode on the insulated substrate surface.Semiconductor layer by the active layer that constitutes with poly semiconductor and respectively between between active layer and the source electrode and the contact layer between active layer and the drain electrode constitute.Source electrode and drain electrode have first relative and second relative with the etched facet of active layer of interface with the same gate insulating film of active layer respectively.Contact layer is between between source electrode and drain electrode first and the active layer, and get involved in the zone that does not have contact layer between source electrode and drain electrode and active layer has the insulation course different with gate insulating film.
The flat shape that projects to the insulated substrate surface of contact layer, source electrode and drain electrode is roughly the same.
The source electrode is a duplexer of forming different two or more conducting films with drain electrode.
The surface of insulated substrate has multi-strip scanning signal wire and multiple bar chart image signal line, is configured to rectangular pixel being formed with by two scan signal lines and two chromosome image signal line area surrounded, is configured to rectangular pixel and forms the viewing area.
On pixel, be formed with the on-off element and the pixel electrode that constitute by the TFT element.On-off element is connected with pixel electrode with image signal line.
A kind of semiconductor devices, the exterior lateral area of insulated substrate in the viewing area disposes the driving circuit with TFT element.Driving circuit has multi-strip scanning signal wire, multiple bar chart image signal line, on-off element and pixel electrode, and is formed at the insulated substrate surface.
On-off element is following such TFT element, stack gradually gate electrode, gate insulating film, semiconductor layer, source electrode and drain electrode and form, and the active layer of semiconductor layer is made up of amorphous semiconductor.
A kind of manufacturing approach of display device, this display device are on insulated substrate, to form to stack gradually the TFT element that gate electrode, gate insulating film, semiconductor layer, source electrode and drain electrode form, and comprise following operation:
First operation forms gate electrode,
Second operation after first operation, forms gate insulating film,
The 3rd operation after second operation, uses poly semiconductor to form active layer,
The 4th operation after the 3rd operation, forms semiconductor film that dopant species is different or concentration is different and conducting film with active layer,
The 5th operation after the 4th operation, is carried out etching and is formed source electrode and drain electrode conducting film,
The 6th operation after the 5th operation, is carried out etching to semiconductor film and is formed respectively between between source electrode and the active layer and the contact layer between drain electrode and the active layer.
In the 4th operation, after having formed semiconductor film, form insulation course, with a part or the whole opening on the active layer that be positioned in this dielectric film, thereby form conducting film.
In the 3rd operation, forming amorphous semiconductor film, and after a part of zone or Zone Full polycrystallization with this amorphous semiconductor film, carry out etching and form active layer.
Semiconductor device according to the invention, in using the bottom gate type TFT element of poly semiconductor as the active layer of semiconductor layer, can reduce by the time the resistive leakage current.
The manufacturing approach of semiconductor device according to the invention can be made the semiconductor devices with following such bottom gate type TFT element easily, this TFT element use poly semiconductor as the active layer of semiconductor layer and by the time the resistive leakage current less.
Description of drawings
Figure 1A is the routine diagrammatic top view of a formation of the TFT element of the expression embodiment of the invention 1.
Figure 1B is A-A ' the line cut-open view of Figure 1A.
Fig. 2 A has just formed active layer schematic sectional view afterwards.
Fig. 2 B has just formed second semiconductor film and conducting film schematic sectional view afterwards.
Fig. 2 C is just to the schematic sectional view after the conducting film etching.
Fig. 2 D is just to the schematic sectional view after the second semiconductor film etching.
Fig. 3 A is a schematic sectional view of representing a formation example of bottom gate type TFT element in the past.
The schematic sectional view of one example of the current direction when Fig. 3 B is the gate turn-on of the TFT element shown in the presentation graphs 3A.
Fig. 3 C be the grid that is illustrated in the TFT element shown in Fig. 3 A by the time phenomenon that produced the schematic sectional view of an example.
Fig. 4 A is the diagrammatic top view of first variation of the TFT element of expression embodiment 1.
Fig. 4 B is B-B ' the line cut-open view of Fig. 4 A.
Fig. 5 is the diagrammatic top view of second variation of the TFT element of expression embodiment 1.
Fig. 6 is the diagrammatic top view of the 3rd variation of the TFT element of expression embodiment 1.
Fig. 7 A is the diagrammatic top view of the example that constitutes of the summary of expression LCD panel.
Fig. 7 B is C-C ' the line cut-open view of Fig. 7 A.
Fig. 7 C is the routine diagrammatic top view of a formation of the TFT substrate of presentation graphs 7A.
Fig. 8 A is the routine diagrammatic top view of a formation of a pixel of the viewing area in the expression TFT substrate.
Fig. 8 B is D-D ' the line cut-open view of Fig. 8 A.
Fig. 8 C is E-E ' the line cut-open view of Fig. 8 A.
Fig. 9 is the schematic sectional view of application examples of the TFT element of expression embodiment 1.
Figure 10 is the schematic sectional view of an example that is used to explain the manufacturing approach of TFT element shown in Figure 9.
Figure 11 is the routine schematic sectional view of a formation of the TFT element of the expression embodiment of the invention 2.
Figure 12 A has just formed second semiconductor film schematic sectional view afterwards.
Figure 12 B has just formed the 3rd insulation course schematic sectional view afterwards.
Figure 12 C has just formed source electrode and drain electrode schematic sectional view afterwards.
Figure 12 D is just to the schematic sectional view after the second semiconductor film etching.
Figure 13 A is the schematic sectional view of first variation of the TFT element of expression embodiment 2.
Figure 13 B is the schematic sectional view of second variation of the TFT element of expression embodiment 2.
Figure 13 C is the schematic sectional view of the 3rd variation of the TFT element of expression embodiment 2.
Figure 14 is the routine schematic sectional view of a formation of the TFT element of the expression embodiment of the invention 3.
Figure 15 A has just formed the 3rd insulation course schematic sectional view afterwards.
Figure 15 B has just formed second semiconductor film schematic sectional view afterwards.
Figure 16 A is the schematic sectional view of first variation of the TFT element of expression embodiment 3.
Figure 16 B is the schematic sectional view of second variation of the TFT element of expression embodiment 3.
Embodiment
Below, for the present invention, specify embodiment (embodiment) with reference to accompanying drawing.
Be used for whole accompanying drawings of illustrative embodiment, the parts with identical function are marked identical Reference numeral and omit its repeat specification.
Figure 1A is the routine diagrammatic top view of a formation of the TFT element of the expression embodiment of the invention 1.Figure 1B is the A-A ' cut-open view of Figure 1A.
In Figure 1A and Figure 1B, 1 expression insulated substrate, 2 expression gate electrodes, 3 expression first insulation courses (gate insulating film); 4 expression active layers, 4a and 4b represent the etched facet of active layer, 501 and 502 expression contact layers; 601 expression source electrodes, 602 expression drain electrodes, 7 expressions, second insulation course.
The TFT element of embodiment 1 is a bottom gate type TFT element; Shown in Figure 1A and Figure 1B, first insulation course 3 that stacks gradually gate electrode 2 on the surface of insulated substrate 1, plays a role as gate insulating film, active layer 4 and contact layer 501,502, source electrode 601 and the drain electrode 602 of semiconductor layer.Observe from insulated substrate 1, for example range upon range of on source electrode 601 and drain electrode 602 have second insulation course 7.
The active layer 4 of semiconductor layer is the layer that when the TFT element conductive, forms channel region, for example is made up of polysilicon (poly-Si).Contact layer 501 is equivalent to source diffusion region and drain diffusion region respectively with contact layer 502, for example is made up of amorphous silicon (a-Si).
When this TFT element was N-channel MOS (below be called NMOS), active layer 4 for example was the lower p type of impurity concentration (p-type) semiconductor, and contact layer 501 for example is the higher n type of impurity concentration (n+ type) semiconductor with contact layer 502.
In the TFT of embodiment 1 element, contact layer 501,502, source electrode 601 and drain electrode 602 are formed directly on first insulation course 3 that is formed with active layer 4.Therefore, source electrode 601 has relative with the back side of the interface of the same gate insulating film (first insulation course 3) of active layer 4 first and relative with the etched facet 4a of active layer 4 second.Equally, drain electrode 602 has relative with the back side of the interface of the same gate insulating film (first insulation course 3) of active layer 4 first and relative with the etched facet 4b of active layer 4 second.
In the TFT of embodiment 1 element; The flat shape that projects to insulated substrate 1 of contact layer 501 and contact layer 502 is respectively and the roughly the same shape of flat shape that source electrode 601 and drain electrode 602 is projected to insulated substrate 1 also to extend to the outside in the zone that is formed with active layer 4.
That is, in the TFT of embodiment 1 element, between first of source electrode 601 and active layer 4 and the All Ranges between second and the active layer 4 all sandwiched contact layer 501.Equally, in the TFT of embodiment 1 element, between first of drain electrode 602 and active layer 4 and the All Ranges between second and the active layer 4 all sandwiched contact layer 502.
Fig. 2 A to Fig. 2 D is the schematic sectional view of an example of manufacturing approach that is used for the TFT element of illustrative embodiment 1.Fig. 2 A has just formed active layer schematic sectional view afterwards.Fig. 2 B has just formed second semiconductor film and conducting film schematic sectional view afterwards.Fig. 2 C is just to the schematic sectional view after the conducting film etching.Fig. 2 D is just to the schematic sectional view after the second semiconductor film etching.Fig. 2 A to Fig. 2 D is respectively the cut-open view that is equivalent to the A-A ' cross section of Figure 1A.
When forming the TFT element of embodiment 1, for example at first form gate electrode 2, then form first insulation course 3 with gate insulating film effect on the surface of insulated substrate 1.When the formation method of gate electrode 2 and employed material (conducting film) can be the manufacturing TFT element of selecting in the past in employed method and the material any.When equally, the formation method of first insulation course 3 and employed material (conducting film) can be the manufacturing TFT element of selecting in the past in employed method and the material any.
Then, for example shown in Fig. 2 A, on first insulation course 3, form the active layer 4 of island.Active layer 4 for example is to form like this: the whole surf zone at first insulation course 3 forms amorphous silicon film (first semiconductor film); After the part of this polysilicon film or Zone Full carried out multi-crystal silicification; This first semiconductor film is carried out etching, thereby form active layer 4.The side that is produced when certainly, in this manual etched facet 4a, 4b is meant and forms active layer 4 with said method.At the TFT element is NMOS; When making active layer 4 for p type (p-type), for example after the part of this polysilicon film or Zone Full are carried out multi-crystal silicification, can implanted dopant and make p type (p-type); Also can behind the amorphous silicon film that forms the p type, carry out multi-crystal silicification again.
Then, for example shown in Fig. 2 B, form second semiconductor film 5 and conducting film 6 at the whole surf zone of first insulation course 3 that is formed with active layer 4.Therefore, in the time of forming conducting film 6, the etched facet 4a of active layer 4,4b are covered by second semiconductor film 5.Second semiconductor film 5 is to form contact layer 501,502 employed semiconductor films.Therefore, when the TFT element is NMOS, for example forms the higher n type of impurity concentration (n+ type) amorphous silicon film and make second semiconductor film 5.Conducting film 6 is formation source electrode 601 and drain electrode 602 employed conducting films.When at this moment, the formation method of the formation method of second semiconductor film 5 and employed material, conducting film 6 and employed material can be the manufacturing TFT element of selecting in the past respectively in employed method and the material any.
Then, for example shown in Fig. 2 C, conducting film 6 is carried out etching, form source electrode 601 and drain electrode 602.
Then; For example shown in Fig. 2 D; If second semiconductor film 5 is carried out etching, then can obtain projecting to the roughly the same contact layer 501 of flat shape and the source electrode 601 of insulated substrate 1 and project to the roughly the same contact layer 502 of flat shape and drain electrode 602 of insulated substrate 1.If form second insulation course 7, then can obtain the TFT element of as Figure 1B shown in such cross-sectional configuration thereafter.
Fig. 3 A to Fig. 3 C is the schematic sectional view of action effect of the TFT element of the summary formation and the problem points that are used to explain bottom gate type TFT element in the past, embodiment 1.Fig. 3 A is a schematic sectional view of representing a formation example of bottom gate type TFT element in the past.The schematic sectional view of one example of the current direction when Fig. 3 B is the gate turn-on of the TFT element shown in the presentation graphs 3A.Fig. 3 C be the grid that is illustrated in the TFT element shown in Fig. 3 A by the time phenomenon that produced the schematic sectional view of an example.Fig. 3 A to Fig. 3 C is the flat shape of TFT element in the past A-A ' the line cut-open view during for shape shown in Figure 1A.
The cross-sectional configuration of bottom gate type TFT element in the past for example is a structure such shown in Fig. 3 A; Stack gradually active layer 4 and contact layer 501,502, source electrode 601 and the drain electrode 602 of gate electrode 2, first insulation course 3 (gate insulating film), semiconductor layer on the surface of insulated substrate 1, the TFT element with embodiment 1 is identical in this.
But in the manufacturing approach of in the past TFT element, range upon range of first semiconductor film and second semiconductor film 5 also carry out after the etching, form conducting film 6, and the source of formation electrode 601 and drain electrode 602.Therefore, in the time conducting film 6 will being formed, expose etched facet 4a, the 4b of active layer 4.Its result, second etched facet 4a with active layer 4 of source electrode 601 directly contacts, and second etched facet 4b with active layer 4 of drain electrode 602 directly contacts.
Shown in Fig. 3 A in the TFT element of such cross-sectional configuration, when the signal potential that for example puts on gate electrode 2 uprised, the TFT element conductive formed inversion layer (channel region) in gate electrode 2 one sides of leaning on of active layer 4.Therefore, shown in Fig. 3 B, interface one side active layer 4 and gate insulating film forms channel region 401.Its result, electrode 601 flows to drain electrode 602 through contact layer 501, channel region 401, contact layer 502 to electronics from the source, and electric current flows to source electrode 601 from drain electrode 602.
In contrast, if put on the signal potential step-down of gate electrode 2, the TFT element become by the time, the channel region 401 of active layer 4 disappears, and therefore between drain electrode 602 and source electrode 601, does not flow through electric current.
But, when active layer 4 for example is the low resistance semiconductor of polysilicon that kind, be the voltage that the TFT element is ended even put on the signal voltage of gate electrode 2, for example also can produce and flow through the such problem of leakage current to source electrode 601 from drain electrode 602.
For this leakage current; Result according to inventor's investigation finds; For example shown in Fig. 3 C; When the TFT element ended, gate electrode 2 one sides of leaning on of active layer 4 caused the hole and form doubtful channel region 401 ', will flow through the resistive leakage current in the hole of having passed through this doubtful channel region 401 '.
Promptly; The inventor finds; In bottom gate type TFT element in the past; Be formed with metal silicide film at the etched facet 4a of active layer 4 and the contact interface of source electrode 601 and the contact interface of etched facet 4b and drain electrode 602, the zone that is formed with this metal silicide film becomes the low resistance contact zone except contact layer 501,502.Therefore, be the voltage that the TFT element is ended even put on the signal voltage of gate electrode 2, have the resistive leakage current and flow through through doubtful channel region 401 ' caused hole.
And; The inventor finds; The method that flows through as the resistive leakage current that prevents above-mentioned that kind; As long as as the TFT element of embodiment 1, between second, sandwich contact layer 501,502 respectively and get final product between the etched facet 4a of active layer 4 and source electrode 601 second and at the etched facet 4b of active layer 4 and drain electrode 602.
If between second, sandwich contact layer 501,502 respectively, then eliminated the zone that is formed with metal silicide film (low resistance contact is regional) of TFT element that kind in the past between the etched facet 4a of active layer 4 and source electrode 601 second and at the etched facet 4b of active layer 4 and drain electrode 602.Therefore, even when the TFT element ends, form doubtful channel region 401 ',, thereby prevent that the resistive leakage current from flowing through through doubtful channel region 401 ' along the etched facet 4a of active layer, contact layer 501, the 502 meeting screen potentials that 4b extends.
The TFT element of embodiment 1 for example can be according to forming with reference to the illustrated order of Fig. 2 A to Fig. 2 D.That is, with the manufacturing approach of in the past TFT element relatively the time, for example,, also availablely make with the identical process number of TFT element in the past though changed the operation that forms active layer 4, the orders such as operation that form second semiconductor film 5.Therefore, can produce easily to active layer 4 use poly semiconductors and by the time prevent the TFT element that the resistive leakage current flows through.
Can know that to sum up in the time of will making the semiconductor devices of the TFT element with many active layers 4 use poly semiconductors, then formation has the TFT element of such structure shown in the embodiment 1, thereby prevent when the TFT element ends, to flow through the resistive leakage current.Can prevent the raising of manufacturing cost when making such semiconductor devices.
Fig. 4 A is the diagrammatic top view of first variation of the TFT element of expression embodiment 1.Fig. 4 B is the B-B ' cut-open view of Fig. 4 A.Fig. 5 is the diagrammatic top view of second variation of the TFT element of expression embodiment 1.
When the characteristic of the TFT of illustrative embodiment 1 element, in Figure 1A and Figure 1B, be example with the whole zone and the gate electrode 2 overlapping TFT elements of active layer 4.
But the present invention's (formation of embodiment 1) is not limited to shown in Figure 1A and Figure 1B such formation, for example can certainly be applicable to the TFT element of such shown in Fig. 4 A and Fig. 4 B, active layer 4 and this structure of gate electrode 2 crossings on different level.
In the vertical view of the TFT element shown in Fig. 4 A, source electrode 601 is overlapped with drain electrode 602 and gate electrode 2.
But; The present invention's (formation of embodiment 1) is not limited to shown in Fig. 4 A and Fig. 4 B such formation, can certainly be applicable to that kind as shown in Figure 5 for example, channel length TrL greater than the width G W of gate electrode 2 and source electrode 601 and drain electrode 602 not with the TFT element of gate electrode 2 overlapping this structures.
The present invention's (formation of embodiment 1) is not limited to the TFT element of the plane formation of Figure 1A, Fig. 4 A or that kind shown in Figure 5; As long as source electrode 601 and drain electrode 602 are the section constitutions that have towards the face of the etched facet of active layer 4, then go for the TFT element that any plane constitutes.
Fig. 6 is the diagrammatic top view of the 3rd variation of the TFT element of expression embodiment 1.Fig. 6 is the cut-open view that is equivalent to the B-B ' cross section of Fig. 4 A.
In TFT element in the past, the conducting film 6 that is used to form source electrode 601 and drain electrode 602 only is 1 layer of such conducting film of aluminium film for example mostly.
But, in the present invention's (formation of embodiment 1), in the time of forming conducting film 6, also can the different conducting film more than 2 kinds of range upon range of composition.That is, the TFT element of embodiment 1 can for example be a that kind shown in Figure 6, and source electrode 601 is made up of the duplexer of the first conducting film 6a and the second conducting film 6b respectively with drain electrode 602.Tungsten), when making the second conducting film 6b be the aluminium film at this moment, for example making the first conducting film 6a is that (Mo: molybdenum, W:, the first conducting film 6a and contact layer 501, the power of connecting airtight between 502 become big to the MoW film, can alleviate peeling off of source electrode 601 and drain electrode 602.
In example shown in Figure 6, be to be example, but be not limited thereto will form the different range upon range of two-layer structures of two kinds of conducting film 6a, 6b, can certainly be range upon range of three kinds or three kinds with the multi-ply construction of upper conductive film or use three-layer structure of two kinds of conducting films etc.
Fig. 7 A to Fig. 7 C is the synoptic diagram that the summary of the semiconductor devices (LCD panel) of the TFT element of expression with embodiment 1 constitutes.Fig. 7 A is the diagrammatic top view of the example that constitutes of the summary of expression LCD panel.Fig. 7 B is C-C ' the line cut-open view of Fig. 7 A.Fig. 7 C is the routine diagrammatic top view of a formation of the TFT substrate of presentation graphs 7A.
In Fig. 7 A to Fig. 7 C, 8 expression TFT substrates, 9 expression counter substrate; 10 expression liquid crystal materials, 11 expression seals, 12 expressions are polaroid down; 13 expression upper polarizers, DA representes the viewing area, GL representes scan signal line; DL presentation video signal wire, GD representes first driving circuit, DD representes second driving circuit.
For the present invention (formation of embodiment 1); In the semiconductor devices in the past so long as following such semiconductor devices; Promptly for example section constitution is constructed for the bottom grid in cross section shown in Fig. 3 A and is to have the semiconductor devices that active layer 4 adopts the TFT element of poly semiconductors; Regardless of its purposes, any semiconductor devices all can be used the present invention.That is, the formation of embodiment 1 is not only applicable to be integrated in the TFT element of IC chips such as CPU, semiconductor memory, is applicable to the TFT element on the TFT substrate that is formed on TFT liquid crystal indicator (plate) yet.
Shown in Fig. 7 A and Fig. 7 B, the TFT LCD panel for example is between TFT substrate 8 and counter substrate 9 these a pair of substrates, to enclose the display board that liquid crystal material 10 forms.At this moment, TFT substrate 8 is bondd by the seal of being located at the DA outside in viewing area with ring-type 11 with counter substrate 9, and liquid crystal material 10 is sealed in the space that is surrounded by TFT substrate 8, counter substrate 9 and seal 11.
When the TFT LCD panel for example is transmission-type or Semitransmissive display board, be provided with polaroid 12 down, be provided with upper polarizer 13 in the one side toward the outer side of counter substrate 9 in the one side toward the outer side of TFT substrate 8.Sometimes between TFT substrate 8 and the following polaroid 12, be respectively equipped with the phase difference film of 1 layer and even multilayer between counter substrate 9 and the upper polarizer 13.When the TFT LCD panel is the reflection-type display board, need not descend polaroid 12 usually.
Shown in Fig. 7 C, TFT substrate 8 for example has multi-strip scanning signal wire GL, multiple bar chart image signal line DL.At this moment, scan signal line GL and image signal line DL are across the insulation course setting.Viewing area DA for example is set to the set of pixel, and this pixel has the TFT element that plays the on-off element effect, and the pixel electrode that is connected with the source electrode or the drain electrode of TFT element.
Shown in Fig. 7 C, the display board that forms the first driving circuit GD and the second driving circuit DD outside the DA is for example arranged in the LCD panel in recent years in the viewing area of TFT substrate 8.The first driving circuit GD is used to carry out integrated circuit that the break-make of the sweep signal that puts on each scan signal line GL is controlled etc., the second driving circuit DD be used to carry out to the picture signal that puts on each image signal line generation, apply the integrated circuit that sequential is controlled etc.
When the LCD panel that adopts in the past; The first driving circuit GD is to use the shaped like chips IC that for example produces in the operation different with the TFT substrate with the second driving circuit DD more; But in the TFT substrate 8 shown in Fig. 7 C; Form the first driving circuit GD and the second driving circuit DD with scan signal line GL, image signal line DL, on-off element (TFT element) etc., and be built in the TFT substrate 8.
The first driving circuit GD and the second driving circuit DD are the circuit that is integrated with TFT element, resistive element, capacity cell etc.Compare with the TFT element (on-off element) that is disposed at the viewing area, the TFT element of the first driving circuit GD and the second driving circuit DD is worked very at high speed.Therefore, when the TFT element that makes the first driving circuit GD and the second driving circuit DD was bottom gate architectures, preferably for example active layer 4 used polysilicon, makes like formation Figure 1A and Figure 1B or the formation as Fig. 4 A and Fig. 4 B.
During for the illustrated bottom gate type TFT element of embodiment 1, be disposed at the also preferably same bottom gate type TFT element of TFT element (on-off element) of viewing area DA at the TFT element that makes the first driving circuit GD and the second driving circuit DD.
Fig. 8 A is the routine diagrammatic top view of a formation of a pixel of the viewing area in the expression TFT substrate.Fig. 8 B is the D-D ' cut-open view of Fig. 8 A.Fig. 8 C is the E-E ' cut-open view of Fig. 8 A.
Constituting of 1 pixel among the viewing area DA of TFT substrate 8 is various, but is the formation that has TFT element (on-off element) and be connected the pixel electrode on the source electrode of this TFT element basically.
When the TFT element of each pixel in the TFT substrate 8 was bottom gate type TFT element, the formation of 1 pixel for example had the formation shown in Fig. 8 A to Fig. 8 C.1 shared zone of pixel for example is equivalent to two adjacent scan signal line GLn, GLn+1, two adjacent image signal line DLm, DLm+1 institute area surrounded in the DA of viewing area.
At this moment, TFT element (on-off element) by on the surface of insulated substrate SUB such as glass substrate active layer SC and contact layer 501,502, source electrode SD1 and the drain electrode SD2 of range upon range of scan signal line GLn+ 1, first insulation course 3, semiconductor layer constitute.Scan signal line GLn+1 plays the effect of the gate electrode of TFT element.First insulation course 3 plays the effect of the gate insulating film of TFT element.
Drain electrode SD2 for example with two adjacent image signal line DLm, DLm+1 in an image signal line DLm be connected, under the situation that adopts common TFT substrate 8, drain electrode SD2 and image signal line DLm are integrally formed.Source electrode SD1 is connected with the pixel electrode PX that forms across second insulation course 7 through through hole TH.
Active layer SC for example can be formed by the poly semiconductor (for example polysilicon) identical with the TFT element of the first driving circuit GD, but also can be formed by amorphous semiconductors such as amorphous silicons.
So; As long as the TFT element (on-off element) of viewing area DA all is a bottom gate type TFT element with the formation of the TFT element of the first driving circuit GD and the second driving circuit DD; Then can in the operation of the TFT element that forms viewing area DA, form the TFT element of the first driving circuit GD and the second driving circuit DD simultaneously.
Form at the active layer 4 of the TFT element that forms the first driving circuit GD and the second driving circuit DD by polysilicon, by amorphous silicon under the situation of active layer SC of TFT element of viewing area DA; For example after the whole surf zone of first insulation course 3 forms amorphous silicon film; The amorphous silicon that only is used in the zone that forms the first driving circuit GD and the second driving circuit DD is that polysilicon gets final product; Therefore, can suppress to make the reduction of efficient and the rising of manufacturing cost.
Formation shown in Fig. 8 A to Fig. 8 C is the formation example with pixel of bottom gate type TFT element (on-off element), and the flat shape of the flat shape of TFT element, allocation position, pixel electrode PX etc. can certainly appropriate change.
In above-mentioned explanation; An example as semiconductor devices with TFT element that embodiment 1 constitutes; What enumerate is LCD panel (TFT substrate 8); But be not limited thereto, for example the TFT element of CPU, DRAM or shaped like chips semiconductor devices (conductor integrated circuit device) such as the employed drive IC of liquid crystal indicator in the past can certainly be suitable for the formation of embodiment 1.
Fig. 9 is the schematic sectional view of application examples of the TFT element of expression embodiment 1.Figure 10 is the schematic sectional view of an example that is used to explain the manufacturing approach of TFT element shown in Figure 9.Fig. 9 and Figure 10 are the cut-open views that is equivalent to B-B ' the line cross section of Fig. 4 A.
In order to prevent that the resistive leakage current flows through when the TFT of embodiment 1 element ends; Make between etched facet 4a and the source electrode 601 of the active layer 4 in this TFT element and sandwich contact layer 501, make between etched facet 4b and the drain electrode 602 of active layer 4 and sandwich contact layer 502.As an example of the manufacturing approach of the TFT element of such formation, the manufacturing approach according to order shown in Fig. 2 A to Fig. 2 D has been described.
But, as long as the TFT element of embodiment 1 is sandwiching contact layer 501, between the etched facet 4b of active layer 4 and drain electrode 602, is sandwiching contact layer 502 as above-mentioned between the etched facet 4a of active layer 4 and the source electrode 601.Therefore, as shown in Figure 9, the TFT element of embodiment 1 for example also can be that contact layer 501,502 only is formed on active layer 4 such cross-sectional configuration on every side.
When forming TFT element, for example shown in Fig. 2 A, the active layer 4 that uses polysilicon is formed island with cross-sectional configuration shown in Figure 9.Then, for example be formed for forming second semiconductor film 5 of contact layer 501,502, this second semiconductor film 5 is carried out etching, that kind shown in figure 10 forms the island semiconductor film 5 that covers each active layer 4 (etched facet 4a, 4b)., form conducting film 6, and carry out etching and form source electrode 601 and drain electrode 602, semiconductor film 5 is carried out etching and forms contact layer 501,502, so can form TFT element with cross-sectional configuration shown in Figure 9 thereafter.
Figure 11 is the routine schematic sectional view of a formation of the TFT element of the expression embodiment of the invention 2.Figure 11 is the cut-open view that is equivalent to the B-B ' cross section of Fig. 4 A.In Figure 11,1401,1402 expressions the 3rd insulation course.
In embodiment 2, based on TFT element with the illustrated formation of embodiment 1, to can be implemented in this TFT element by the time resistive leakage current that further reduces to be flow through the formation of TFT element describe
For example shown in figure 11; The illustrated TFT element of the basic comprising of the TFT element of embodiment 2 and embodiment 1 is identical, is sandwiching contact layer 501 between the etched facet 4a of the active layer 4 that uses polysilicon and the source electrode 601, between the etched facet 4b of active layer 4 and drain electrode 602, is sandwiching contact layer 502.
In the TFT of embodiment 2 element, between the etched facet 4a and source electrode 601 of active layer 4, except sandwiching contact layer 501, also accompany the 3rd insulation course 1401.At this moment, the 3rd insulation course 1401 for example is sandwiched between source electrode 601 and the contact layer 501, between first of source electrode 601 and active layer 4, also has part the 3rd insulation course 1401.Equally, between the etched facet 4b and drain electrode 602 of active layer 4, except sandwiching contact layer 502, also accompany the 3rd insulation course 1402.At this moment, the 3rd insulation course 1402 for example is sandwiched between drain electrode 602 and the contact layer 502, between first of drain electrode 602 and active layer 4, also has part the 3rd insulation course 1402.
If make formation like this, then compare with the TFT element of embodiment 1, this TFT element by the time, between the etched facet 4a of active layer 4 and the source electrode 601 and the etched facet 4b of active layer 4 and the raising of the insulation effect between the drain electrode 602.Therefore, prevent that the effect that when the TFT element ends, flows through the resistive leakage current from improving.
Figure 12 A to Figure 12 D is the schematic sectional view of an example of manufacturing approach that is used for the TFT element of illustrative embodiment 2.Figure 12 A has just formed second semiconductor film schematic sectional view afterwards.Figure 12 B has just formed the 3rd insulation course schematic sectional view afterwards.Figure 12 C has just formed source electrode and drain electrode schematic sectional view afterwards.Figure 12 D is just to the schematic sectional view after the second semiconductor film etching.Figure 12 A to Figure 12 D is respectively the cut-open view that is equivalent to B-B ' the line cross section of Fig. 4 A.
When forming the TFT element of embodiment 2, for example,, form the active layer 4 of gate electrode 2, first insulation course 3, island on the surface of insulated substrate 1 at first according to the illustrated order of embodiment 1.
Then, for example shown in Figure 12 A, form second semiconductor film 5 at the whole surf zone of first insulation course 3 that is formed with active layer 4.At this moment, the etched facet 4a of active layer 4,4b are covered by second semiconductor film 5.
Then, for example shown in Figure 12 B, form the 3rd insulation course 14 on the surface of second semiconductor film 5.The 3rd insulation course 14 for example is after the whole surface of second semiconductor film 5 has formed silicon oxide layer, to carry out etching and form; In the 3rd insulation course 14 and active layer 4 overlapping areas, be formed with the window that is connected (peristome) that is connected and guarantees drain electrode 602 and contact layer 502 that is used to guarantee source electrode 601 and contact layer 501.
Then; Form conducting film 6, this conducting film 6 is carried out etching and forms source electrode 601 and drain electrode 602, then; For example shown in Figure 12 C; The 3rd insulation course 14 is carried out etching, will except between the source electrode 601 and second semiconductor film 5 and the dielectric film the part between the drain electrode 602 and second semiconductor film 5 remove, form the 3rd insulation course 1401,1402.
Then, for example shown in Figure 12 D, second semiconductor film 5 is carried out etching, form contact layer 501,502., form second insulation course 7, then obtain having the TFT element of cross-sectional configuration shown in Figure 11 thereafter.
TFT element for embodiment 2, can certainly be, when forming the employed conducting film 6 of source electrode 601 and drain electrode 602, the two or more conducting film that for example range upon range of composition is different.
Omitted the explanation of object lesson at this, enumerated the TFT element of shaped like chips semiconductor devices such as the TFT element of the TFT substrate 8 of such LCD panel, CPU, DRAM etc. but the formation of the TFT element of embodiment 2 can certainly be applicable to 1 of embodiment.
Figure 13 A is the schematic sectional view of first variation of the TFT element of expression embodiment 2.Figure 13 B is the schematic sectional view of second variation of the TFT element of expression embodiment 2.Figure 13 C is the schematic sectional view of the 3rd variation of the TFT element of expression embodiment 2.Figure 13 A to Figure 13 C is respectively the cut-open view that is equivalent to the B-B ' cross section of Fig. 4 A.
The TFT element of embodiment 2 is through between the etched facet 4a and source electrode 601 of active layer 4, sandwich the 3rd insulation course 1401,1402 respectively between the etched facet 4b of active layer 4 and the drain electrode 602, thus prevent the TFT element by the time flow through the resistive leakage current.Therefore, shown in Figure 13 A, in the TFT of embodiment 2 element, for example can be between the etched facet 4a and source electrode 601 of active layer 4, do not sandwich the formation of contact layer 501,502 between the etched facet 4b of active layer 4 and the drain electrode 602 respectively.
During the TFT element wanting to constitute shown in the shop drawings 13A; For example; At first, according to the identical order of manufacturing approach of in the past TFT element, form continuously after the polysilicon semiconductor film (first semiconductor film) and second semiconductor film 5; Range upon range of second semiconductor film 5, and form the active layer 4 exposed etched facet 4a, 4b.Then; For example according to main points such shown in Figure 12 C; Forming the 3rd insulation course 14 with window (peristome) with active layer 4 overlapping areas, wherein this window (peristome) is used to guarantee being connected of source electrode 601 and contact layer 501 and guarantees being connected of drain electrode 602 and contact layer 502.Then, form source electrode 601 and drain electrode 602, dielectric film 14 is carried out etching and forms the 3rd insulation course 1401,1402.If form second insulation course 7, then obtain the TFT element of Figure 13 A shown in such cross-sectional configuration thereafter.
In addition, when forming the TFT element,, for example shown in Figure 13 B, use the contact layer 501,502 of amorphous silicon only to be formed on the active layer 4 in the moment that has formed source electrode 601 and drain electrode 602 according to said sequence.Therefore, if the 3rd insulation course 14 for example is the higher insulator of light transmission, then after having formed source electrode 601 and drain electrode 602, even the 3rd insulation course 14 is not carried out etching the 3rd insulation course 1401,1402 is separated and also be fine.At this moment, the section constitution of TFT element for example becomes formation such shown in Figure 13 B.
When forming the TFT element, as long as between the etched facet 4a and source electrode 601 of active layer 4, sandwich the 3rd insulation course 1401,1402 respectively between the etched facet 4b of active layer 4 and the drain electrode 602 according to said sequence.Therefore, in the time of forming the 3rd insulation course 14, for example can the 3rd insulation course be formed and cover each active layer 4 island of (with second semiconductor film 5) respectively.At this moment, the section constitution of TFT element for example becomes formation such shown in Figure 13 C.
Figure 14 is the routine schematic sectional view of a formation of the TFT element of the expression embodiment of the invention 3.Figure 14 is the cut-open view that is equivalent to the B-B ' cross section of Fig. 4 A.
In embodiment 3, based on the formation of the illustrated TFT element of embodiment 2, to can be implemented in this TFT element by the time resistive leakage current that further reduces to be flow through other formations of TFT element describe
For example shown in figure 14; The illustrated TFT element of the basic comprising of the TFT element of embodiment 3 and embodiment 2 is identical, is sandwiching the 3rd insulation course 1401 between the etched facet 4a of the active layer 4 that uses polysilicon and the source electrode 601, between the etched facet 4b of active layer 4 and drain electrode 602, is sandwiching the 3rd insulation course 1402.
Shown in figure 14; The difference of the TFT element of embodiment 3 and the TFT element of embodiment 2 is, place, interface back side active layer 4 and first insulation course 3 (gate insulating film), between between source electrode 601 and the active layer 4 and between drain electrode 602 and the active layer 4, contact layer 501,502 and the 3rd insulation course 1401, relation between 1402.
In the TFT of embodiment 3 element, between first of source electrode 601 and active layer 4, only there are zone of only getting involved contact layer 501 or the zone of only getting involved the 3rd insulation course 1401.Equally, between first of drain electrode 602 and active layer 4, just there are zone of only getting involved contact layer 502 or the zone of only getting involved the 3rd insulation course 1402.
TFT element for such formation; Also be as long as, can prevent when this TFT element ends, to flow through the resistive leakage current between the etched facet 4a and source electrode 601 of active layer 4, between the etched facet 4b of active layer 4 and drain electrode 602, sandwich the 3rd insulation course 1401,1402 respectively.
Figure 15 A and Figure 15 B are the schematic sectional views of an example of manufacturing approach of the TFT element of expression embodiment 3.Figure 15 A has just formed the 3rd insulation course schematic sectional view afterwards.Figure 15 B has just formed second semiconductor film schematic sectional view afterwards.Figure 15 A and Figure 15 B are respectively the cut-open views that is equivalent to the B-B ' cross section of Fig. 4 A.
When forming the TFT element of embodiment 3, for example,, form the active layer 4 of gate electrode 2, first insulation course 3, island on the surface of insulated substrate 1 at first according to the illustrated order of embodiment 1.
Then, for example shown in Figure 15 A, form the 3rd insulation course 14 on the surface of first insulation course that is formed with active layer 4.The 3rd insulation course 14 for example is after the whole surface of second semiconductor film 5 has formed silicon oxide layer, to carry out etching and form; In the 3rd insulation course 14 and active layer 4 overlapping areas, be formed with the window that is connected (peristome) that is connected and guarantees drain electrode 602 and contact layer 502 that is used to guarantee source electrode 601 and contact layer 501.
Then, for example shown in Figure 15 B, form second semiconductor film 5 at the peristome of the 3rd insulation course 14.
, though omitted diagram, form source electrode 601 and drain electrode 602, the 3rd insulation course 14 is carried out etching and forms the 3rd insulation course 1401,1402, second semiconductor film 5 is carried out etching and forms contact layer 501,502 thereafter., form second insulation course 7, then obtain having the TFT element of cross-sectional configuration shown in Figure 14 thereafter.
TFT element for embodiment 3, can certainly be, when forming the employed conducting film 6 of source electrode 601 and drain electrode 602, the two or more conducting film that for example range upon range of composition is different.
Omitted the explanation of object lesson at this, enumerated the TFT element of shaped like chips semiconductor devices such as the TFT element of the TFT substrate 8 of such LCD panel, CPU, DRAM etc. but the formation of the TFT element of embodiment 3 can certainly be applicable to 1 of embodiment.
Figure 16 A is the schematic sectional view of first variation of the TFT element of expression embodiment 3.Figure 16 B is the schematic sectional view of second variation of the TFT element of expression embodiment 3.Figure 16 A and Figure 16 B are respectively the cut-open views that is equivalent to the B-B ' cross section of Fig. 4 A.
When forming the TFT element according to said sequence, in the moment that has formed source electrode 601 and drain electrode 602, second semiconductor film 5 that is used to form contact layer 501,502 only is formed on the active layer 4.Therefore, if the 3rd insulation course 14 for example is the higher insulator of light transmission, then after having formed source electrode 601 and drain electrode 602, even the 3rd insulation course 14 is not carried out etching the 3rd insulation course 1401,1402 is separated and also be fine.At this moment, the section constitution of TFT element for example becomes formation such shown in Figure 16 A.
In the manufacturing approach of above-mentioned TFT element, in the time of forming the 3rd insulation course 14, for example on 1 active layer 4, form 1 peristome, formed after source electrode 601 and the drain electrode 602, second semiconductor film 5 is separated with contact layer 501,502.But, in the time will forming the 3rd insulation course 14, also can be the peristome and these two peristomes of peristome that are used to form contact layer 502 that for example on 1 active layer 4, is formed for forming contact layer 501, form second semiconductor film 5 at each peristome.At this moment, the section constitution of TFT element for example becomes formation such shown in Figure 16 B.
When forming the TFT element, for example after having formed source electrode 601 and drain electrode 602, can omit second semiconductor film 5 is carried out etching and operation that it is separated with contact layer 501,502 according to such method.
Though omitted diagram,, can certainly be that for example such shown in Figure 13 C, the 3rd insulation course 1401,1402 only is formed on the structure around the active layer 4 for the TFT element of embodiment 3 at this.
More than, based on the clear specifically the present invention of the foregoing description, but the invention is not restricted to the foregoing description, in the scope that does not break away from its main idea, certainly carry out various changes.
Claims (12)
1. a display device has insulated substrate and is formed at the TFT element on the above-mentioned insulated substrate,
Stacked gradually gate electrode, gate insulating film, semiconductor layer, insulation course, source electrode and drain electrode on the surface of above-mentioned insulated substrate,
Above-mentioned semiconductor layer has: the active layer that is made up of poly semiconductor; Respectively between between above-mentioned active layer and the above-mentioned source electrode and the contact layer between above-mentioned active layer and the above-mentioned drain electrode,
Above-mentioned contact layer is on the active layer that forms island through etching, to form amorphous silicon film to form,
On above-mentioned amorphous silicon film, form insulation course,
At the opening that is connected that is formed on the above-mentioned insulation course between above-mentioned source electrode and above-mentioned drain electrode and the above-mentioned contact layer,
On above-mentioned amorphous silicon film and above-mentioned insulation course, form conducting film,
Through above-mentioned amorphous silicon film of etching and above-mentioned conducting film, under above-mentioned source electrode and above-mentioned drain electrode, form above-mentioned contact layer and above-mentioned insulation course, and above-mentioned contact layer and above-mentioned insulation course are arranged at the side that forms the above-mentioned active layer of island through etching.
2. display device according to claim 1 is characterized in that:
Between above-mentioned source electrode and the above-mentioned active layer and the insulation course that forms between above-mentioned drain electrode and the above-mentioned active layer carry out etching after being to form silicon oxide layer on through whole surface and form at above-mentioned amorphous silicon film.
3. a display device has insulated substrate and is formed at the TFT element on the above-mentioned insulated substrate,
Stacked gradually gate electrode, gate insulating film, semiconductor layer, source electrode and drain electrode on the surface of above-mentioned insulated substrate,
Above-mentioned semiconductor layer has: the active layer that is made up of poly semiconductor; Respectively between between above-mentioned active layer and the above-mentioned source electrode and the contact layer between above-mentioned active layer and the above-mentioned drain electrode,
Above-mentioned contact layer is on the active layer that forms island through etching, to form amorphous silicon film to form,
On above-mentioned amorphous silicon film, form insulation course,
At the opening that is connected that is formed on the above-mentioned insulation course between above-mentioned source electrode and above-mentioned drain electrode and the above-mentioned contact layer,
On above-mentioned amorphous silicon film and above-mentioned insulation course, form conducting film,
Through above-mentioned amorphous silicon film of etching and above-mentioned conducting film, under above-mentioned source electrode and above-mentioned drain electrode, form above-mentioned contact layer and insulation course,
And above-mentioned contact layer and above-mentioned insulation course are arranged at the side that forms the above-mentioned active layer of island through etching,
Between above-mentioned active layer except that above-mentioned opening and the above-mentioned source electrode, have above-mentioned insulation course between source layer and the above-mentioned drain electrode.
4. display device according to claim 3 is characterized in that:
Overlook and observe above-mentioned insulated substrate, then
The profile of above-mentioned contact layer, above-mentioned source electrode and above-mentioned drain electrode is overlapping.
5. display device according to claim 3 is characterized in that:
Above-mentioned source electrode is a duplexer of forming different two or more conducting films with above-mentioned drain electrode.
6. display device according to claim 3 is characterized in that:
Above-mentioned insulated substrate has and a plurality ofly is configured to rectangular pixel electrode, and has the viewing area that the collection of pixels that comprises pixel electrodes forms.
7. display device according to claim 3 is characterized in that:
Above-mentioned TFT element is an on-off element.
8. display device according to claim 3 is characterized in that:
Above-mentioned insulated substrate has and a plurality ofly is configured to rectangular pixel electrode, and has the viewing area that the collection of pixels that comprises pixel electrodes forms, and on the exterior lateral area of this viewing area, disposes the driving circuit with TFT element.
9. display device according to claim 3 is characterized in that:
Above-mentioned insulated substrate has a plurality of rectangular on-off elements that are configured to, and the active layer of above-mentioned on-off element is made up of amorphous semiconductor.
10. the manufacturing approach of a display device comprises following operation:
First operation forms gate electrode on the surface of insulated substrate,
Second operation forms gate insulating film on above-mentioned gate electrode,
The 3rd operation forms poly semiconductor on above-mentioned gate insulating film, through the active layer of etching formation island,
The 4th operation forms kind or the different semiconductor film of concentration with the impurity of above-mentioned active layer on the active layer of above-mentioned island, at the side formation contact layer of the active layer of the island through etching formation,
The 5th operation forms insulation course and conducting film on above-mentioned semiconductor layer,
The 6th operation is carried out etching and is formed source electrode and drain electrode above-mentioned conducting film,
The 7th operation is carried out etching to above-mentioned semiconductor film and is formed respectively between between above-mentioned source electrode and the above-mentioned active layer and the contact layer between above-mentioned drain electrode and the above-mentioned active layer,
On above-mentioned insulation course, opening is set, and is connected to form the semiconductor film and the conducting film of contact layer.
11. method according to claim 10 is characterized in that:
After forming above-mentioned semiconductor film, form insulation course.
12. method according to claim 10 is characterized in that:
Above-mentioned the 3rd operation is at the formation amorphous semiconductor film and after with this amorphous semiconductor film polycrystallization, and it is carried out etching and forms above-mentioned active layer.
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| JP2007-149249 | 2007-06-05 | ||
| JP2007149249 | 2007-06-05 | ||
| JP2007149249A JP5303119B2 (en) | 2007-06-05 | 2007-06-05 | Semiconductor device |
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| EP (1) | EP2001046A3 (en) |
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Also Published As
| Publication number | Publication date |
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| TWI381529B (en) | 2013-01-01 |
| CN101320181A (en) | 2008-12-10 |
| EP2001046A3 (en) | 2011-01-05 |
| KR100973361B1 (en) | 2010-07-30 |
| KR20080107281A (en) | 2008-12-10 |
| US8049255B2 (en) | 2011-11-01 |
| US20080303030A1 (en) | 2008-12-11 |
| JP2008305843A (en) | 2008-12-18 |
| TW200915575A (en) | 2009-04-01 |
| JP5303119B2 (en) | 2013-10-02 |
| EP2001046A2 (en) | 2008-12-10 |
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