CN105572992A - Pixel structure, array substrate and manufacturing method for pixel structure - Google Patents

Abstract

The invention provides a pixel structure, an array substrate and a manufacturing method for the pixel structure. The pixel structure comprises a plurality of scanning lines arranged in parallel and insulated from one another, and a plurality of data lines arranged in parallel and insulated from one another, wherein the data lines are crossed with the scanning lines to define a plurality of pixels. Each pixel comprises a pixel electrode and a thin film transistor. The thin film transistor comprises double gates, a source and a drain, wherein the double gates include a first gate and a second gate. The first gates are at least partially overlapped with the data lines and electrically conducted with the scanning lines, part of the scanning lines serve as the second gates, the sources are electrically connected with the data lines, and the drains are electrically connected with the pixel electrodes.

Description

Dot structure, array base palte and pixel structure preparation method

Technical field

The present invention relates to and be a kind ofly applied to the dot structure of image display and there is the array base palte of this dot structure.

Background technology

Liquid crystal indicator has the advantages such as lightweight, little power consumption, radiation be low and easy to carry due to it and is widely used in modernization information equipment, as display, TV, mobile phone and digital product etc.

With regard to Thin Film Transistor-LCD (TFT-LCD), for a long time mainly with the main material of traditional amorphous silicon as TFT, nowadays separately there is a selection, namely use polysilicon replace amorphous silicon and likely become main flow.This is mainly conceived to be no matter the rate travel (mobility) in electronics or hole, and polysilicon all provides better rate travel than amorphous silicon.In addition, multi-crystal TFT also has an advantage to be that the driving circuit (comprising nmos pass transistor or PMOS transistor CMOS CMOS even) forming LCD can carry out with the manufacture of pixel panel simultaneously.Due to above-mentioned factor, use the liquid crystal display of polycrystalline silicon type TFT can provide better switching rate, more attractive.

Polycrystalline silicon type TFT is applicable to plurality of liquid crystals display, such as, in face switch type (In-planeSwitching, IPS) liquid crystal display, or multi-domain perpendicular alignment-type (Multi-domainVerticalAlignment, MVA) liquid crystal display etc.Wherein, in common MVA type liquid crystal display, the pixel electrode that dot structure comprises a TFT and is electrically connected with it.This pixel electrode district has multiple orientation region, and each orientation region has one group of orientation slit that alignment direction is identical each other respectively, effectively to control the arrangement of liquid crystal molecule.The alignment direction of the slit in different alignment region is different, can present different toppling directions by liquid crystal molecule corresponding to Shi Ge orientation district, and then reach the object of the wide viewing angle scope increasing liquid crystal display.

For adopting the MVA liquid crystal display of polycrystalline silicon type TFT, the bigrid of polycrystalline silicon type TFT can occupy more space, reduces the aperture opening ratio of liquid crystal display.Further, the configuration of polysilicon layer may affect the line of electric force between slit, makes the LCD alignment near polysilicon layer disorderly and causes picture to produce dark line.

Summary of the invention

In view of above content, be necessary the dot structure that a kind of polycrystalline silicon type liquid crystal display is provided, aperture opening ratio can be improved and avoid picture to produce dark line.

Further, a kind of array base palte comprising aforementioned dot structure is provided.

Further, a kind of method making aforementioned dot structure is provided.

A kind of dot structure, comprising:

Many the arranged in parallel and sweep traces of mutually insulated;

Many the arranged in parallel and data lines of mutually insulated, this plurality of data lines and this sweep trace intersect to limit multiple pixel, and each pixel comprises:

One pixel electrode, this pixel electrode is positioned at two adjacent sweep traces and adjacent two regions that data line is formed; And

One thin film transistor (TFT), this thin film transistor (TFT) comprises bigrid, source electrode and drain electrode, this bigrid comprises first grid and second grid, this first grid is at least partly overlapping with this data line and electrically conduct with this sweep trace, part of scanning line is as this second grid, this source electrode is electrically connected this data line, and this drain electrode is electrically connected this pixel electrode.

Further, a kind of array base palte comprising above-mentioned dot structure is provided.

As a method for making for aforementioned dot structure, this method for making comprises:

A first substrate is formed this bigrid, sweep trace and covers this two grid gate insulator;

This gate insulator is formed a polysilicon layer;

Adulterate this polysilicon layer form conductive impurity doping semiconductor layer;

Pattern conductive impurity doped semiconductor layer, with this double grid very mask, again to adulterate this conductive impurity doping semiconductor layer away from this two grid side from the first substrate, wherein, be not doped to conductor further by the conductive impurity doping semiconductor layer that this bigrid covers, be not doped by the conductive impurity doping semiconductor layer that this bigrid covers;

Form at least one insulation material layer, this insulation material layer of patterning also forms multiple opening thus forms interbedded insulating layer, and this semiconductor layer of part exposes from this opening, to forming this source electrode, data line and drain electrode by aperture position;

This pixel electrode is formed at this insulation material layer.

Compared to prior art, two grids forming gate channels in bigrid are overlapping with sweep trace and data line at least partly respectively, effectively reduce the display space that grid takies pixel electrode, effectively improve aperture opening ratio.By partial polysilicon layer correspondence is arranged between the first slot set of pixel electrode and the second slot set, this polysilicon layer can be avoided to cause the line of electric force of pixel electrode uneven thus cause picture to produce too much dark line.

Accompanying drawing explanation

Fig. 1 is the side structure schematic diagram of liquid crystal indicator in a preferred embodiment of the present invention.

Fig. 2 is the planar structure schematic diagram of dot structure in liquid crystal indicator shown in Fig. 1.

Fig. 3 is for array base palte shown in Fig. 2 is along the cross-sectional view of II-II line.

Fig. 4 is the method flow diagram of dot structure shown in construction drawing 1.

Main element symbol description

Liquid crystal indicator	100
		Array base palte	10
Liquid crystal layer	20
		Color membrane substrates	30
First substrate	101
		Cushion	102
Dot structure layer	103
		Second substrate	301
Chromatic filter layer	302
		Control element layer	303
Sweep trace	GL
		Data line	DL
Public electrode wire	CL
		Thin film transistor (TFT)	110
Pixel	111
		Pixel electrode	112
First direction	X
		Second direction	Y
First slot set	12A
		Second slot set	12B
Central electrode bar	12C
		Bigrid	14
First grid	141
		Second grid	142
Interlayer insulating film	15
		First contact hole	15A
Second contact hole	15B
		Source electrode	16
Drain electrode	17
		Semiconductor layer	18
Conductive impurity doping source region	18A
		First grid passage	18B
First conductive impurity doped region	18C
		Second grid passage	18D
Second conductive impurity doped region	18E
		Conductive impurity doped drain region	18F
Flatness layer	19
		3rd contact hole	19A
Step	S101~S106

Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.

Embodiment

Illustrate the present invention below in conjunction with accompanying drawing, the present invention relates to display device, this display device adopts thin film transistor (TFT) array to drive.For ease of follow-up explanation, be described for liquid crystal indicator.

Fig. 1 is the side structure schematic diagram of the liquid crystal indicator of better embodiment of the present invention.In present embodiment, this liquid crystal display is described for multi-domain perpendicular alignment-type (Multi-domainVerticalAlignment, MVA) liquid crystal display.

As shown in Figure 1, liquid crystal indicator 100 comprises array base palte 10, liquid crystal layer 20 and color membrane substrates 30, and wherein, liquid crystal layer 20 is located between array base palte 10 and color membrane substrates 30.

Further, array base palte 10 comprise be cascading the first substrate 101, cushion 102, dot structure layer 103.Wherein, dot structure layer 103 comprises the dot structure 11 be arranged in array.Color membrane substrates 30 comprises the second substrate 301 of stacked setting, chromatic filter layer 302 and control element layer 303 successively.Array base palte 10 and color membrane substrates 30 cooperatively interact and control the sense of rotation of liquid crystal molecule in liquid crystal layer 20, thus reach the function that liquid crystal indicator 100 carries out image display.

Refer to Fig. 2, it is the planar structure schematic diagram of dot structure layer 103 pixel structure in array base palte 10.

Dot structure 11 comprises: multi-strip scanning line GL, a plurality of data lines DL, many public electrode wire CL, thin film transistor (TFT) 110 and pixel electrodes 112.Parallel to each other and the mutually insulated of this multi-strip scanning line GL, and along first direction X(horizontal direction) extend.These many public electrode wire CL are parallel to each other, and almost parallel with this sweep trace GL, between two adjacent sweep trace GL.Parallel to each other and the mutually insulated of this plurality of data lines DL, and along second direction Y(vertical direction) extend, and intersect to limit many pixels 111 with this multi-strip scanning line GL.Each pixel 111 at least comprises thin film transistor (TFT) 110 and the pixel electrode be electrically connected with it 112.Wherein, this first direction X is mutually vertical with second direction Y.

This pixel electrode 112 comprises multiple slit, and this slit comprises the first slot set 12A and the second slot set 12B.Be a central electrode bar 12C between first slot set 12A of this pixel electrode 112 and the second slot set 12B, this central electrode bar 12C and this data line DL is almost parallel, and this first slot set 12A and the second slot set 12B is symmetrical with central electrode bar 12C.

First slot set 12A and the second slot set 12B also comprises the orientation district that two have different orientation angles.That is, this pixel electrode 112 comprises four orientation regions altogether, but is not limited thereto.The alignment direction of the slit in different alignment region is different, and liquid crystal molecule corresponding to each orientation region can be made to present different toppling directions, and then increases the wide viewing angle scope of liquid crystal display.

This thin film transistor (TFT) 110 comprises bigrid 14, source electrode 16, drain electrode 17 and semiconductor layer 18, forms a bottom gate type (BottomGate) thin film transistor (TFT).

This bigrid 14 comprises first grid 141 and second grid 142, and wherein, this first grid 141 is vertically connected at sweep trace GL in the region of proximity data line DL, and part is overlapping with this data line DL; Part of scanning line GL as this second grid 142, thus makes second grid 142 be parallel to sweep trace GL general direction completely, and certainly, first grid 141 and this sweep trace GL electrically conduct.

This source electrode 16 is positioned on data line DL, and is electrically connected this data line DL.This drain electrode 17 is electrically connected this pixel electrode 112, and this drain electrode simultaneously 17 and this public electrode wire CL partly overlap, with and public electrode wire CL between form a memory capacitance (sign).This semiconductor layer 18 is between this source electrode 16 and this drain electrode 17, overall in a L-type distribution.In the present embodiment, semiconductor layer 18 is low-temperature polysilicon silicon material layer.

Fig. 3 is the cross-sectional view of the dot structure 11 shown in Fig. 2 along II-II line.Please refer to Fig. 2-3, start to drain electrode 17 from source electrode 16, respectively corresponding source electrode 16, bigrid 14 and drain electrode 17, this semiconductor layer 18 comprises conductive impurity doping source region 18A, the first grid passage 18B of sequential, the first conductive impurity doped region 18C, second grid passage 18D, the second conductive impurity doped region 18E and conductive impurity doped drain region 18F.

Wherein, conductive impurity doping source region 18A, first grid passage 18B, the first conductive impurity doped region 18C, second grid passage 18D arrange along first direction X, second conductive impurity doped region 18E and conductive impurity doped drain region 18F along second direction Y arrangement, thus forms this L-type structure.Second conductive impurity doped region 18E corresponds to the central electrode bar 12C between the first slot set 12A and the second slot set 12B.In the present embodiment, the doping of this conductive impurity can be N-shaped doping or p-type doping.

This conductive impurity doping source region 18A is positioned at below this source electrode 16, and is electrically connected with this source electrode 16 by one first contact hole 15A.Similarly, this conductive impurity doped drain region 18F is positioned at below this drain electrode 17, is electrically connected, simultaneously by one second contact hole 15B with this drain electrode 17, drain electrode 17 is also electrically connected by one the 3rd contact hole 19A and pixel electrode 112, with to pixel electrode 112 transmitting display signal therefor.

Corresponding to first grid 141, this first grid passage 18B panel data line DL is also partly overlapping with data line DL, corresponding second grid 142, second grid passage 18D is all overlapping with sweep trace GL, the overlapping region of effective reduction bigrid 14 and pixel electrode 112, namely reduce the space that first grid passage 18B and second grid passage 18D takies viewing area, be the reserved larger display space of pixel 111, effectively improve the aperture opening ratio of pixel.

This first conductive impurity doped region 18C between first grid passage 18B and second grid passage 18D, to reduce the resistance between gate channels.

Second grid passage 18D and the second conductive impurity doped region 18E corresponds between the first slot set 12A and the second slot set 12B, i.e. the central electrode bar 12C of second grid passage 18D and the second conductive impurity doped region 18E respective pixel electrode.Utilizing is arranged between the first slot set 12A of pixel electrode 112 and the second slot set 12B by part of semiconductor layer 18 correspondence be made up of polysilicon, the line of electric force of the first slot set 12A and the second slot set 12B so can not be caused uneven, avoid Liquid Crystal Molecules Alignment disorderly and cause display frame to produce too much dark line.

This dot structure 11 is positioned at cushion 102 surface of the first substrate 101, respectively is bigrid 14, gate insulator 13, semiconductor layer 18, interlayer insulating film 15, source electrode 16, drain electrode 17, flatness layer 19 and pixel electrode 112 from bottom to top.

This cushion 102 is positioned at the surface of the first substrate 101, and this cushion 102 can comprise silicon nitride layer (B-SiNx) and silicon oxide layer (B-SiOx) double-layer structure.

First grid 141 in bigrid 14 is arranged on cushion 102 respectively with second grid 142.This gate insulator 13 is covered on this bigrid 14, and this gate insulator 13 can comprise silicon nitride layer and silicon oxide layer.This semiconductor layer 18 to be covered on this gate insulator 13 and between flatness layer 19 and gate insulator 13.

Usually, after this bigrid 14 of making, a dopping process will be carried out to the semiconductor layer 18 of polycrystalline silicon material, make the region do not covered by bigrid 14 form conductor, formed semiconductor by the region that bigrid 14 covers, and semiconductor both sides form lightly doped region (LDD).This LDD can reduce electric field intensity, can increase the fiduciary level of element simultaneously.Therefore, this first conductive impurity doped region 18C and the second conductive impurity doped region 18E, in the both sides near first grid passage 18B and second grid passage 18D, usually also comprises in LDD(figure and not indicating).

In addition, in the present embodiment, in semiconductor layer 18, first grid passage 18B is identical with particle concentration with the material of second grid passage 18D, and the material of conductive impurity doping source region 18A, the first conductive impurity doped region 18C, the second conductive impurity doped region 18E and conductive impurity doped drain region 18F is identical with particle concentration.

This interlayer insulating film 15 is positioned on semiconductor layer 18, can comprise silicon nitride layer and silicon oxide layer is two-layer.This interlayer insulating film 15 has the first contact hole 15A and the second contact hole 15B, expose conductive impurity doping source region 18A and the conductive impurity doped drain region 18F of polycrystalline silicon material respectively, make the source electrode 16 of follow-up formation and drain electrode 17 be connected with semiconductor layer 18 respectively by the first contact hole 15A and the second contact hole 15B and electrically conduct.

This flatness layer 19 covers this source electrode 16, drain electrode 17 and interlayer insulating film 15, and comprises the 3rd contact hole 19A, with exposed portion drain electrode 17.This flatness layer 19 can be organic material layer.This pixel electrode 112 is positioned at above this flatness layer 19, and is contacted by the 3rd contact hole 19A with drain electrode 17 and electrically conduct.

Compared to prior art, first grid 141 part forming gate channels in bigrid 14 is overlapping with data line DL, and part of scanning line GL is as second grid 142, then it is basic parallel with sweep trace GL, effective reduction bigrid 14 takies the display space of pixel electrode 112, effectively improves aperture opening ratio.

Further, by part of semiconductor layer 18 correspondence is arranged between the first slot set 12A of pixel electrode 112 and the second slot set 12B, the semiconductor layer 18 of low-temperature polysilicon silicon materials can be avoided to cause the line of electric force of pixel electrode 112 uneven thus cause picture to produce too much dark line.

Refer to Fig. 4, it is the schematic flow sheet of pixel structure preparation method as Figure 2-3.

Step S101, provides one first substrate 101, this first substrate 101 is formed this bigrid 14, sweep trace GL and covers the gate insulator 13 of this bigrid 14.

Step S102, this gate insulator 13 forms a polysilicon material layer.

Step S103, adulterate this polysilicon layer form conductive impurity doping semiconductor layer.

Step S104, pattern conductive impurity doped semiconductor layer, with this bigrid 14 for mask, again to adulterate this conductive impurity doping semiconductor layer away from the side of this bigrid 14 from the first substrate 101, wherein, be not doped to conductor further by the conductive impurity doping semiconductor layer that this bigrid covers, be not doped by the conductive impurity doping semiconductor layer that this bigrid covers, thus form semiconductor layer 18.Thus corresponding formation conductive impurity doping source region 18A, a first grid passage 18B, one first conductive impurity doped region 18C, a second grid passage 18D, one second conductive impurity doped region 18E and a conductive impurity doped drain region 18F.

Step S105, forms at least one insulation material layer, and this insulation material layer of patterning also forms multiple opening thus interlayer insulating film 15.In this enforcement, the plurality of opening comprises the first contact hole 15A and the second contact hole 15B part, and semiconductor layer 18 exposes from this opening, to should aperture position be formed this source electrode 16, data line DL and drain electrode 17.

Step S106, forms this pixel electrode 112 at this interlayer insulating film 15.

Visible, in bottom gate type (bottomGate) the thin film transistor (TFT) manufacturing process of low temperature polycrystalline silicon, by utilize bigrid 14 as mask from the first substrate 101 dorsad doped polysilicon layer formed semiconductor layer 18, effectively reduce process and the complexity of making, improve make efficiency.

Certainly, the present invention is not limited to above-mentioned disclosed embodiment, and the present invention carries out various change to above-described embodiment.As long as the art personnel are appreciated that in spirit of the present invention, the suitable change do above embodiment and change all drop in the scope of protection of present invention.

Claims (14)

1. a dot structure, comprising:

Many the arranged in parallel and sweep traces of mutually insulated;

Many the arranged in parallel and data lines of mutually insulated, this plurality of data lines and this sweep trace intersect to limit multiple pixel, and each pixel comprises:

One pixel electrode, this pixel electrode is positioned at two adjacent sweep traces and adjacent two regions that data line is formed; And

One thin film transistor (TFT), this thin film transistor (TFT) comprises bigrid, source electrode and drain electrode, this bigrid comprises first grid and second grid, it is characterized in that, this first grid is at least partly overlapping with this data line and electrically conduct with this sweep trace, part of scanning line is as this second grid, and this source electrode is electrically connected this data line, and this drain electrode is electrically connected this pixel electrode.

2. dot structure as claimed in claim 1, it is characterized in that, this second grid is all overlapping with this sweep trace.

3. dot structure as claimed in claim 1, it is characterized in that, this thin film transistor (TFT) also comprises semi-conductor layer, this semiconductor layer this bigrid and source electrode, drain between, and form first grid passage in the region of corresponding first grid, form second grid passage in the region of corresponding second grid.

4. dot structure as claimed in claim 3, it is characterized in that, this semiconductor layer comprises a conductive impurity doping source region of sequential, this first grid passage, one first conductive impurity doped region, this second grid passage, one second conductive impurity doped region and a conductive impurity doped drain region.

5. dot structure as claimed in claim 4, it is characterized in that, this pixel electrode comprises multiple slit, this slit comprises the first symmetrical slot set and the second slot set, this semiconductor layer is L-type from this second grid passage to the second conductive impurity doped region entirety, and the 3rd conductive impurity doped region corresponds between the first slot set and the second slot set.

6. dot structure as claimed in claim 5, it is characterized in that, this semiconductor layer is that low-temperature polysilicon silicon materials are made.

7. as dot structure that claim 5 is somebody's turn to do, it is characterized in that, this dot structure also comprises public electrode wire, this public electrode wire is between adjacent two these sweep traces and be parallel to this sweep trace, this drain electrode and this public electrode wire partly overlap, this drain electrode heavily doped drain region is electrically connected with this drain electrode by one second contact hole, and is electrically connected with this pixel electrode by one the 3rd contact hole.

8. dot structure as claimed in claim 5, it is characterized in that, the 3rd conductive impurity doped region is continuous print semiconductor layer.

9. as the dot structure that claim 1 is somebody's turn to do, it is characterized in that, this source electrode is right against this data line, and this conductive impurity heavy-doped source polar region is electrically connected with this source electrode by one first contact hole.

10. as dot structure that claim 5 is somebody's turn to do, it is characterized in that, have a central electrode bar between first slot set of this pixel electrode and the second slot set, this central electrode bar is parallel with this data line, and this first slot set and the second slot set symmetrical centered by central electrode bar.

11. dot structures as claimed in claim 5, wherein, this dot structure also comprises a gate insulator, and this gate insulator is between this semiconductor layer and this bigrid.

12. dot structures be somebody's turn to do as claim 11, is characterized in that, this dot structure also comprises interbedded insulating layer, and this interlayer insulating film is positioned at this semiconductor layer upper surface, and comprise multiple contact holes exposing and go out part of semiconductor layer.

13. 1 kinds of array base paltes, comprise the first substrate, cushion and the dot structure as described in claim 3-12 any one that set gradually, and this bigrid are arranged at this buffer-layer surface.

The method for making of 14. 1 kinds of dot structures as described in claim 1-12 any one, is characterized in that, this method for making comprises:

A first substrate is formed this bigrid, sweep trace and covers this two grid gate insulator;

This gate insulator is formed a polysilicon layer;

Adulterate this polysilicon layer form conductive impurity doping semiconductor layer;

Pattern conductive impurity doped semiconductor layer, with this double grid very mask, again to adulterate this conductive impurity doping semiconductor layer away from this two grid side from the first substrate, wherein, be not doped to conductor further by the conductive impurity doping semiconductor layer that this bigrid covers, be not doped by the conductive impurity doping semiconductor layer that this bigrid covers;

Form at least one insulation material layer, this insulation material layer of patterning also forms multiple opening thus forms interbedded insulating layer, and this semiconductor layer of part exposes from this opening, to forming this source electrode, data line and drain electrode by aperture position;

This interlayer insulating film is formed this pixel electrode.