CN106405963A - Array substrate and display panel comprising same - Google Patents
Array substrate and display panel comprising same Download PDFInfo
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- CN106405963A CN106405963A CN201610933209.2A CN201610933209A CN106405963A CN 106405963 A CN106405963 A CN 106405963A CN 201610933209 A CN201610933209 A CN 201610933209A CN 106405963 A CN106405963 A CN 106405963A
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- array base
- base palte
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the invention discloses an array substrate and a display panel. The array substrate comprises a first substrate, a plurality of data lines, a plurality of scanning lines, a plurality of pixel electrodes and thin film transistors, wherein the plurality of data lines and the plurality of scanning lines are located on a first side of the first substrate, are insulated from each other, and are crossed; a plurality of sub pixels are defined by the plurality of data lines and the plurality of scanning lines; the plurality of pixel electrodes are located on the first side of the first substrate; the thin film transistors in one-to-one correspondence to the sub pixels are located on the first side of the first substrate; each thin film transistor comprises a grid, a source, a drain and an active layer; projections of the drains on the first substrate is at least partially overlapped with projections of the scanning lines on the first substrate; through a manner of moving the drains of the thin film transistors to the directions of the scanning lines and enabling the drains and the scanning lines to be at least partially overlapped, the area of the thin film transistor in each sub pixel is reduced; the aperture ratio of each sub pixel is increased, so that the aperture ratio of the array substrate and the aperture ratio of the display panel comprising the array substrate are increased.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of array base palte and the display surface including this array base palte
Plate.
Background technology
With the development of Display Technique, the resolution more and more higher of display floater, the sub-pixel including under equal area
Quantity gets more and more, and during work, each sub-pixel is required for a corresponding thin film transistor (TFT) and controls its display, therefore,
In each sub-pixel, the area shared by thin film transistor (TFT) drastically influence the aperture opening ratio of display floater.
Content of the invention
For solving above-mentioned technical problem, embodiments provide a kind of array base palte and include the aobvious of this array base palte
Show panel, to improve the aperture opening ratio of described display floater.
For solving the above problems, embodiments provide following technical scheme：
A kind of array base palte, including：
First substrate；
Positioned at described first substrate the first side mutually insulated and a plurality of data lines arranged in a crossed manner and multi-strip scanning line, described
A plurality of data lines and described multi-strip scanning line limit multiple sub-pixels；
Multiple pixel electrodes positioned at described first substrate first side；
Positioned at the one-to-one thin film transistor (TFT) with described sub-pixel of described first substrate first side, described film crystal
Pipe includes grid, source electrode, drain electrode and active layer, and wherein, described source electrode is electrically connected with described data wire, described grid with described
Scan line electrically connects, and described drain electrode is electrically connected with described pixel electrode；
Wherein, described drain electrode is in the projection on described first substrate and projection on described first substrate for the described scan line
At least partly overlap.
A kind of display floater, the second substrate be oppositely arranged including above-mentioned array base palte and with described array base palte.
Compared with prior art, in the array base palte that the embodiment of the present invention is provided, the drain electrode of described thin film transistor (TFT) exists
Projection on described first substrate and projection on described first substrate for the described scan line at least partly overlap so that described leakage
Pole is at least partly overlapped with described scan line, reduces the area shared by thin film transistor (TFT) in each sub-pixel, improves each sub-pixel
Aperture opening ratio, and then the aperture opening ratio improving this array base palte and including the display floater of this array base palte.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, acceptable
Other accompanying drawings are obtained according to these accompanying drawings.
The structural representation of the array base palte that Fig. 1 is provided by one embodiment of the invention；
Fig. 2 is the sectional view in array base palte shown in Fig. 1, at thin film transistor (TFT)；
Fig. 3 is the partial top view of a sub-pixel in array base palte shown in Fig. 1；
Sectional view in the array base palte that Fig. 4 is provided by another embodiment of the present invention, at thin film transistor (TFT)；
Sectional view in the array base palte that Fig. 5 is provided by another embodiment of the present invention, at thin film transistor (TFT)；
Fig. 6 shows the structural representation of the display floater that one embodiment of the invention is provided.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation description is it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of protection of the invention.
Elaborate a lot of details in the following description in order to fully understand the present invention, but the present invention is acceptable
To be implemented different from alternate manner described here using other, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
As depicted in figs. 1 and 2, the structural representation of the array base palte that Fig. 1 is provided by one embodiment of the invention, Fig. 2
Sectional view in array base palte shown in Fig. 1, at thin film transistor (TFT).In embodiments of the present invention, array base palte includes：
First substrate 10；
Positioned at first substrate 10 first side mutually insulated and a plurality of data lines 20 arranged in a crossed manner and multi-strip scanning line 30, many
Data line 20 and multi-strip scanning line 30 limit multiple sub-pixels 40；
Multiple pixel electrodes 50 positioned at first substrate 10 first side；
Positioned at the one-to-one thin film transistor (TFT) 60 with sub-pixel 40 of first substrate 10 first side, thin film transistor (TFT) 60 wraps
Include：Grid g, source electrode s, drain electrode d and active layer 61, wherein, active layer 61 includes：The source region electrically connecting with source electrode s, with drain electrode
The drain region of electrical connection, and it is located at the channel region between source region and drain region；Source electrode s is electrically connected with data wire 20, grid g and scanning
Line 30 electrically connects, and drain electrode d is electrically connected with pixel electrode 50.
It should be noted that in embodiments of the present invention, grid is located at same layer with scan line, but scan line is in space bit
Put and do not include grid, grid is divided into a part for thin film transistor (TFT).
As shown in figure 3, Fig. 3 is the partial top view of a sub-pixel in array base palte shown in Fig. 1, in the present embodiment,
In the projection on first substrate 10, the projection on first substrate 10 at least partly overlaps drain electrode d with scan line 30.Specifically, scheme
3 show a kind of thin film transistor (TFT) of low temperature polycrystalline silicon, and its active layer 61 is U-shaped raceway groove, and thin film transistor (TFT) is tied for top gate type
Structure, i.e. the more structure of low-temperature polysilicon film transistor application.In the present embodiment, by setting drain electrode d with scan line 30
It is set to and partly overlaps, reduce the area occupied ratio of alternatively non-transparent district in each sub-pixel, leave bigger sky to pixel electrode 50
Between such that it is able to improve sub-pixel aperture opening ratio.It should be noted that for convenience of explanation, Fig. 3 illustrates common U-shaped
The top-gated low-temperature polycrystalline silicon thin film transistor structure of raceway groove, but the embodiment of the present invention is not limited to this, implements other
In example, thin film transistor (TFT) can also be in top gate structure, U-shaped bottom grating structure and L-type bottom grating structure of L-type raceway groove etc.
Kind.
Optionally, in embodiments of the present invention, drain electrode projection on the first substrate and scan line be on the first substrate
Projection at least partly overlaps and is：The position of scanning constant line is constant (to be scanned in the array base palte that i.e. embodiment of the present invention is provided
The position of line is identical with the position of scan line in existing array base palte), by arranging the position of drain electrode in thin film transistor (TFT), will be thin
The drain electrode of film transistor is close to the scan-line direction electrically connecting with the grid of this thin film transistor (TFT), thus brilliant by reducing thin film
The area occupied of body pipe, increases the aperture opening ratio of each sub-pixel, thus increasing the aperture opening ratio of array base palte.
Optionally, on the basis of above-described embodiment, in one particular embodiment of the present invention, the leakage of thin film transistor (TFT)
Pole being projected on the first substrate is completely covered sweeping of electrically connecting with this thin film transistor (TFT) on scan line bearing of trend
Retouch line projection on the first substrate, with the maximum aperture opening ratio improving each sub-pixel.But the present invention does not limit to this
Fixed, specifically depend on the circumstances.
Continue as shown in Fig. 2, in embodiments of the present invention, array base palte also includes：Positioned at first substrate 10 first side with
The public electrode 80 that pixel electrode 50 mutually insulate.During specific works, scan conducting and the cut-off of line traffic control thin film transistor (TFT), thin
During film transistor conducting, the signal on data wire transmits to pixel electrode through thin film transistor (TFT), in pixel electrode and public electrode
Between formed control electric field, control each sub-pixel display.
Optionally, in one particular embodiment of the present invention, public electrode 80 is located at pixel electrode 50 towards the first base
Plate 10 side, in embodiments of the present invention, grid g is mutually insulated by gate insulation layer 91 with active layer 61, and it is exhausted that drain electrode d passes through interlayer
Edge layer 92 is insulated with grid g phase, and drain electrode d is mutually insulated with public electrode 80 by planarization layer 93, and public electrode 80 passes through passivation
Layer 94 is mutually insulated with pixel electrode 50.It is provided with the first sub- via in passivation layer 94, in planarization layer 93, be provided with the second sub- mistake
Hole, the first sub- via is connected with the second sub- via and constitutes the first via 71, and drain electrode d and pixel electrode 50 pass through the first via 71
Electrical connection.It should be noted that in embodiments of the present invention, drain electrode d may be located at same layer it is also possible to be located at active layer 61
Different layers, the present invention does not limit to this, and when drain d and active layer 61 are located at different layers, optionally, drain electrode d passes through the
Two vias 72 are electrically connected with active layer 61.
Optionally, in embodiments of the present invention, source electrode s and data line bit be in same layer, and is located at same layer with drain electrode d,
Wherein, source electrode s is electrically connected by the 3rd via 73 with active layer 61.
On the basis of above-described embodiment, in one embodiment of the invention, the second via throwing on the first substrate
The projection on the first substrate of shadow and scan line at least partly overlaps so that drain electrode to its corresponding scan line is close when
Wait, with this drain electrode electrical connection the second via also together with close to its corresponding scan line, to reduce the first via in the first base
Projection on plate and the overlapping area of the second via projection on the first substrate, thus avoid institute in the first via forming process
The photoresist using enters the region that the second via is located, and leads to the phenomenon that photoetching glue residua increases.Optionally, the second via exists
It is projected in, on first substrate, the throwing corresponding scan line being completely covered on scan-line direction on the first substrate
Shadow, projection on the first substrate does not overlap the projection on the first substrate of the first via with the second via, and the present invention is to this simultaneously
Do not limit, specifically depend on the circumstances.
It should be noted that on the basis of above-described embodiment, in one particular embodiment of the present invention, drain electrode is the
Projection on one substrate is completely covered the first via and projects on the first substrate, increases the first via and drain electrode with maximum
Contact area, reduce pixel electrode and drain electrode between resistance.
Although also, it should be noted when drain electrode projection on the first substrate and scan line projection on the first substrate
When at least partly overlapping, in first substrate surface direction, at drain electrode and the overlapping area of scan line, parasitism can be produced
Electric capacity, thus in the time of the conducting of each thin film transistor (TFT) and cut-off, producing feed-trough voltage, affects the display of each sub-pixel.However,
Study through inventor and find, in the present invention, scan line display impact on sub-pixel overlapping with drain electrode is very faint.
As shown in table 1, table 1 shows in the top-gated low-temperature polycrystalline silicon thin film transistor structure of same U-shaped raceway groove, its drain electrode
When at least partly overlapping and do not overlap with scan line, the signal voltage on data wire that its source electrode electrically connects, its drain electrode electrical connection
Pixel electrode on signal voltage, and the emulation data of its charge rate.
It should be noted that described data signal driving voltage is described data wire exporting to the drive of described thin film transistor (TFT)
Galvanic electricity pressure, due to during concrete emulation it is impossible to accomplish completely the same, therefore slightly deviation；Described pixel electrode voltage is this thin film
Voltage on the corresponding pixel electrode of transistor, charge rate is the ratio of pixel electrode voltage and data signal driving voltage.From
Table 1 is as can be seen that compared to the array base palte draining with scan line no overlap, in array base palte provided by the present invention, scan
When line is at least partly overlapped with drain electrode, charge rate does not substantially reduce, i.e. scan line and drain electrode at least partly overlaps antithetical phrase picture
The pixel voltage impact of element is less, thus affect less on the display of sub-pixel.
Specifically, the moment opening and closing in thin film transistor (TFT), the change of scanning line voltage can be via parasitic capacitance Cgs,
Have influence on the voltage of pixel electrode.When on display floater, often the scanning line driving of row image is opened, thin-film transistor gate
Voltage is by VglRise to Vgh, a feed-trough voltage (feed though voltage) upwards can be produced on pixel electrode, no
Cross because now scan line is opened, the signal on data wire can start to charge up to pixel electrode, therefore, even if at the beginning because
Impact for feed-trough voltage is not so that the voltage on pixel electrode is right, but the signal on final data line still can be by pixel electrode
On voltage be charged to normal voltage so as to the impact that picture is shown is little.
But, in thin film transistor (TFT) shutdown moment, the voltage of thin-film transistor gate can be by VghIt is down to Vgl, due to data
Signal on line is no longer charged to the voltage on pixel electrode, so voltage drop when scan line is closed, Jiu Huijing
By parasitic capacitance CgsHave influence on the voltage on pixel electrode so that the voltage on pixel electrode has the voltage pressure of a feed-trough voltage
Fall, thus have influence on the correctness that picture shows.So generally speaking, the active voltage on pixel electrode can be than on data wire
Signal voltage is low, and the voltage reducing just is produced on pixel electrode via parasitic capacitance Cgs by scan line change in voltage
Raw feed-trough voltage.Wherein, the computing formula of feed-trough voltage is：
Vfeedthough=(Vgh-Vgl)*Cgs/(Clc+Cst+Cgs)
=(Vgh-Vgl)/(Clc/Cgs+Cst/Cgs+1).
As can be seen here, on pixel electrode produced feed-trough voltage with drain electrode (or pixel electrode) and scan line between
The increase of parasitic capacitance and increase, with (Vgh-Vgl) increase and increase.Again because often row sub-pixel corresponds in display floater
Same scan line, and scan line has certain resistive performance in itself, therefore, when thin film transistor (TFT) turns off, along scan line
Bearing of trend, the corresponding (V of each sub-pixelgh-Vgl) be gradually reduced.
Be additionally, since scan line in signal transmission direction, the delay of diverse location different so that corresponding film crystal
(the V of pipegh-Vgl) also variant, finally result in feed-trough voltage also different.Wherein very fast, its feed-trough voltage is closed at scan line top
Maximum.
Therefore, in order to reduce the difference of scan line feed-trough voltage in signal transmission direction so that each thin film transistor (TFT) pair
The feed-trough voltage on pixel electrode answered is identical, improves the uniformity of display floater display picture, reduces this array base further
Impact to display picture when drain electrode and scan line at least partly overlap in plate.On the basis of any of the above-described embodiment, at this
In one embodiment of invention, the multiple sub-pixels electrically connecting with same scan line include the biography of the drive signal along along scan line
The first sub-pixel and the second sub-pixel arranged successively in defeated direction, wherein, the corresponding drain electrode of the first sub-pixel is on the first substrate
Projection projection on the first substrate with scan line overlapping area be less than the second sub-pixel corresponding drain electrode in first substrate
On projection and scan line projection on the first substrate overlapping area.Optionally, in the transmission direction of scanning-line signal,
The closer to scan line top (one end that i.e. signal is first sent to), drain less with the overlapping area of scan line.
Optionally, in the multiple sub-pixels electrically connecting with same scan line, the transmission direction of drive signal along along scan line,
Drain electrode in each thin film transistor (TFT) on the first substrate projection with this scan line projection overlapping area on the first substrate by
Decrescence little.But the present invention does not limit to this, specifically depend on the circumstances.
As shown in figure 4, Fig. 4 shows in the array base palte that another embodiment of the present invention is provided, at thin film transistor (TFT)
Sectional view, in embodiments of the present invention, thin film transistor (TFT) be top gate structure, that is, in this thin film transistor (TFT), grid g be located at have
Active layer 61 deviates from the side of first substrate 10, insulate with active layer 61.
It should be noted that due to when grid g deviates from first substrate 10 side positioned at active layer 61, in external environment
When light passes through the channel region of first substrate 10 directive active layer 61, the performance of thin film transistor (TFT) can be affected, therefore, in the present invention
An alternative embodiment in, array base palte also includes：Light shield layer 95 between first substrate 10 and active layer 61, shading
Layer 95 has lap in the projection on first substrate 10 and projection on first substrate 10 for the active layer 61, to utilize shading
Layer 95 blocks the light of directive active layer 61 in external environment.Especially, when active layer is for low temperature polycrystalline silicon, because low temperature is many
The electrical properties of crystal silicon are big compared with non-crystalline silicon by illumination effect, and therefore, the setting of light shield layer 95 is more important.
As shown in figure 5, Fig. 5 shows in the array base palte that another embodiment of the present invention is provided, at thin film transistor (TFT)
Sectional view, in embodiments of the present invention, thin film transistor (TFT) be bottom grating structure, that is, grid g be located at active layer 61 towards the first base
The side of plate 10, the present invention does not limit to this, specifically depends on the circumstances.
Continue as shown in figure 4, in one embodiment of the invention, grid is double-gate structure, including positioned at same layer and
The first grid being set up in parallel and second grid, first grid and second grid are electrically connected with same scan line；But the present invention
This is not limited, in other embodiments of the invention, grid can also be single grid structure, as shown in figure 5, specifically regarding feelings
Depending on condition.
As shown in fig. 6, Fig. 6 shows the structural representation of the display floater that one embodiment of the invention is provided, at this
In inventive embodiments, display floater includes：The array base palte 100 that any of the above-described embodiment is provided is relative with array base palte 100
The second substrate of setting.Optionally, in one embodiment of the invention, display floater is display panels, in the present invention
In embodiment, display floater also includes the liquid crystal layer 300 between array base palte 100 and second substrate 200, but the present invention couple
This does not limit, and specifically depends on the circumstances.
In sum, the embodiment of the present invention is provided array base palte and include this array base palte display floater in, thin
Projection on the first substrate at least partly overlaps with scan line for the drain electrode of film transistor projection on the first substrate, thus logical
Cross and move the drain electrode of thin film transistor (TFT) so that the mode at least partly overlapping with scan line that drains to scan-line direction, reduce
Area shared by thin film transistor (TFT) in each sub-pixel, improves the aperture opening ratio of each sub-pixel, and then improves this array base palte and inclusion
The aperture opening ratio of the display floater of this array base palte.
In this specification, various pieces are described by the way of going forward one by one, and what each some importance illustrated is and other parts
Difference, between various pieces identical similar portion mutually referring to.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention.
Multiple modifications to these embodiments will be apparent from for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
It is not intended to be limited to embodiment illustrated herein, and be to fit to consistent with principles disclosed herein and features of novelty
Scope the widest.
Claims (11)
1. a kind of array base palte is it is characterised in that include：
First substrate；
Positioned at described first substrate the first side mutually insulated and a plurality of data lines arranged in a crossed manner and multi-strip scanning line, described a plurality of
Data wire and described multi-strip scanning line limit multiple sub-pixels；
Multiple pixel electrodes positioned at described first substrate first side；
Positioned at the one-to-one thin film transistor (TFT) with described sub-pixel of described first substrate first side, described thin film transistor (TFT) bag
Include grid, source electrode, drain electrode and active layer, wherein, described source electrode is electrically connected with described data wire, described grid and described scanning
Line electrically connects, and described drain electrode is electrically connected with described pixel electrode；
Wherein, described drain electrode is in projecting with projection on described first substrate for the described scan line at least on described first substrate
Partly overlap.
2. array base palte according to claim 1 is it is characterised in that described drain electrode passes through the first mistake with described pixel electrode
Hole electrically connects.
3. array base palte according to claim 1 and 2 is it is characterised in that described drain electrode is had with described by the second via
Active layer electrically connects.
4. array base palte according to claim 3 is it is characterised in that throwing on described first substrate for described second via
Projection on described first substrate at least partly overlaps shadow with described scan line.
5. array base palte according to claim 3 is it is characterised in that projection on described first substrate for the described drain electrode is complete
Projection on described first substrate for first via described in all standing.
6. array base palte according to claim 1 is it is characterised in that many height picture of electrically connecting with same described scan line
Element includes the first sub-pixel and the second sub-pixel that the transmission direction of the drive signal along along described scan line is arranged successively, its
In, described first sub-pixel is corresponding to drain in the projection on described first substrate and described scan line on described first substrate
The overlapping area of projection be less than the projection on described first substrate for the corresponding drain electrode of described second sub-pixel and described scanning
The overlapping area of projection on described first substrate for the line.
7. array base palte according to claim 1 is it is characterised in that in described thin film transistor (TFT), described grid is located at institute
State active layer and deviate from described first substrate side, and insulate with described active layer phase.
8. array base palte according to claim 7 is it is characterised in that also include：
Light shield layer between described first substrate and described active layer, projection on described first substrate for the described light shield layer
With projection on described first substrate for the described active layer, there is lap.
9. array base palte according to claim 1 is it is characterised in that described grid includes positioned at same layer and is set up in parallel
First grid and second grid, described first grid and described second grid are electrically connected with scan line described in same.
10. array base palte according to claim 1 is it is characterised in that described array base palte also includes：
The public electrode insulating with described pixel electrode phase positioned at described first substrate first side.
A kind of 11. display floaters are it is characterised in that include：Array base palte described in any one of claim 1-10, and with institute
State the second substrate that array base palte is oppositely arranged.
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| CN106855674A (en) * | 2017-03-23 | 2017-06-16 | 厦门天马微电子有限公司 | Array base palte, display panel and display device |
| CN107153308A (en) * | 2017-06-19 | 2017-09-12 | 深圳市华星光电技术有限公司 | Array base palte and preparation method |
| CN110730984A (en) * | 2017-06-08 | 2020-01-24 | 夏普株式会社 | Active matrix substrate and display device |
| CN111521546A (en) * | 2020-06-15 | 2020-08-11 | 京东方科技集团股份有限公司 | Cell sensor array and cell detection chip |
| CN112987420A (en) * | 2019-12-17 | 2021-06-18 | 京东方科技集团股份有限公司 | Pixel circuit layout structure, display panel and display device |
| WO2022156131A1 (en) * | 2021-01-21 | 2022-07-28 | Tcl华星光电技术有限公司 | Array substrate, fabrication method for array substrate, and display panel |
| CN115061318A (en) * | 2022-06-30 | 2022-09-16 | 厦门天马微电子有限公司 | Display panel and display device |
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| CN110730984B (en) * | 2017-06-08 | 2021-12-03 | 夏普株式会社 | Active matrix substrate and display device |
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| CN112987420A (en) * | 2019-12-17 | 2021-06-18 | 京东方科技集团股份有限公司 | Pixel circuit layout structure, display panel and display device |
| CN111521546A (en) * | 2020-06-15 | 2020-08-11 | 京东方科技集团股份有限公司 | Cell sensor array and cell detection chip |
| CN111521546B (en) * | 2020-06-15 | 2023-07-25 | 京东方科技集团股份有限公司 | Cell sensor array and cell detection chip |
| WO2022156131A1 (en) * | 2021-01-21 | 2022-07-28 | Tcl华星光电技术有限公司 | Array substrate, fabrication method for array substrate, and display panel |
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| CN115061318B (en) * | 2022-06-30 | 2023-12-22 | 厦门天马微电子有限公司 | Display panel and display device |
| WO2024020952A1 (en) * | 2022-07-28 | 2024-02-01 | 京东方科技集团股份有限公司 | Display substrate, display panel, and display apparatus |
| CN115440789A (en) * | 2022-11-09 | 2022-12-06 | 北京京东方技术开发有限公司 | Display panel and display device |
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