JPH10142636A - Active matrix type display circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the auxiliary capacity without reducing the numerical aperture by using a semiconductor layer or wiring and a conductive film used as black matrix as electrodes, and using a silicon nitride as dielectric to form the auxiliary capacity. SOLUTION: A gate wiring 2 and a capacity wiring 3 are formed on a glass substrate 1 having a silicon nitride film formed as bed film. A silicon oxide film 4 is formed as gate insulating film, and an amorphous silicon film is formed. The amorphous silicon film is etched to provide a semiconductor layer 5 of thin film transistor. A polycrystalline silicon film having phosphor is formed and etched to provide a source 6 and a drain 7. Further, a data wiring 8 is provided by use of an aluminum film. A first auxiliary capacity 9 having the gate insulating film 3 as dielectric is formed between the capacity wiring 3 and the drain 7. A silicon nitride film 10 is then formed, and a polyimide layer 11 is form followed by etching to form the hole 12 of the auxiliary capacity. A titanium film is etched to form a black matrix.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a circuit configuration of a pixel region of an active matrix display device using a bottom gate thin film transistor. In particular, it relates to the configuration of the auxiliary capacitance.

[0002]

2. Description of the Related Art Recently, a technique for manufacturing a thin film transistor (TFT) on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for the active matrix type liquid crystal display device has increased. The active matrix type liquid crystal display device has a configuration in which tens to millions of pixels arranged in a matrix are each provided with a thin film transistor, and electric charges flowing into and out of each pixel electrode are controlled by a switching function of the thin film transistor. .

A liquid crystal is sandwiched between each pixel electrode and a counter electrode to form a kind of capacitor. Therefore,
By controlling the flow of charges into and out of the capacitor by the thin film transistor, the electro-optical characteristics of the liquid crystal are changed, and light transmitted through the liquid crystal panel can be controlled to display an image. In addition, since the holding voltage of the capacitor having such a configuration gradually decreases due to current leakage, there is a problem that the electro-optical characteristics of the liquid crystal change and the contrast of image display deteriorates.

In order to solve this problem, it is a general practice to provide another capacitor called an auxiliary capacitor in series with the capacitor composed of liquid crystal, and to supply charges lost due to leakage or the like to the capacitor composed of liquid crystal. FIG. 3 shows a circuit diagram of a conventional active matrix type liquid crystal display device. An active matrix display circuit is roughly divided into three parts. That is, a gate driver circuit 42 for driving a gate wiring (scan wiring, scanning wiring) 44,
A data driver circuit 41 for driving data lines (source lines and signal lines) 45 and an active matrix circuit 43 provided with pixels. Among them, the data driver circuit 41 and the gate driver circuit 42 are collectively called peripheral circuits.

The active matrix circuit 43 is provided so that a large number of gate wires 44 and data wires 45 cross each other, and a pixel electrode 47 is provided at each intersection. In addition, a switching element (thin film transistor) 46 for controlling the charge flowing into and out of the pixel electrode is provided. Further, as described above, the auxiliary capacitance 48 is provided in parallel with the pixel capacitor for the purpose of suppressing the fluctuation of the voltage of the pixel due to the leak current. (Fig. 3)

Various methods have been proposed for forming an auxiliary capacitance. The most typical configuration is to overlap a semiconductor layer (active layer) of a thin film transistor with a gate wiring (or a wiring in the same layer as the gate wiring). It is of the structure used. FIG. 6 shows the state of the cross section by explaining a manufacturing process. A gate wiring 72 and a capacitance wiring 73 are formed on a substrate 71. The capacitance wiring 73 may also serve as the gate wiring. In this case, the opening area can be made larger than when the capacitance wiring is provided.

When the capacitance wiring 73 is a gate wiring, wirings in rows different from the gate wiring 72 are used. If the gate wiring 72 and the wiring 73 are formed in the same row, the parasitic capacitance between the drain of the thin film transistor and the gate electrode becomes extremely large, which hinders switching. When the capacitance wiring 73 also serves as the gate wiring, there is a disadvantage that the parasitic capacitance of the wiring becomes large and the operation speed and the signal shape are reduced.

Next, a gate insulating film 7 covering these wirings is formed.
4. Further, an intrinsic semiconductor layer 75 is formed. Further, conductive regions (sources, drains) 76 and 7 doped with N-type or P-type impurities connected to the semiconductor layer 75.
7 is formed. Further, a data wiring 78 is formed.
(FIG. 6A) Thus, an auxiliary capacitor 79 using the gate insulating film 74 as a dielectric is obtained between the capacitor wiring 73 and the conductive region 77. Thereafter, a silicon nitride layer 80 is used as a passivation film.
And a first interlayer insulator made of a resin material layer 81 suitable for planarization such as polyimide. (FIG. 6 (B))

Since the conductivity of the thin film transistor changes due to light irradiation, a light-shielding coating (black matrix) 82 is overlaid on the thin film transistor in order to prevent the change. Further, the above-mentioned light-shielding film is also formed between pixels in order to prevent mixing of colors and brightness between pixels and to prevent display failure due to disturbance of an electric field at a boundary portion between pixels. For this reason, this light-shielding coating has a matrix shape and is called a black matrix (BM). B
When M82 is provided on a substrate provided with an active matrix circuit, it is effective in integrating pixels. In that case, it is usually formed on the polyimide layer 81 of the first interlayer insulator. (FIG. 6 (C))

Thereafter, a second interlayer insulator 83 is formed,
This and the first interlayer insulator are etched to form a contact hole reaching the conductive region 77, and the pixel electrodes 84 and 85 (pixel electrodes of another pixel) are formed by a transparent conductive film. Generally, the BM and the pixel electrode are formed such that there is no portion that does not overlap each other. If the BM is formed of an insulating material, the second interlayer insulator 83
Is unnecessary. (FIG. 6 (D))

[0011]

In the active matrix circuit having the above structure, the area occupied by the capacitance wiring 73 must be increased in order to increase the auxiliary capacitance. That is, in the conventional method, the auxiliary capacitance has a structure mainly having a two-dimensional spread. Since the portion where the capacitor wiring is also provided does not transmit light, the aperture ratio is reduced. An object of the present invention is to solve this problem and to increase the auxiliary capacitance without lowering the aperture ratio by configuring the auxiliary capacitance in a three-dimensional manner.

[0012]

According to the invention disclosed in this specification, a black matrix and an N-type or P-type conductive region (semiconductor layer) as a storage capacitor or a metal wiring connected to the region are provided. A capacitor is formed between the two, and a silicon nitride layer (corresponding to the silicon nitride layer 80 in FIG. 6) used as a passivation film of a first interlayer insulator is used as a dielectric.

An active matrix type display circuit according to the present invention comprises a bottom gate type thin film transistor, a gate wiring and a data wiring, a conductive film functioning as a black matrix and maintained at a constant potential, and an N-type or P-type semiconductor layer. (Or a metal wiring connected to it and in the same layer as the data wiring) An interlayer insulator having a silicon nitride layer and a polyimide layer between the conductive film and the data wiring (the silicon nitride layer is below the polyimide layer) , And

According to a first aspect of the present invention, in the above structure, a semiconductor layer (or a metal wiring) and a conductive film are used as both electrodes in a portion where the polyimide layer of the interlayer insulator is etched, and at least the nitride of the interlayer insulator is formed. An auxiliary capacitor having a silicon layer as a dielectric is formed. According to a second aspect of the present invention, in the above structure, in the interlayer insulator, the conductive film has a portion in contact with the silicon nitride layer of the interlayer insulator in a portion overlapping with the semiconductor layer (or the metal wiring). And

In the first or second aspect of the present invention,
When the semiconductor layer functioning as an auxiliary capacitor electrode has a structure continuous with the source or the drain of the thin film transistor, the circuit structure is simple and the occupied area can be reduced. Further, as the dielectric of the auxiliary capacitance, it is possible to use only a silicon nitride layer or a multilayer structure with another film (for example, silicon oxide). In the former case, a larger capacitance can be obtained by using silicon nitride having a thin dielectric and a large dielectric constant. First of the present invention
Alternatively, in the second, the thickness of the silicon nitride layer is 1000
{}, Preferably 500 ° or less.

In the present invention, the portion where the auxiliary capacitance is formed in the above configuration can be overlapped with the portion where the auxiliary capacitance is formed by the method shown in FIG. In that case,
The auxiliary capacitance of the present invention overlaps with the capacitance wiring. Thus, since the auxiliary capacitance is formed in multiple layers, the capacitance can be increased without lowering the aperture ratio. Further, in carrying out the present invention, the only necessary step is an etching step of the polyimide layer, other film formation, etching, etc. are unnecessary, and there is no difficulty in manufacturing by carrying out the present invention. .

[0017]

【Example】

[Embodiment 1] FIG. 1 shows a manufacturing process of this embodiment. First,
On a glass substrate 1 on which a silicon oxide film is formed as a base film by a sputtering method or a plasma CVD method to a thickness of 3000 ゲ, a gate wiring 2 and a capacity wiring 3 are formed by a 4000 厚 thick tantalum film. An oxide film may be formed on the surface of these wirings by anodic oxidation. So,
Insulation can be improved. Next, a silicon oxide film 4 is formed as a gate insulating film to a thickness of 1000 ° by a plasma CVD method, a low pressure thermal CVD method, or a sputtering method. This may be a multilayer film of a silicon nitride film and a silicon oxide film.

Further, an amorphous silicon film is formed to a thickness of 500 ° by a plasma CVD method or a low pressure thermal CVD method. This may be converted into a crystalline silicon film by further heating or irradiation with a laser beam. The semiconductor layer (active layer) 5 of the thin film transistor is obtained by etching the amorphous silicon film (or crystalline silicon film) thus obtained. Next, the polycrystalline silicon film containing phosphorus is
A source 6 and a drain 7 are obtained by forming a film having a thickness of 000 ° and etching the film. In addition, the thickness 60
The data wiring 8 is obtained by using the aluminum film of 00 °.
As described above, the first auxiliary capacitance 9 having the gate insulating film 4 as a dielectric is formed between the capacitance wiring 3 and the drain 7. (Fig. 1 (A))

FIG. 4A shows the circuit obtained in the steps up to this point when viewed from above. The numbers correspond to those in FIG. (FIG. 4A) Next, the silicon nitride film 10 is formed by a plasma CVD method using silane and ammonia, or silane and N ₂ O, or silane, ammonia and N ₂ O. This silicon nitride film 1
0 is formed to a thickness of 250 to 1000 °, here 500 °. The method for forming the silicon nitride film may be a method using dichlorosilane and ammonia. Decompression heat CV
The D method or the photo CVD method may be used.

Subsequently, by a spin coating method,
The polyimide layer 11 is formed to a thickness of at least 8000 ° or more, preferably 1.5 μm. The surface of the polyimide layer is formed flat. Thus, a first interlayer insulator composed of the silicon nitride layer 10 and the polyimide layer 11 is formed. Then, the polyimide layer 11 is etched to form holes 12 for auxiliary capacitance. (FIG. 1B) Further, a titanium film having a thickness of 1000 ° is formed by a sputtering method. Of course, a metal film such as a chromium film or an aluminum film may be used.

Then, the titanium film is etched to form a black matrix 13. Black matrix 13
Is formed so as to cover the hole 12 for the auxiliary capacitance formed earlier. Thus, the silicon nitride layer 10 is provided between the black matrix 13 and the drain 7 in the hole 12 for the auxiliary capacitance.
Is formed as a dielectric. (FIG. 1C) FIG. 4B shows the storage capacitor holes 12 and the black matrix 13 obtained in the steps up to here, as viewed from above. The numbers correspond to those in FIG. Hole 12 for auxiliary capacity
And a second auxiliary capacitance is formed in a portion where the black matrix 13 and the black matrix 13 overlap. (FIG. 4 (B))

Further, as a second interlayer insulator, a layer having a thickness of 5
000 of polyimide film 15 and polyimide film 11
And 15 and the silicon nitride layer 10 are etched to form a contact hole reaching the drain 7. Further, an ITO (indium tin oxide) film having a thickness of 1000 ° is formed by a sputtering method, and is etched.
The pixel electrodes 16 and 17 are formed. (FIG. 1D) Thus, an active matrix circuit is completed. When an insulating layer is formed using a polyimide film as in this embodiment, planarization is easy and the effect is large.

[Embodiment 2] FIG. 2 shows a manufacturing process of this embodiment. First, a glass substrate 2 coated with a base film
On top of this, the gate wiring 22 and the capacity wiring 23 are
ア ル ミ ニ ウ ム is formed of an aluminum film. An oxide film may be formed on the surface of these wirings by anodic oxidation.
Thus, the insulation can be improved. Next, a silicon oxide film 24 as a gate insulating film is
A film is formed to a thickness of 0 °. This may be a multilayer film of a silicon nitride film and a silicon oxide film.

Further, an amorphous silicon film is formed to a thickness of 500 ° by a plasma CVD method or a low pressure thermal CVD method. This may be converted into a crystalline silicon film by further heating or irradiation with a laser beam. By etching the amorphous silicon film (or crystalline silicon film) thus obtained, a semiconductor layer (active layer) 25 of the thin film transistor is obtained. Next, ions of phosphorus, which is an impurity imparting N-type, are selectively implanted into the semiconductor layer 25 at a dose of 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ³ , so that the source 2
6. Obtain the drain 27. After the impurity ions are implanted, heat treatment or laser irradiation may be performed to activate the region where the impurity ions have been implanted. (Fig. 2 (A))

Next, a data wiring 28 and a wiring (drain wiring) 29 connected to the drain are obtained by using an aluminum film having a thickness of 6000 °. In the above, the gate insulating film 24 is provided between the capacitance line 23 and the drain line 29.
Is formed as a first auxiliary capacitance 30. (FIG. 2B) Next, a silicon nitride layer 31 and a polyimide layer 32 were formed in Example 1.
It is formed under the same conditions as described above. Next, the polyimide layer 32 is etched to form holes 33 for auxiliary capacitance. (Figure 2
(C))

Further, a titanium film having a thickness of 1000 ° is formed by a sputtering method. Of course, a metal film such as a chromium film or an aluminum film may be used. Then, the black film 34 is formed by etching the titanium film. Thus, in the auxiliary capacitance hole 33, the second auxiliary capacitance 35 having the silicon nitride layer 31 as a dielectric is formed between the black matrix 34 and the drain wiring 29. (Figure 2
(D))

Further, as the second interlayer insulating material, a thickness of 5
2,000 polyimide film 36, and polyimide film 32
And 36 and the silicon nitride layer 31 are etched to form a contact hole reaching the drain wiring 29. In addition, a 1000 mm thick ITO film is formed by sputtering.
A (indium tin oxide) film is formed and etched to form pixel electrodes 37 and 38. (Figure 2
(E))

[Embodiment 3] FIG. 5 shows a manufacturing process of this embodiment. First, a glass substrate 5 coated with a base film
1 and a gate wiring 52 and a capacitance wiring 53 having a thickness of 4000
タ ン is formed by the tantalum film. An oxide film may be formed on the surface of these wirings by anodic oxidation. Thus, the insulation can be improved. Next, a silicon oxide film 54 is formed as a gate insulating film by a plasma CVD method at 1000.
To a thickness of This may be a multilayer film of a silicon nitride film and a silicon oxide film.

Further, an amorphous silicon film is formed to a thickness of 500 ° by a plasma CVD method. By etching the amorphous silicon film thus obtained, a semiconductor layer (active layer) 55 of the thin film transistor is obtained. Next, ions of phosphorus, which is an impurity imparting N-type, are added in an amount of 5 × 10 ¹⁴
The source 56 and the drain 57 are obtained by selectively implanting the semiconductor layer 55 at a dose of 0 ¹⁵ atoms / cm ³ . After the impurity ions are implanted, heat treatment or laser irradiation may be performed to activate the region where the impurity ions have been implanted. (FIG. 5 (A))

Next, a data wiring 58 is obtained using an aluminum film having a thickness of 6000 °. In the above, the semiconductor layer 55 is formed so as to overlap with the capacitor wiring 53. Therefore, a first auxiliary capacitance 59 having the gate insulating film 54 as a dielectric is formed between the capacitance wiring 53 and the drain 57. (FIG. 5B) Next, the silicon nitride layer 60 and the polyimide layer 61 were formed in Example 1.
It is formed under the same conditions as described above. Next, the polyimide layer 61 is etched to form holes 62 for auxiliary capacitance. (FIG. 5
(C))

Further, a titanium film having a thickness of 1000 ° is formed by a sputtering method, and the titanium film is etched to form a black matrix 63. Thus, a second auxiliary capacitor 64 having the silicon nitride layer 60 as a dielectric is formed between the black matrix 63 and the drain 57 in the auxiliary capacitor hole 62. (FIG. 5 (D))

Further, as the second interlayer insulator, a layer having a thickness of 5
000 polyimide film 65, and a polyimide film 61
And 65 and the silicon nitride layer 60 are etched to form a contact hole reaching the drain 57. further,
A 1000 ° thick ITO (indium tin oxide) film is formed by a sputtering method, and is etched to form pixel electrodes 66 and 67. (FIG. 5E)

[0033]

According to the present invention, an auxiliary capacitance is formed by using an N-type or P-type semiconductor layer or a wiring connected thereto and a conductive film used as a black matrix as an electrode, and a silicon nitride layer formed as a passivation film as a dielectric. This has clarified that the conventional problem can be solved. As described above, the present invention is industrially useful.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing step of an active matrix circuit of Example 1.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of an active matrix circuit of Example 2.

FIG. 3 is a circuit diagram of a general active matrix circuit.

FIG. 4 is a top view of a manufacturing process of the active matrix circuit of Example 1.

FIG. 5 is a cross-sectional view illustrating a manufacturing step of the active matrix circuit of Example 3.

FIG. 6 is a sectional view showing a manufacturing process of a conventional active matrix circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate wiring 3 Capacitance wiring 4 Gate insulating film 5 Semiconductor layer (active layer) 6 Source 7 Drain 8 Data wiring 9 1st storage capacitor 10 Silicon nitride layer 11, 15 Polyimide layer 12 Hole for storage capacitor 13 Black Matrix 14 Second auxiliary capacitance 16, 17 Pixel electrode

Claims (7)

[Claims] A bottom-gate thin film transistor; a gate wiring and a data wiring; an N-type or P-type semiconductor layer; or a metal wiring connected to the semiconductor layer and in the same layer as the data wiring; A conductive film that functions and is held at a constant potential; and an active matrix type display circuit including an interlayer insulator having a silicon nitride layer and a resin layer between the conductive film and the data wiring, In the interlayer insulator, the silicon nitride layer is below the resin layer, and the semiconductor layer and the conductive film, or the metal wiring and the conductive film, are provided in a portion where the resin layer of the interlayer insulator is etched. An active matrix display circuit in which auxiliary electrodes are formed using both electrodes as electrodes and at least the silicon nitride layer of the interlayer insulator as a dielectric. 2. A bottom-gate thin film transistor, a gate wiring and a data wiring, an N-type or P-type semiconductor layer, or a metal wiring connected to the semiconductor layer and in the same layer as the data wiring, and a black matrix. A conductive film that functions and is held at a constant potential; and an active matrix type display circuit including an interlayer insulator having a silicon nitride layer and a resin layer between the conductive film and the data wiring, In the interlayer insulator, the silicon nitride layer is below the resin layer, and the conductive film has a portion in contact with the silicon nitride layer of the interlayer insulator in a portion overlapping with the semiconductor layer or the metal wiring. An active matrix display circuit characterized by the following. 3. The active matrix display circuit according to claim 1, wherein the semiconductor layer is continuous with a source or a drain of the thin film transistor. 4. The active matrix type display circuit according to claim 1, wherein said auxiliary capacitance is formed only of a silicon nitride layer of said interlayer insulator as a dielectric. 5. The active matrix display circuit according to claim 1, wherein the thickness of the silicon nitride layer is 1000 ° or less. 6. The active matrix display circuit according to claim 1, wherein a portion where the resin layer of the interlayer insulator is etched overlaps a wiring in the same layer as the gate wiring. 7. The active matrix display circuit according to claim 1, wherein a portion where the conductive film is in contact with the silicon nitride layer of the interlayer insulator overlaps with a wiring in the same layer as the gate wiring.