KR101331803B1 - Liquid crystal display and method for fabricating the same - Google Patents

Abstract

The present invention discloses a method for manufacturing a liquid crystal display device in which the number of masks is simplified, the manufacturing process is simplified, the yield is improved, and the aperture ratio is secured, thereby improving the brightness. According to the disclosed method, a pixel portion is defined, wherein the pixel portion provides an insulating substrate divided into a pixel portion TFT region and a storage region, and sequentially forms a polysilicon film and a storage electrode film on the front surface of the substrate, wherein the storage electrode film and Selectively patterning a polysilicon film to form a pixel pattern covering the pixel portion, and selectively removing a storage electrode film of the pixel portion TFT region from the pixel pattern to form a storage electrode in the storage region and at the same time the pixel portion TFT region And forming a first active layer of a polysilicon film exposed by the storage electrode.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device,

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view schematically showing the structure of a liquid crystal display device with a built-in drive circuit. Fig.

2 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to the related art.

3A to 3I are cross-sectional views sequentially illustrating a manufacturing process along the line II-II ′ of the array substrate shown in FIG. 2.

4 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to the present invention.

5A through 5G are cross-sectional views taken along line III-III ′ of FIG. 4, and are cross-sectional views illustrating processes for manufacturing a liquid crystal display device according to the present invention.

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a method of manufacturing a liquid crystal display device in which the number of masks is simplified to simplify the manufacturing process, improve the yield and secure the aperture ratio and improve the brightness. .

In today's information society, display is more important as a visual information transmission medium, and in order to gain a major position in the future, it is necessary to satisfy requirements such as low power consumption, thinness, light weight, and high definition. Liquid Crystal Display (LCD), which is the flagship product of Flat Panel Display (FPD), is not only capable of satisfying these conditions of display but also has mass productivity. Therefore, And has become a core parts industry that can gradually replace conventional cathode ray tubes (CRTs).

In general, a liquid crystal display device displays a desired image by individually supplying data signals according to image information to liquid crystal cells arranged in a matrix form to adjust a light transmittance of the liquid crystal cells. to be.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

The amorphous silicon thin film transistor technology was established in 1979 by LeComber et al. In England, and was commercialized as a 3 "liquid crystal portable television in 1986. Recently, a large area thin film transistor liquid crystal display device of 50" or more has been developed. In particular, the amorphous silicon thin film transistor has been actively used because it is possible to use a low-cost insulating substrate to enable a low temperature process.

However, the electrical mobility (˜1 cm ² / Vsec) of the amorphous silicon thin film transistor is limited to use in peripheral circuits requiring high-speed operation of 1 MHz or more. As a result, studies are being actively conducted to simultaneously integrate the pixel portion and the driving circuit portion on a glass substrate by using a polycrystalline silicon (poly-Si) thin film transistor having a larger field effect mobility than the amorphous silicon thin film transistor. It's going on.

Polycrystalline silicon thin film transistor technology has been applied to small modules such as camcorders since liquid crystal color television was developed in 1982, and has the advantage of being able to manufacture driving circuits directly on the board because of its low sensitivity and high field effect mobility. .

Increasing the mobility may improve the operating frequency of the driving circuit unit that determines the number of driving pixels, thereby facilitating high definition of the display device. In addition, the distortion of the transmission signal is reduced due to the reduction of the charging time of the signal voltage of the pixel portion, thereby improving the picture quality.

In addition, the polycrystalline silicon thin film transistor can be driven at less than 10V compared to the amorphous silicon thin film transistor having a high driving voltage (˜25V) has the advantage that the power consumption can be reduced.

Hereinafter, the structure of the liquid crystal display device will be described in detail with reference to FIG.

1 is a plan view schematically illustrating a structure of a general liquid crystal display device, and illustrates a driving circuit-integrated liquid crystal display device in which a driving circuit unit is integrated on an array substrate.

As shown in the figure, the liquid crystal display is largely composed of a color filter substrate 5 and an array substrate 10 and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10. .

The array substrate 10 includes a pixel portion 35, which is an image display area in which unit pixels are arranged in a matrix, and a data driving circuit portion 31 and a gate driving circuit portion 32 positioned outside the pixel portion 35. It consists of a driving circuit section (30). Although not shown in the figure, the pixel portion 35 of the array substrate 10 includes a plurality of gate lines and data lines arranged vertically and horizontally on the substrate 10 to define a plurality of pixel regions, A thin film transistor which is a switching element formed in a crossing region of the data line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching element for applying and blocking a signal voltage to the pixel electrode, and is a kind of field effect transistor (FET) for controlling current flow by an electric field.

The driving circuit part 30 of the array substrate 10 is located outside the pixel portion 35 of the array substrate 10 protruding from the color filter substrate 5, and one side of the protruding array substrate 10. The data driving circuit part 31 is positioned at a long side, and the gate driving circuit part 32 is positioned at one end side of the protruding array substrate 10.

In this case, the data driving circuit 31 and the gate driving circuit 32 use a thin film transistor having a complementary metal oxide semiconductor (CMOS) structure, which is an inverter, in order to properly output an input signal.

For reference, the CMOS is an integrated circuit having an MOS structure which is used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS requires both an n-channel thin film transistor and a p-channel thin film transistor. It shows the intermediate form of PMOS.

The gate driving circuit unit 32 and the data driving circuit unit 31 are devices for supplying a scan signal and a data signal to the pixel electrode through the gate line and the data line, respectively, and are connected to an external signal input terminal (not shown). It controls the external signal input through the external signal input terminal to output to the pixel electrode.

In addition, a color filter (not shown) for implementing color and a common electrode (not shown), which is an opposite electrode of the pixel electrode formed on the array substrate 10, are formed in the pixel part 35 of the color filter substrate 5. have.

The color filter substrate 5 and the array substrate 10 having the above-described structure are provided with cell gaps to be spaced apart from each other by a spacer (not shown) Are attached together by a seal pattern (not shown) to form a unit liquid crystal display panel. At this time, the two substrates 5 and 10 are bonded to each other through a bonding key formed on the color filter substrate 5 or the array substrate 10.

The driving circuit integrated type liquid crystal display device having the above structure is advantageous in device characteristics because it uses a polycrystalline silicon thin film transistor, has excellent image quality, is capable of high definition, and consumes less power.

However, since the n-channel thin film transistor and the p-channel thin film transistor must be formed together on the same substrate, the driving circuit-integrated liquid crystal display device is more complicated in manufacturing process than the amorphous silicon thin film transistor liquid crystal display device forming only a single type channel. There are disadvantages.

As such, fabrication of an array substrate including the thin film transistor requires a plurality of photolithography processes.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development. As a result, many photolithography processes have many problems, such as lowering the production yield and increasing the probability of defects in the formed thin film transistors.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion.
2 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to the related art, and in particular, illustrates one pixel including a thin film transistor of a pixel portion.
In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.
As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 vertically and horizontally on the array substrate 110 to define a pixel area. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the thin film transistor in the pixel area, and the common electrode of a color filter substrate (not shown). In addition, a pixel electrode 118 for driving a liquid crystal (not shown) is formed.
The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the pixel electrode 118. In addition, the thin film transistor includes an active pattern 124 ′ that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. .
In this case, the active pattern 124 'is formed of a polycrystalline silicon thin film, and the active pattern 124' is a storage pattern (a part of which extends into the pixel region to form a first storage capacitor together with the common line 108). 124 “). That is, the common line 108 is formed in the pixel area in substantially the same direction as the gate line 116, and the common line 108 has a first insulating layer (not shown) therebetween. The first storage capacitor is configured to overlap with the storage pattern 124 ″. In this case, the storage pattern 124 ″ of the first embodiment is formed by storage doping through a separate mask process on the polycrystalline silicon thin film constituting the active pattern 124 ′.
The source electrode 122 and the drain electrode 123 are connected to the active pattern 124 ′ through the first contact hole 140a and the second contact hole 140b formed in the first insulating film and the second insulating film (not shown). Is electrically connected to the source region and the drain region. In addition, a portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to be formed in the third insulating layer (not shown). It is electrically connected to the pixel electrode 118 through the third contact hole 140c.
In this case, a part of the drain electrode 123 extending to the pixel region overlaps the common line 108 below the second insulating layer to form a second storage capacitor.
Hereinafter, a manufacturing process of the array substrate configured as described above will be described in detail with reference to the accompanying drawings.
3A to 3I are cross-sectional views sequentially illustrating a manufacturing process along a line II-II 'of the array substrate shown in FIG. 2, and illustrating, for example, a process of manufacturing an array substrate of a pixel portion where n-channel TFTs are formed. have.
As shown in FIG. 3A, a silicon thin film is formed on a substrate 110 made of a transparent insulating material such as glass, and then the silicon thin film is crystallized to form a polycrystalline silicon thin film. In this case, the substrate 110 includes a pixel portion divided into an n-channel TFT region and a storage region, and a circuit portion (not shown) divided into an n-channel TFT region and a p-channel TFT region, respectively. Thereafter, the polycrystalline silicon thin film is patterned using a photolithography process (first mask process) to form a polycrystalline silicon thin film pattern 124 constituting an active pattern and a storage pattern. In this case, a buffer layer 111 may be interposed between the substrate 110 and the polycrystalline silicon thin film pattern 124.
As shown in FIG. 3B, a portion of the polycrystalline silicon thin film pattern 124 is covered and then doped to form a storage pattern 124 ″. Here, a part of the polycrystalline silicon thin film pattern 124 covered by the photoresist forms an active pattern 124 ', which requires another photolithography process (second mask process).
As shown in FIG. 3C, after the first insulating film 115a and the first conductive film are sequentially formed on the entire surface of the substrate 110, the first conductive film is selectively selected using a photolithography process (third mask process). Patterning to form a gate electrode 121 made of the first conductive layer on the active pattern 124 'and forming a common line 108 formed of the first conductive layer on the storage pattern 124 ". The first conductive layer may be formed of aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), to form a common line 108 with the gate electrode 121. It may be made of a low resistance opaque conductive material such as chromium (Cr), molybdenum (Mo), etc. In this case, the common line 108 may be formed with the first insulating layer 115a therebetween in the pixel area. Overlap with the lower storage pattern 124 " The first is to configure the storage capacitor.
As shown in FIG. 3D, a first photoresist pattern 170 is formed on a substrate having the gate electrode 121 and a common line 108. The first photoresist pattern 170 is patterned to cover the entire surface of the pixel portion array substrate and the n-channel TFT region of the circuit portion and to expose the p-channel TFT region of the circuit portion (not shown in the circuit portion). A high concentration of p + ions is implanted into the p-channel TFT region of the circuit portion using the mask 170 as a mask to form a p + source region and a drain region (not shown). (Fourth Mask Process)
As shown in FIG. 3E, the first photoresist pattern is removed. Next, a second photoresist pattern 170 ′ is formed on the substrate having the p + source region and the drain region. The second photoresist pattern 170 'is patterned to cover the p-channel TFT region of the circuit portion, a portion of the n-channel TFT region of the pixel portion / circuit portion, and a storage region. A high concentration of n + ions is implanted into a predetermined region of the active pattern 124 'of the pixel portion using the second photoresist pattern 170' as a mask. As a result, an n + source region 124a and a drain region 124b are formed in the active pattern 124 'of the pixel portion. (Fifth mask process)
As shown in FIG. 3F, the second photoresist layer pattern 170 ′ is removed. Subsequently, a lightly doped drain (LDD) region 124l is formed by implanting low concentrations of n- ions into the entire surface of the substrate from which the second photoresist pattern is removed. In FIG. 3F, an unexplained reference numeral 124c denotes a channel region that forms a conductive channel between the source region 124a and the drain region 124b. Specifically, the LED region 124l is formed between the n + source region 124a and the channel region 124c and the n + drain region 124b and the channel region 124c.
On the other hand, although not shown in the figure, while forming the LED region 124l in the n-channel TFT region of the pixel portion, n-ions are also implanted in the n-channel TFT region of the circuit portion to form the LED region.
Then, after depositing the second insulating film 115b on the entire surface of the LED region 124l, the first insulating film 115a and the second insulating film 115b through a photolithography process (sixth mask process). The first contact hole 140a exposing a portion of the source region 124a and the second contact hole 140b exposing a portion of the drain region 124b are formed by removing a portion of the region.
As shown in FIG. 3G, the source region 124a is formed through the first contact hole 140a by forming a second conductive layer on the entire surface of the substrate 110 and then patterning the same by using a photolithography process (seventh mask process). ) And a source electrode 122 to be electrically connected to each other, and a drain electrode 123 to be electrically connected to the drain region 124b through the second contact hole 140b. In this case, a portion of the source electrode 122 extends in one direction to form a data line 117, and a portion of the drain electrode 123 extends into the pixel region so that the second insulating layer 115b is interposed therebetween. The second storage capacitor overlaps with the common line 108 below the second storage capacitor.
As shown in FIG. 3H, after the third insulating film 115c is deposited on the entire surface of the substrate 110, the drain is formed by patterning the third insulating film 115c using a photolithography process (eighth mask process). A third contact hole 140c exposing a part of the electrode 123 is formed.
As shown in FIG. 3I, after the third conductive film is formed on the entire surface of the substrate 110 on which the third insulating film 115c is formed, the third conductive film is selectively selected using a photolithography process (ninth mask process). By patterning, the pixel electrode 118 is electrically connected to the drain electrode 123 through the third contact hole 140c. The third conductive layer may use a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form the pixel electrode 118. have.
As described above, according to the related art, a total of nine mask processes are formed by forming an active pattern 124 ′ and a storage pattern 124 ″ from a polycrystalline silicon thin film and performing storage doping on the storage pattern through a separate mask process. Through this, TFTs of the pixel portion and the circuit portion can be manufactured.

In order to solve the above problems, an object of the present invention is to provide a method of manufacturing a liquid crystal display device which can improve the brightness by reducing the number of masks to simplify the manufacturing process, improve the yield and at the same time secure the aperture ratio.

 In order to achieve the above object, the manufacturing method of the liquid crystal display device according to the present invention, the pixel portion is defined, the pixel portion provides an insulating substrate divided into a pixel portion TFT region and a storage region, a polysilicon film on the entire surface of the substrate And forming a storage electrode film in sequence, and selectively patterning the storage electrode film and the polysilicon film to form a pixel pattern covering the pixel portion, and selectively removing the storage electrode film of the pixel portion TFT region from the pixel pattern. And forming a storage electrode at the same time, and forming a first active layer of a polysilicon film exposed by the storage electrode in the pixel portion TFT region.

Meanwhile, in the liquid crystal display device according to the present invention formed by the above method, a pixel portion is defined, and the pixel portion is formed on an insulating substrate divided into a pixel portion TFT region and a storage region, and is formed on the insulating substrate, and at least the thin film transistor region. And a storage electrode formed on the first active layer and selectively covering the storage area.
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Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the manufacturing method of the liquid crystal display device according to the present invention.

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4 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to the present invention.

As shown in FIG. 4, a gate line 250 and a data line 240 are formed on the insulating substrate 201 to define pixel regions vertically and horizontally. The insulating substrate 201 corresponds to an array substrate. A thin film transistor (TFT), which is a switching element, is formed in an intersection region of the gate line 250 and the data line 240. A pixel portion drain electrode pattern 225P2 is formed in the pixel area, which is a pixel electrode connected to the TFT and driving a liquid crystal (not shown) together with a common electrode (not shown) of a color filter substrate (not shown).

The TFT includes a pixel portion gate electrode 213P2 connected to the gate line 250, a pixel portion source electrode 223S1 connected to the data line 240, and a pixel portion drain electrode 223D1. In addition, the TFT includes a first active layer 205P1 which forms a conductive channel between the pixel portion source electrode 223S1 and the pixel portion drain electrode 223D1 by a gate voltage supplied to the pixel portion gate electrode 213P2. . The first active layer 205P1 is divided into a pixel portion source region 205P1S and a pixel portion drain region 205P1D. A portion of the first active layer 205P1 extends toward the pixel region, and a storage electrode 209P is formed on the first active layer 205P1 extending toward the pixel region. The storage electrode 209P may be patterned with an n + silicon layer or a metal film. An insulating film (not shown) may be interposed between the first active layer 205P1 and the storage electrode 209P.

The common line 213P3 is formed in the pixel area in substantially the same direction as the gate line 250. The common line 213P3 overlaps the storage electrode 209P with a gate insulating film (not shown) therebetween to form a storage capacitor. The common line 213P3 may be patterned with the same layer as the pixel portion gate electrode 213P2. When an insulating layer is interposed between the active layer 205P1 and the storage electrode 209P, the insulating layer may correspond to the first gate insulating layer and the gate insulating layer may correspond to the second gate insulating layer.

A protective film (not shown) is disposed to cover the substrate having the common line 213P3. A first contact hole 221H1 and a second contact hole 221H2 exposing the pixel portion source region 205P1S and the pixel portion drain region 205P1D of the first active layer 205P1 are formed in the passivation layer and the gate insulating layer, respectively. do. The pixel portion source electrode 223S1 and the pixel portion drain electrode 223D1 are respectively disposed in the pixel portion source region 205P1S of the first active layer 205P1 through the first contact hole 221H1 and the second contact hole 221H2. ) And the pixel portion drain region 205P1D.

The pixel portion drain electrode pattern 225P2 covers the pixel portion drain electrode 223D1 and is disposed so that a portion thereof extends toward the pixel region. The pixel portion drain electrode pattern 225P2 may correspond to a pixel electrode. In addition, a pixel portion source electrode pattern 225P1 is formed on the pixel portion source electrode 223S1. The pixel portion drain electrode pattern 225P2 and the pixel portion source electrode pattern 225P1 may be patterned with the same film.

5A through 5G are cross-sectional views taken along line III-III ′ of FIG. 4, and are cross-sectional views illustrating processes for manufacturing a liquid crystal display device according to the present invention.

Hereinafter, a method of manufacturing a liquid crystal display device according to the present invention will be described with reference to FIGS. 5A to 5G.

As shown in FIG. 5A, an insulating substrate 201 is provided. The insulating substrate 201 defines pixel portions divided into n-channel (or p-channel) TFT regions and storage regions, and circuit portions divided into n-channel TFT regions and p-channel TFT regions, respectively. That is, both the n-channel TFT and the p-channel TFT can be formed in the pixel portion, and the n-channel TFT and the p-channel TFT are both formed in the circuit portion to form a CMOS. The insulating substrate 201 may be an array substrate. The insulating substrate 201 may be a transparent substrate such as glass. A buffer layer 203, a polysilicon film 205, an insulating film 207, and a storage electrode film 209 are sequentially formed on the cut-out plate 201. The insulating layer 207 may be a gate insulating layer. The insulating layer 207 may be a silicon oxide layer SiO 2. The insulating film 207 may be omitted. The storage electrode film 209 may be an n + silicon layer or a metal film.

As shown in FIG. 5B, the first photoresist layer pattern 230 is formed on a substrate having the storage electrode layer using a slit or halftone mask (not shown). In the first photoresist pattern 230, an n-channel TFT region and a p-channel TFT region of the circuit portion, and an n-channel TFT region of the pixel portion are formed relatively thinner than the storage region of the pixel portion. A pixel pattern 210P1 covering the pixel portion by selectively primary etching the storage electrode layer, the insulating layer, and the polysilicon layer using the first photoresist layer pattern 230, and an n-channel TFT region and a p-channel TFT region of the circuit portion First and second circuit patterns 210P2 and 210P3 respectively covering the first and second circuit patterns 210P2 and 210P3 are formed. The storage electrode film, the insulating film, and the polysilicon film may be simultaneously etched. The etching process may be performed in a dry or mixed manner of wet and dry.

As shown in FIG. 5C, the first photoresist pattern is ashed. The first photoresist pattern 230P remaining after the ashing is removed from the n-channel TFT region and the p-channel TFT region of the relatively thin circuit portion and the TFT region of the pixel portion, and is selectively retained only in the storage region of the pixel portion. . Next, the storage electrode layer and the insulating layer are selectively removed from the pixel pattern 210P1 and the first and second circuit patterns 210P2 and 210P3 exposed by the remaining first photoresist layer pattern 230P. As a result, the storage electrode 209P made of the remaining storage electrode film is formed in the storage region of the pixel portion. At this time, each of the first, second and third active layers 205P1 and 205P2 made of a polysilicon film is formed in the n-channel TFT region of the pixel portion, the n-channel TFT region of the circuit portion, and the p-channel TFT region of the circuit portion. 205P3) is formed.

As shown in FIG. 5D, the remaining first photoresist pattern is removed. A gate insulating film 211, a first metal film 213, and a second photoresist film pattern 233 are sequentially formed on a substrate having the first, second and third active layers 205P1, 205P2, and 205P3. Meanwhile, as shown in FIG. 5A, when the insulating film 207 is interposed between the polysilicon film 205 and the storage electrode film 209, the insulating film 207 corresponds to a first gate insulating film, and the gate insulating film ( 211 may correspond to the second gate insulating layer. As described above, when the gate insulating film has a double structure of the first gate insulating film and the second gate insulating film, the total thickness of the gate insulating film having the double structure is the sum of the first gate insulating film and the second gate insulating film. Corresponds to Therefore, the gate insulating film having the double structure according to the present invention is formed to the same thickness as the conventional one by appropriately adjusting the thicknesses of the first gate insulating film and the second gate insulating film.

On the other hand, the second photoresist pattern 233 is patterned to selectively cover the entire portion of the pixel portion, the entire n-channel TFT region of the circuit portion, and a portion where the p-channel gate electrode of the p-channel TFT region is to be formed. That is, the second photoresist pattern 233 is patterned to selectively expose only a portion where the source / drain region is to be formed in the circuit portion p-channel TFT region.

Subsequently, the first metal layer is etched using the second photoresist layer pattern 233 to form a circuit portion first gate electrode 213P1 in the p-channel TFT region of the circuit portion. At this time, the entire pixel portion and the circuit portion n-channel TFT region are masked by the second photosensitive film pattern 233, so that the first metal film is left without being patterned. Next, p + doping is performed on the substrate having the first gate electrode 213P1 of the circuit part using the second photoresist pattern 233. As a result, circuit portion first source / drain regions 205P3S and 205P3D are formed in the third active layer 205P3.

As shown in FIG. 5E, the second photoresist pattern is removed. A third photoresist pattern 235 is formed on the entire surface of the substrate having the first gate electrode 213P1. The third photoresist pattern 235 includes a portion where each pixel portion gate electrode and a common line are to be formed in the pixel portion, a portion in which a circuit portion second gate electrode is to be formed in an n-channel TFT region of the circuit portion, and the p-channel TFT. Patterned to cover the entire area.

As shown in FIG. 5F, the remaining first metal layer is etched using the third photoresist pattern to form a pixel portion gate electrode 213P2 and a common line 213P3 in the pixel portion, and at the same time, the circuit portion The circuit portion second gate electrode 213P4 is formed in the n-type TFT region of? The remaining first metal layer etching process may be performed by wet etching. As a result, the pixel portion gate electrode 213P2, the common line 213P3, and the circuit portion second gate electrode 213P4 may be excessively etched laterally. Subsequently, n + ion doping is performed on the substrate having the third photoresist pattern. As a result, the pixel portion source region 205P1S and the pixel portion drain region 205P1D are formed in the n-channel TFT region of the pixel portion, and the circuit portion second source region 205P2S and the circuit portion second are formed in the n-channel TFT region of the circuit portion. Drain region 205P2D is formed. That is, the pixel portion source region 205P1S and the pixel portion drain region 205P1D are formed in the first active layer 205P1 under both sides of the pixel portion gate electrode 213P2. The circuit portion second source region 205P2S and the circuit portion second drain region 205P2D are formed in the second active layer 205P2 under both sides of the circuit portion second gate electrode 213P4.

Thereafter, the third photoresist pattern is removed. Next, the LED doping (n−) is applied to the entire surface of the substrate using the pixel portion gate electrode 213P2 and the circuit portion second gate electrode 213P4 as a mask. As a result, a first LED region 205P1L is formed in the n-channel TFT region of the pixel portion, and a second LED region 205P2L is formed in the n-channel TFT region of the circuit portion. The first and second LED regions 205P1L and 205P2L are formed by wet CD biases, and may be obtained by doping the entire substrate without a separate mask. The third photoresist pattern is removed.

As shown in FIG. 5G, a protective film 221 is formed on a substrate having the first and second LED areas 205P1L and 205P2L. The protective film 221 may use a silicon oxide film (SiO 2) and a silicon nitride film (SiN x) that are sequentially stacked. At this time, the protective film 221, (1) the silicon oxide film is deposited and activated heat treatment, and then the silicon nitride film is deposited and hydrogenated heat treatment, or (2) the silicon oxide film (SiO2) and silicon nitride film (SiNx ) Are formed in sequence, and these films are formed by heat treatment. Here, in the case of forming the protective film 221 by the method (2), the activation of the silicon oxide film (SiO2) and the hydrogenation of the silicon nitride film (SiNx) may be simultaneously performed through one heat treatment.

Meanwhile, a single silicon nitride film (SiNx) may be used as the passivation layer 221. As described above, in the present invention, the protective film 221 has a structure including a silicon nitride film (SiNx). At this time, the silicon nitride film (SiNx) serves as a hydrogen source that can contribute to the hydrogenation.

However, as described above, when the silicon oxide film (SiO 2) / silicon nitride film (SiN x) structure or a single silicon nitride film (SiN x) structure is adopted as the passivation layer, the silicon nitride film (SiN x) has a dielectric constant of 6.5 to 7.0 and the dielectric constant. The capacitance per unit area is larger for the same stacking thickness as compared to the silicon oxide film (SiO 2) having a constant of 3.9. Accordingly, the electrical delay between the gate lines and the data lines arranged on the upper and lower portions of the passivation layer is increased, thereby increasing the signal delay. This can be problematic in view of high speed operation or high resolution implementation.

In order to compensate for this problem, a silicon oxide film (SiO2) / silicon nitride film (SiNx) / silicon oxide film (SiO2) having a low dielectric constant silicon oxide film (SiO2) stacked on the silicon nitride film (SiNx) as the protective film 221. Can adopt triple structure. As such, when the protective film 221 adopts a triple structure of silicon oxide film (SiO 2) / silicon nitride film (SiN x) / silicon oxide film (SiO 2), a silicon oxide film (SiO 2) / silicon nitride film (SiN x) structure or a silicon nitride film ( Compared to the SiNx) structure, the capacitance per unit area can be reduced for the same stack thickness. As a result, the electrical influence between the gate line and the data line is reduced, thereby reducing the delay factor. As a result, high speed operation and high resolution can be realized.

Subsequently, the passivation layer and the gate insulation layer are etched using a separate mask (not shown) to form first, second, third, fourth, fifth, and sixth contact holes 221H1, 221H2, 221H3, and 221H4. ) 221H5 and 221H6. The first contact hole 221H1 and the second contact hole 221H2 expose the pixel portion source region 205P1S and the pixel portion drain region 205P1D. The second contact hole 221H2 is patterned to expose not only the pixel portion drain region 205P1D but also a portion of the storage electrode 209P. The third contact hole 221H3 and the fourth contact hole 221H4 expose the circuit portion second source region 205P2S and the circuit portion second drain region 205P2D. The fifth contact hole 221H5 and the sixth contact hole 221H6 expose the circuit portion first source region 205P3S and the circuit portion first drain region 205P3D.

Next, a second metal film is formed on the substrate having the contact holes. The second metal layer is patterned to form a pixel portion source electrode 223S1 and a pixel portion drain electrode 223D1 covering the first contact hole 221H1 and the second contact hole 221H2 in the pixel portion n-channel TFT region. . The circuit part second source covering the third contact hole 221H3 and the fourth contact hole 221H4 in the n-channel TFT region of the circuit part while the pixel part source electrode 223S1 and the pixel part drain electrode 223D1 are formed. The electrode 223S3 and the circuit portion second drain electrode 223D3 are formed. In addition, a circuit portion first source electrode 223S2 and a circuit portion first drain electrode 223S2 are formed in the circuit portion p-channel TFT region to cover the fifth contact hole 221H5 and the sixth contact hole 221H6.

Subsequently, a transparent conductive film is formed on the substrate having the source electrodes 223S1, 223S2, 223S3 and drain electrodes 223D1, 223D2, and 223D3. The transparent conductive film is patterned to form a pixel portion source electrode pattern 225P1 covering the pixel portion source electrode 223S1 and a pixel portion drain electrode pattern 225P2 covering the pixel portion drain electrode 223D1. Here, the pixel portion drain electrode pattern 225P2 is patterned to cover the pixel portion drain electrode 223D1 and extend toward the pixel region, as shown in FIG. 4. The pixel portion drain electrode pattern 225P2 may be a pixel electrode. At the same time, circuit portion first and second source electrode patterns 225P5 and 225P3 are formed in the p-channel TFT region and the n-channel TFT region of the circuit portion to cover the circuit portion first and second source electrodes 223S2 and 223S3. In addition, the circuit part first and second drain electrode patterns 225P6 and 225P4 covering the circuit part first and second drain electrodes 223D2 and 223D3 are formed.

As described above, in the present invention, the active layer and the storage electrode are formed by diffraction exposure (first mask process), the circuit part second gate electrode is formed in the circuit part p-channel TFT region (second mask process), and the pixel part is formed in the pixel part. Forming a gate electrode and a common line (third mask process), forming a contact hole in a protective film (fourth mask process), forming a source electrode and a drain electrode (fifth mask process), and forming a source electrode pattern and a drain electrode pattern (the first mask process) 6 mask process). Therefore, a high-aperture six-mask CMOS structure can be realized through such a process.

According to the present invention, an active layer and a storage electrode are formed by using a mask by a diffraction exposure process. Therefore, the number of masks used for manufacturing the thin film transistor can be reduced, thereby reducing the manufacturing process and cost.

In the present invention, the storage electrode is formed through the insulating layer on the active layer to prevent the active layer from being damaged, thereby improving the electrical characteristics of the thin film transistor. In addition, the effect of increasing the luminance due to the improvement of the aperture ratio can be expected.

Claims (31)

Providing an insulating substrate defined by a pixel portion divided into a pixel portion TFT region and a storage region and a circuit portion; Sequentially forming a polysilicon film, an insulating film, and a storage electrode film on the entire surface of the insulating substrate; Selectively patterning the polysilicon film, the insulating film, and the storage electrode film through a single mask process to form a polysilicon film pattern, an insulating film pattern, and a storage electrode film pattern in the pixel portion TFT region and the storage area; A storage electrode is formed in the storage area by removing the storage electrode film pattern and an insulating film pattern below the TFT, and the storage electrode film pattern and an insulating film under the pixel area TFT area. Forming an active layer of the polysilicon film pattern exposed by removing the pattern; Forming a gate insulating film on an entire surface of the insulating substrate including the active layer and the storage electrode; And Forming a gate electrode on the gate insulating film of the pixel portion TFT region, and forming a common line overlapping the storage electrode on the gate insulating film of the storage region. delete delete The method of claim 1, wherein the insulating layer is formed of a silicon oxide layer (SiO 2). The method of claim 1, wherein the forming of the storage electrode comprises: And sequentially removing the storage electrode film and the insulating film of the pixel portion TFT region of the pixel pattern. The method of claim 1, wherein the storage electrode layer is formed of an N + silicon layer. The method of claim 1, wherein the storage electrode layer is formed of a metal layer. The method of claim 1, wherein the active layer and the storage electrode are formed by diffraction exposure with the same mask. The method of claim 1, further comprising forming a buffer layer between the insulating substrate and the polysilicon film. The method of claim 1, wherein after forming the common line with the gate electrode, Forming a pixel portion source region and a drain region in the active layers under both sides of the gate electrode; Forming a protective film on the insulating substrate including the gate electrode; Patterning the passivation layer to form first and second contact holes exposing the pixel portion source region and drain region, respectively; Filling the first and second contact holes on the passivation layer, respectively, to form a pixel portion source electrode connected to the pixel portion source region and a pixel portion drain electrode connected to the pixel portion drain region; And And forming a pixel portion source electrode pattern covering the pixel portion source electrode and a pixel portion drain electrode pattern covering the pixel portion drain electrode. delete The method of claim 10, wherein the second contact hole is formed to simultaneously expose a portion of the storage electrode together with the pixel portion drain region. The method of claim 10, wherein forming the passivation layer comprises: Depositing and activating a silicon oxide film on an insulating substrate having the pixel portion source region and drain region; And depositing a silicon nitride film and performing a hydrogenation heat treatment on the activated silicon oxide film. The method of claim 10, wherein forming the passivation layer comprises: A silicon oxide film and a silicon nitride film are sequentially formed on the insulating substrate having the pixel portion source region and drain region, And heat-treating the silicon nitride film and the silicon oxide film to activate the silicon oxide film and to hydrogenate the silicon nitride film at the same time. The method of claim 10, wherein forming the passivation layer comprises: And forming a silicon oxide film, a silicon nitride film, and a silicon oxide film on a substrate having the pixel portion source region and the drain region in this order. Providing an insulating substrate defined by a pixel portion divided into a pixel portion TFT region and a storage region, and a circuit portion divided into an n-channel TFT region and a p-channel TFT region; Sequentially forming a polysilicon film, an insulating film, and a storage electrode film on the entire surface of the substrate; By selectively patterning the polysilicon film, the insulating film, and the storage electrode film through a single mask process, a pixel pattern covering the pixel portion and first and second circuit patterns covering the n-channel TFT region and the p-channel TFT region of the circuit portion, respectively, are formed. Forming; And By selectively removing the pixel pattern of the pixel portion TFT region, the storage electrode film of each of the first and second circuit patterns, and an insulating layer below the pixel portion TFT region, the pixel region TFT region and the storage region are formed, as well as the storage region. The n-channel TFT region and the p-channel TFT are selectively removed by selectively removing a first active layer having an insulating film and a storage electrode formed thereon, and at the same time the storage electrode films of the first and second circuit patterns of the circuit part and the insulating film under the insulating film. Forming a second active layer and a third active layer covering the region. 17. The method of claim 16, Forming a gate insulating film on the entire surface of the insulating substrate including the first, second, and third active layers, and then forming a circuit part first gate electrode of the p-channel TFT region on the gate insulating film on the third active layer; Forming a circuit portion first source region and a first drain region in the third active layer under both sides of the circuit portion first gate electrode; Forming a common line with a pixel portion gate electrode on the gate insulating layer on the first active layer, and forming a circuit portion second gate electrode on the n-channel TFT region of the gate insulating layer on the second active layer; A pixel portion source region and a drain region are formed in the first active layer under both sides of the pixel portion gate electrode, and a circuit portion second source region and a second drain are formed in the second active layer under both sides of the circuit portion second gate electrode. Forming a region; After forming a passivation film on the insulating substrate including the circuit portion second source region and the second drain region, patterning the passivation layer to form the pixel portion source region and the drain region, the circuit portion second source region and the second drain region, And forming first, second, third, fourth, fifth, and sixth contact holes exposing the circuit unit first source region and first drain region, respectively. A pixel portion source electrode connected to the pixel portion source region by filling the first, third, and fifth contact holes on the passivation layer, a circuit portion second source electrode connected to the circuit portion second source region, and the circuit portion agent A circuit portion first source electrode connected to the first source region is formed, and at the same time, the pixel portion drain electrode connected to the pixel portion drain region by filling the second, fourth, and sixth contact holes, respectively, and the second drain region of the circuit portion. Forming a circuit part second drain electrode connected to the circuit part, and a circuit part first drain electrode connected to the circuit part first drain area; And A pixel portion source electrode pattern covering the pixel portion source electrode and a circuit portion second and first source electrode pattern covering the circuit portion second and first source electrodes, respectively, and at the same time covering the pixel portion drain electrode And forming a circuit part second and a first drain electrode pattern covering the electrode pattern and the circuit part second and first drain electrodes, respectively. An insulating substrate on which a pixel portion divided into a pixel portion TFT region and a storage region and a circuit portion are defined; A first active layer formed on the insulating substrate in the pixel portion TFT area and the storage area; An insulating film formed on the first active layer of the storage area; A storage electrode formed on the insulating layer and covering the storage area; A gate insulating film formed on an entire surface of the insulating substrate including the storage electrode and the first active layer; A gate electrode formed on the gate insulating film over the first active layer in the pixel portion TFT region; And And a common line overlapping the storage electrode on the gate insulating layer of the storage area. 19. The liquid crystal display device of claim 18, further comprising a buffer layer interposed between the insulating substrate and the first active layer. 19. The liquid crystal display device according to claim 18, wherein the first active layer is a polycrystalline silicon film. delete 19. The liquid crystal display device according to claim 18, wherein the storage electrode is an N + silicon layer. 19. The liquid crystal display device according to claim 18, wherein the storage electrode is a metal film. 19. The semiconductor device of claim 18, further comprising: a circuit portion second gate electrode and a circuit portion first gate electrode formed in each of the n-channel TFT region and the p-channel TFT region of the circuit portion; A pixel portion source region and a drain region formed in the first active layer under both sides of the pixel portion gate electrode, a circuit portion second source region and a second drain region formed in the second active layer under both sides of the circuit portion second gate electrode; A circuit portion first source region and a first drain region formed in third active layers under both sides of the circuit portion first gate electrode; A protective film formed on an entire surface of the insulating substrate including the circuit portion first source region and first drain region; First, second, and third through the passivation layer to expose the pixel portion source region and drain region, the circuit portion second source region and second drain region, and the circuit portion first source region and first drain region, respectively; Fourth, fifth and sixth contact holes; A pixel portion source electrode and a circuit portion second source formed on the passivation layer and connected to the pixel portion source region, the circuit portion second source region, and the circuit portion first source region by filling the first, third, and fifth contact holes, respectively; Electrode and circuit part A pixel part drain electrode and a circuit part connected to the pixel part drain region, the circuit part second source region and the circuit part first drain region respectively by filling the first source electrode and the second, fourth and sixth contact holes. A second source electrode and a circuit portion first drain electrode; A pixel portion source electrode pattern covering the pixel portion source electrode, the circuit portion second source electrode and the first source electrode, a circuit portion second source electrode pattern and a circuit portion first source electrode pattern, and the pixel portion drain electrode and the circuit portion And a second drain electrode, a pixel part drain electrode pattern covering the circuit part first drain electrode, a circuit part second drain electrode pattern, and a circuit part first drain electrode pattern. 25. The liquid crystal display device according to claim 24, wherein a buffer layer is interposed between the substrate and the first active layer. delete 25. The liquid crystal display device according to claim 24, wherein the gate insulating film is a silicon oxide film (SiO2). 25. The liquid crystal display of claim 24, wherein the second contact hole exposes a portion of the storage electrode along with the pixel portion drain region. The method of claim 24, wherein the passivation layer comprises a single silicon nitride film (SiNx), a silicon oxide film (SiO2) / silicon nitride film (SiNx) sequentially stacked, and a silicon oxide film (SiO2) / silicon nitride film (SiNx) / silicon oxide film (sequentially stacked). And at least one of SiO2). An insulating substrate on which a pixel portion divided into a pixel portion TFT region and a storage region and a circuit portion divided into an n-channel TFT region and a p-channel TFT region are defined; First, second and third active layers formed on the insulating substrate in the pixel portion TFT region and the storage region and the n-channel TFT region and p-channel TFT region of the circuit portion; An insulating film formed on the first active layer of the storage area; A storage electrode formed on the insulating layer and covering the storage area; A gate insulating film formed on an entire surface of the insulating substrate including the storage electrode and the first, second and third active layers; A pixel portion gate electrode, a common line, a circuit portion second gate electrode and a circuit portion first gate electrode formed on the gate insulating films of the pixel portion TFT region and the storage region, the n-channel TFT region and the p-channel TFT region, respectively; A pixel portion source region and a drain region formed in the first active layer under both sides of the pixel portion gate electrode, a circuit portion second source region and a second drain region formed in the second active layer under both sides of the circuit portion second gate electrode, and the A circuit portion first source region and a first drain region formed in third active layers under both sides of the circuit portion first gate electrode; A protective film formed on an entire surface of the insulating substrate including the circuit portion first source region and first drain region; First, second, and third through the passivation layer to expose the pixel portion source region and drain region, the circuit portion second source region and second drain region, and the circuit portion first source region and first drain region, respectively; Fourth, fifth and sixth contact holes; A pixel portion source electrode and a circuit portion second source formed on the passivation layer and connected to the pixel portion source region, the circuit portion second source region, and the circuit portion first source region by filling the first, third, and fifth contact holes, respectively; Electrode and circuit part A pixel part drain electrode and a circuit part connected to the pixel part drain region, the circuit part second source region and the circuit part first drain region respectively by filling the first source electrode and the second, fourth and sixth contact holes. A second source electrode and a circuit portion first drain electrode; A pixel portion source electrode pattern covering the pixel portion source electrode, the circuit portion second source electrode and the first source electrode, a circuit portion second source electrode pattern and a circuit portion first source electrode pattern, and the pixel portion drain electrode and the circuit portion And a second drain electrode, a pixel portion drain electrode pattern covering the circuit portion first drain electrode, a circuit portion second drain electrode pattern, and a circuit portion first drain electrode pattern. delete

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