KR101266276B1 - Method of fabricating liquid crystal display device - Google Patents

Abstract

In the manufacturing method of the liquid crystal display of the present invention, the active pattern and the storage electrode are formed through one mask process, and data lines are disconnected up and down using gate metal, and then disconnected when the source / drain electrodes are formed. By simplifying the manufacturing process by reducing the number of masks by connecting the data lines, an organic insulating layer is formed between the data lines and the pixel electrodes and the apertures are improved by overlapping the data lines and the pixel electrodes. Providing a first substrate divided by a circuit portion of a second region; Forming an active pattern made of a silicon thin film and a first gate insulating layer on the pixel portion and the circuit portion through one mask process, and forming a storage electrode made of a conductive material on a predetermined region of the active pattern of the pixel portion; Forming a second gate insulating film on the first substrate on which the active pattern, the first gate insulating film, and the storage electrode are formed; Forming a gate electrode on a circuit portion of the first region where the second gate insulating film is formed, and forming a p + source / drain region on a predetermined region of an active pattern of the circuit portion of the first region; A gate electrode and a gate line are formed in the pixel portion on which the second gate insulating film is formed and the circuit portion of the second region, and are disconnected to the upper and lower portions with the common line and the gate line and the common line interposed therebetween; Forming a lower data line; Forming an n + source / drain region in a predetermined region of an active pattern of the pixel portion and the circuit portion of the second region; Forming a second insulating film on the first substrate on which the n + source / drain region is formed; Partial regions of the first gate insulating layer, the second gate insulating layer, and the second insulating layer may be removed to form first and second contact holes exposing source and drain regions of the active pattern; Forming a third contact hole and a fourth contact hole to expose a portion of the disconnected upper data line and the lower data line by removing a partial area; Source and drain electrodes electrically connected to the source and drain regions of the active pattern through the first and second contact holes, and the upper data through the third and fourth contact holes. Forming a connection line electrically connecting the line and the lower data line; Providing a second substrate; And bonding the first substrate and the second substrate to each other.

Active pattern, storage electrode, data line, connection line, pixel electrode, organic insulating film

Description

Manufacturing method of liquid crystal display device {METHOD OF FABRICATING LIQUID CRYSTAL DISPLAY DEVICE}

1 is a plan view schematically illustrating a structure of a general liquid crystal display device integrated with a driving circuit.

2 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

3A to 3I are cross-sectional views sequentially illustrating a manufacturing process along the line II-II ′ of the array substrate shown in FIG. 2.

4 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

5A through 5J are cross-sectional views sequentially illustrating a manufacturing process along line IV-IV ′ of the array substrate illustrated in FIG. 4.

6A to 6E are plan views sequentially illustrating a manufacturing process along the line IV-IV 'of the array substrate shown in FIG.

7A to 7F are cross-sectional views illustrating in detail the first mask process illustrated in FIGS. 5A and 6A.

8 is a schematic cross-sectional view taken along line AA ′ of the array substrate of FIG. 4.

9 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a third exemplary embodiment of the present invention.

10A to 10I are cross-sectional views sequentially showing a manufacturing process along the line IX-IX 'of the array substrate shown in FIG.

11A to 11E are plan views sequentially illustrating a manufacturing process along the line IX-IX 'of the array substrate shown in FIG.

12 is a schematic cross-sectional view taken along line BB ′ of the array substrate illustrated in FIG. 9.

DESCRIPTION OF REFERENCE NUMERALS

108,208,308: Common line 110,210,310: Array board

116,216,316: Gate line 117,217,317: Data line

118,218,318 pixel electrodes

121 ~ 321,221n, 321n, 221p, 321p: Gate electrode

122 ~ 322,222n, 322n, 222p, 322p: Source electrode

123 ~ 323,223n, 323n, 223p, 323p: Drain electrode

124 ', 224', 324 ': Active pattern

The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a liquid crystal display device in which the number of masks is reduced to simplify the manufacturing process, improve the yield, and secure the aperture ratio to improve luminance.

In today's information society, display is more important as a visual information transmission medium, and in order to gain a major position in the future, it is necessary to satisfy requirements such as low power consumption, thinness, light weight, and high definition. Liquid Crystal Display (LCD), the flagship product of Flat Panel Display (FPD), has not only the ability to satisfy these conditions of the display but also mass production. It has been established as a core parts industry that can gradually replace the existing cathode ray tube (CRT).

In general, a liquid crystal display device displays a desired image by individually supplying data signals according to image information to liquid crystal cells arranged in a matrix form to adjust a light transmittance of the liquid crystal cells. to be.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Amorphous silicon thin film transistor technology was established in 1979 by LeComber et al., UK, and commercialized as a 3 "liquid crystal portable television in 1986. Recently, a large area thin film transistor liquid crystal display device of 50" or more has been developed. In particular, the amorphous silicon thin film transistor has been actively used because it is possible to use a low-cost insulating substrate to enable a low temperature process.

However, the electrical mobility (˜1 cm ² / Vsec) of the amorphous silicon thin film transistor is limited to use in peripheral circuits requiring high-speed operation of 1 MHz or more. As a result, studies are being actively conducted to simultaneously integrate the pixel portion and the driving circuit portion on a glass substrate by using a polycrystalline silicon (poly-Si) thin film transistor having a larger field effect mobility than the amorphous silicon thin film transistor. It's going on.

Polycrystalline silicon thin film transistor technology has been applied to small modules such as camcorders since liquid crystal color television was developed in 1982, and has the advantage of being able to manufacture driving circuits directly on the board because of its low sensitivity and high field effect mobility. .

Increasing the mobility may improve the operating frequency of the driving circuit unit that determines the number of driving pixels, thereby facilitating high definition of the display device. In addition, due to the reduction in the charging time of the signal voltage of the pixel portion, the distortion of the transmission signal may be reduced, thereby improving image quality.

In addition, the polycrystalline silicon thin film transistor can be driven at less than 10V compared to the amorphous silicon thin film transistor having a high driving voltage (˜25V) has the advantage that the power consumption can be reduced.

Hereinafter, the structure of the liquid crystal display will be described in detail with reference to FIG. 1.

1 is a plan view schematically illustrating a structure of a general liquid crystal display device, and illustrates a driving circuit-integrated liquid crystal display device in which a driving circuit unit is integrated on an array substrate.

As shown in the figure, the liquid crystal display is largely composed of a color filter substrate 5 and an array substrate 10 and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10. .

The array substrate 10 includes a pixel portion 35, which is an image display area in which unit pixels are arranged in a matrix, and a data driving circuit portion 31 and a gate driving circuit portion 32 positioned outside the pixel portion 35. It consists of a driving circuit section (30).

In this case, although not shown in the drawing, the pixel portion 35 of the array substrate 10 is arranged on the substrate 10 vertically and horizontally to define a plurality of gate lines and data lines, the gate lines and A thin film transistor, which is a switching element formed in an intersection region of a data line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching element that applies and cuts off a signal voltage to a pixel electrode and is a type of field effect transistor (FET) that controls the flow of current by an electric field.

The driving circuit part 30 of the array substrate 10 is located outside the pixel portion 35 of the array substrate 10 protruding from the color filter substrate 5, and one side of the protruding array substrate 10. The data driving circuit part 31 is positioned at a long side, and the gate driving circuit part 32 is positioned at one end side of the protruding array substrate 10.

In this case, the data driving circuit 31 and the gate driving circuit 32 use a thin film transistor having a complementary metal oxide semiconductor (CMOS) structure, which is an inverter, in order to properly output an input signal.

For reference, the CMOS is an integrated circuit having an MOS structure which is used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS requires both an n-channel thin film transistor and a p-channel thin film transistor. It shows the intermediate form of PMOS.

The gate driving circuit unit 32 and the data driving circuit unit 31 are devices for supplying a scan signal and a data signal to the pixel electrode through the gate line and the data line, respectively, and are connected to an external signal input terminal (not shown). It controls the external signal input through the external signal input terminal to output to the pixel electrode.

In addition, a color filter (not shown) for implementing color and a common electrode (not shown), which is an opposite electrode of the pixel electrode formed on the array substrate 10, are formed in the pixel part 35 of the color filter substrate 5. have.

The color filter substrate 5 and the array substrate 10 configured as described above are provided with a cell gap so as to be uniformly spaced apart by a spacer (not shown), and a seal formed at an outer portion of the pixel portion 35. The patterns are bonded by a seal pattern (not shown) to form a unit liquid crystal display panel. At this time, the two substrates 5 and 10 are bonded to each other through a bonding key formed on the color filter substrate 5 or the array substrate 10.

The driving circuit-integrated liquid crystal display device configured as described above has the advantage of excellent device characteristics, excellent image quality, high definition, and low power consumption because it uses polycrystalline silicon thin film transistors.

However, since the n-channel thin film transistor and the p-channel thin film transistor must be formed together on the same substrate, the driving circuit-integrated liquid crystal display device is more complicated in manufacturing process than the amorphous silicon thin film transistor liquid crystal display device forming only a single type channel. There are disadvantages.

As such, fabrication of an array substrate including the thin film transistor requires a plurality of photolithography processes.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development. As a result, many photolithography processes have many problems, such as lowering the production yield and increasing the probability of defects in the formed thin film transistors.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problem, and forms the active pattern and the storage electrode in one mask process, and forms the gate wiring and the data line in one mask process to reduce the number of masks used in the manufacture of the thin film transistor. It is an object of the present invention to provide a method for manufacturing a reduced liquid crystal display device.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display device having an improved aperture ratio by using an organic insulating film.

Further objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a first substrate divided into a pixel portion and a circuit portion of the first and second regions; Forming an active pattern made of a silicon thin film and a first gate insulating layer on the pixel portion and the circuit portion through one mask process, and forming a storage electrode made of a conductive material on a predetermined region of the active pattern of the pixel portion; Forming a second gate insulating film on the first substrate on which the active pattern, the first gate insulating film, and the storage electrode are formed; Forming a gate electrode on a circuit portion of the first region where the second gate insulating film is formed, and forming a p + source / drain region on a predetermined region of an active pattern of the circuit portion of the first region; A gate electrode and a gate line are formed in the pixel portion on which the second gate insulating film is formed and the circuit portion of the second region, and are disconnected to the upper and lower portions with the common line and the gate line and the common line interposed therebetween; Forming a lower data line; Forming an n + source / drain region in a predetermined region of an active pattern of the pixel portion and the circuit portion of the second region; Forming a second insulating film on the first substrate on which the n + source / drain region is formed; Partial regions of the first gate insulating layer, the second gate insulating layer, and the second insulating layer may be removed to form first and second contact holes exposing source and drain regions of the active pattern; Forming a third contact hole and a fourth contact hole to expose a portion of the disconnected upper data line and the lower data line by removing a partial area; Source and drain electrodes electrically connected to the source and drain regions of the active pattern through the first and second contact holes, and the upper data through the third and fourth contact holes. Forming a connection line electrically connecting the line and the lower data line; Providing a second substrate; And bonding the first substrate and the second substrate to each other.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the manufacturing method of the liquid crystal display device according to the present invention.

FIG. 2 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention. In particular, FIG. 2 illustrates one pixel including a thin film transistor of a pixel portion.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 of the first embodiment to be arranged on the array substrate 110 in a vertical direction to define a pixel area. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the thin film transistor in the pixel area and is connected to a common electrode of a color filter substrate (not shown). In addition, a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the pixel electrode 118. In addition, the thin film transistor includes an active pattern 124 ′ that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. .

In this case, the active pattern 124 ′ of the first embodiment is formed of a polycrystalline silicon thin film, and a portion of the active pattern 124 ′ extends into the pixel region to form a first storage capacitor together with the common line 108. Is connected to the storage pattern 124 ". That is, the common line 108 is formed in the pixel area in substantially the same direction as the gate line 116, and the common line 108 is formed as a first line. The first storage capacitor is formed by overlapping the lower storage pattern 124 ″ with an insulating layer interposed therebetween. In this case, the storage pattern 124 ″ of the first embodiment is formed by storage doping through a separate mask process on the polycrystalline silicon thin film constituting the active pattern 124 ′.

The source electrode 122 and the drain electrode 123 are connected to the active pattern 124 ′ through the first contact hole 140a and the second contact hole 140b formed in the first insulating film and the second insulating film (not shown). Is electrically connected to the source region and the drain region. In addition, a portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to form a third insulating layer (not shown). It is electrically connected to the pixel electrode 118 through the formed third contact hole 140c.

In this case, a part of the drain electrode 123 extending to the pixel region overlaps the common line 108 below the second insulating layer to form a second storage capacitor.

Hereinafter, a manufacturing process of the array substrate configured as described above will be described in detail with reference to the accompanying drawings.

3A to 3I are cross-sectional views sequentially illustrating a manufacturing process along a line II-II 'of the array substrate shown in FIG. 2, and illustrating, for example, a process of manufacturing an array substrate of a pixel portion where n-channel TFTs are formed. have. At this time, both the n-channel TFT and the p-channel TFT are formed in the circuit portion.

As shown in FIG. 3A, a buffer layer 111 and a silicon thin film are formed on a substrate 110 made of a transparent insulating material such as glass, and then the silicon thin film is crystallized to form a polycrystalline silicon thin film. Thereafter, the polycrystalline silicon thin film is patterned using a photolithography process (first mask process) to form a polycrystalline silicon thin film pattern 124 constituting an active pattern and a storage pattern.

3B, a portion of the polycrystalline silicon thin film pattern 124 is covered and then doped to form a storage pattern 124 ″. Here, the polycrystalline silicon thin film pattern 124 covered by photoresist is formed. ) Forms an active pattern 124 ', which requires another photolithography process (second mask process).

Next, as shown in FIG. 3C, the first insulating film 115a and the first conductive film are sequentially formed on the entire surface of the substrate 110, and then the first film is formed using a photolithography process (third mask process). By selectively patterning a conductive layer, a gate electrode 121 made of the first conductive layer is formed on the active pattern 124 'and a common line 108 formed of the first conductive layer on the storage pattern 124 ". To form.

The first conductive layer may include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), and chromium to form the common line 108 with the gate electrode 121. It may be made of a low resistance opaque conductive material such as (chromium; Cr), molybdenum (Mo).

In this case, the common line 108 overlaps the lower storage pattern 124 ″ with the first insulating layer 115a therebetween in the pixel region to form a first storage capacitor.

After that, as shown in FIG. 3D, the n-channel TFT region of the front surface of the pixel portion array substrate 110 and the circuit portion are covered by the first blocking layer 170 made of photoresist (fourth mask process). High concentrations of p + ions are implanted into the p-channel TFT region to form a p + source region and a drain region.

3E, after the p-channel TFT region of the circuit portion, a portion of the n-channel TFT region and the storage region of the pixel portion / circuit portion are covered by the second blocking film 170 ′ (fifth mask process), A high concentration of n + ions is implanted into a predetermined region of the active pattern 124 'of the pixel portion to form an n + source region 124a and a drain region 124b. Here, reference numeral 124c denotes a channel region forming a conductive channel between the source region 124a and the drain region 124b.

Subsequently, the second blocking layer 170 ′ is removed, and then a low concentration of n − ions is implanted into the entire surface of the substrate 110 to form the n + source region 124a and the channel region 124c and the n + drain region 124b. A lightly doped drain (LDD) region 124l is formed between the channel region 124c and the channel region 124c.

In this case, the storage region may or may not be covered by the second blocking layer 170 ′, and n + ions are implanted in the same manner as the n-channel TFT region of the circuit unit so that the source region, the drain region, and the LED region of n + are formed. Will be formed.

Next, as shown in FIG. 3F, after depositing the second insulating film 115b on the entire surface of the substrate 110, the first insulating film 115a and the second film may be subjected to a photolithography process (sixth mask process). A portion of the insulating layer 115b is removed to form a first contact hole 140a for exposing a portion of the source region 124a and a second contact hole 140b for exposing a portion of the drain region 124b. .

As shown in FIG. 3G, the source region is formed through the first contact hole 140a by forming a second conductive layer on the entire surface of the substrate 110 and then patterning the same by using a photolithography process (seventh mask process). A source electrode 122 is formed to be electrically connected to 124a, and a drain electrode 123 is formed to be electrically connected to the drain region 124b through the second contact hole 140b. In this case, a portion of the source electrode 122 extends in one direction to form the data line 117, and a portion of the drain electrode 123 extends into the pixel region so that the second insulating layer 115b is interposed therebetween. The second storage capacitor overlaps with the common line 108 below the second storage capacitor.

Next, as shown in FIG. 3H, after depositing a third insulating film 115c on the entire surface of the substrate 110, patterning the third insulating film 115c using a photolithography process (eighth mask process). As a result, a third contact hole 140c exposing a part of the drain electrode 123 is formed.

3I, after the third conductive film is formed over the entire surface of the substrate 110 on which the third insulating film 115c is formed, the third conductive film is formed by using a photolithography process (ninth mask process). By selectively patterning, the pixel electrode 118 electrically connected to the drain electrode 123 through the third contact hole 140c is formed.

The third conductive layer may use a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form the pixel electrode 118. have.

In this case, in the case of the first embodiment, the active pattern and the storage pattern are formed of a polycrystalline silicon thin film and the storage doping is performed on the storage pattern through a separate mask process. By using diffraction exposure, it is possible to form an active pattern made of a silicon thin film and a storage electrode made of a conductive material in one mask process by using diffraction exposure, and a data line that is disconnected up and down using a gate metal is formed. Next, a second embodiment of the present invention in which the number of masks is reduced by connecting the disconnected data lines when forming a source / drain electrode is described in detail with reference to the accompanying drawings.

FIG. 4 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention, in particular one pixel including a thin film transistor of a pixel portion.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the figure, a gate line 216 and a data line 217 and 217 'are formed on the array substrate 210 in the second embodiment to be arranged horizontally and horizontally on the array substrate 210 to define a pixel area. have. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 216 and the data lines 217 and 217 ', and is connected to the thin film transistor in the pixel area, thereby forming a color filter substrate (not shown). A pixel electrode 218 for driving a liquid crystal (not shown) is formed together with the common electrode.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data lines 217 and 217 ′, and a drain electrode 223 connected to the pixel electrode 218. In addition, the thin film transistor includes an active pattern 224 ′ that forms a conductive channel between the source electrode 222 and the drain electrode 223 by the gate voltage supplied to the gate electrode 221.

In this case, a portion of the active pattern 224 ′ made of a polycrystalline silicon thin film extends to a pixel region, and a first gate insulating layer (not shown) is interposed on the active pattern 224 ′ extending to the pixel region. A storage electrode 230 " made of a conductive material is formed at < RTI ID = 0.0 > < / RTI > ) Overlaps the lower storage electrode 230 ″ with a second gate insulating layer interposed therebetween to form a first storage capacitor. In this case, unlike the first embodiment, the storage electrode 230 ″ of the second embodiment is made of an opaque conductive material and is formed simultaneously with the active pattern 224 ′ through one mask process.

The source electrode 222 and the drain electrode 223 form a first contact hole 240a and a second contact hole 240b formed in the first gate insulating film, the second gate insulating film, and the second insulating film (not shown). Through the active pattern 224 ′ is electrically connected to the source region and the drain region. In addition, a portion of the source electrode 222 extends in one direction to form a portion of the data line 217, and a portion of the drain electrode 223 extends toward the pixel region to be formed in the third insulating layer (not shown). The pixel electrode 218 is electrically connected to the pixel electrode 218 through the third contact hole 240c.

In this case, a part of the drain electrode 223 extending to the pixel region overlaps the common line 208 below the second insulating layer to form a second storage capacitor.

The third insulating film of the second embodiment may be formed of an organic insulating film having a low dielectric constant such that the pixel electrode 218 overlaps the gate line 216 and a part of the data line 217. It has the effect that an opening ratio is improved.

In this case, the data lines 217 and 217 'of the second embodiment may be formed through the same mask process using the same conductive material forming the gate line 216 and the common line 208, thereby reducing the number of masks. . In addition, since the data lines 217 and 217 'are formed on the same layer as the gate line 216 and the common line 208, the data lines 217 and 217' are positioned on the basis of the region where the gate line 216 and the common line 208 pass. In this case, the upper data line 217 and the lower data line 217 'which are disconnected are connected to each other through the connection line 220 formed by the source electrode 222 extending. For reference, the upper data line 217 represents a data line 217 of a corresponding pixel, and the lower data line 217 'represents a data line 217' of a next pixel.

In the array substrate of the second embodiment configured as described above, the active pattern 224 ′ and the storage electrode 230 ″ may be simultaneously formed in one mask process using diffraction exposure after depositing a conductive material on the polycrystalline silicon thin film. In particular, in the second embodiment, data lines 217 that are disconnected up and down when patterning gate wirings (that is, the gate electrode 221, the gate line 216, and the common electrode 208) are patterned. , 217 'are simultaneously patterned and the number of masks can be further reduced by connecting the disconnected data lines 217 and 217' using the connection line 220 when the source electrode 222 and the drain electrode 223 are formed. It will be described in detail through the manufacturing method of the liquid crystal display device.

5A through 5J are cross-sectional views sequentially illustrating a manufacturing process along line IV-IV ′ of the array substrate illustrated in FIG. 4, and FIGS. 6A through 6E are line IV-IV ′ of the array substrate illustrated in FIG. 4. It is a top view which shows the manufacturing process according to this sequentially.

In this case, in general, the thin film transistor formed in the pixel portion may be both n-channel or p-channel, and both the n-channel TFT and the p-channel TFT are formed in the circuit portion to form a CMOS. The method of manufacturing an n-channel TFT and a p-channel TFT is shown, for example.

5A and 6A, a buffer layer 211 and a silicon thin film are formed on a substrate 210 made of a transparent insulating material such as glass, and then the silicon thin film is crystallized to form a polycrystalline silicon thin film.

In this case, the buffer layer 211 serves to block impurities such as sodium (natrium) from the substrate 210 from penetrating into the upper layer during the process.

Thereafter, a first gate insulating film 215a and a conductive film are formed on the entire surface of the substrate 210 on which the polycrystalline silicon thin film is formed, and then patterned by using a photolithography process (first mask process) to form the pixel array substrate 210. The active pattern 224 ′ and the storage electrode 230 ″ are formed, and the n-channel active pattern 224n and the p-channel active pattern 224p are formed on the circuit unit array substrate 210.

As described above, the active patterns 224 ′, 224 n and 224 p and the storage electrode 230 ″ may be formed through one mask process by using diffraction exposure, which will be described in detail with reference to the accompanying drawings.

7A to 7F are cross-sectional views illustrating in detail the first mask process illustrated in FIGS. 5A and 6A.

As shown in FIG. 7A, a buffer film 211 and a silicon thin film 224 are formed on a substrate 210 made of a transparent insulating material such as glass.

The silicon thin film 224 may be formed of an amorphous silicon thin film or a polycrystalline silicon thin film. However, in the present exemplary embodiment, a thin film transistor is formed using a polycrystalline silicon thin film. In this case, the polycrystalline silicon thin film may be formed by depositing an amorphous silicon thin film on a substrate using various crystallization methods, which will be described below.

First, an amorphous silicon thin film may be formed by depositing in various ways. Representative methods of depositing the amorphous silicon thin film may include low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (Plasma Enhanced). Chemical Vapor Deposition (PECVD) method.

As a method of crystallizing the amorphous silicon thin film, there are largely a solid phase crystallization (SPC) method for heat treating the amorphous silicon thin film in a high temperature furnace and an excimer laser annealing (ELA) method using a laser. .

As the laser crystallization, an excimer laser annealing method using a pulse-type laser is mainly used, but in recent years, sequential lateral solidification (SLS) in which grains are grown in a horizontal direction to improve crystallization characteristics. The method is being studied.

The first gate insulating film 215a and the conductive film 230 made of molybdenum or aluminum-based conductive material are formed on the crystallized polycrystalline silicon thin film 224 as described above. In this case, the second embodiment does not directly sputter the conductive film constituting the storage electrode on the polycrystalline silicon thin film 224, but after depositing the first gate insulating film 215a on the polycrystalline silicon thin film 224, the conductive film ( By forming the 230, damage to the polycrystalline silicon thin film 224 due to sputtering can be prevented.

Next, as shown in FIG. 7B, a photosensitive film 270 made of a photosensitive material such as a photoresist is formed on the entire surface of the substrate 210 and then formed on the photosensitive film 270 through the diffraction mask 280 of the present embodiment. Optionally irradiates light.

In this case, the diffraction mask 280 used in the present embodiment is applied with a transmission region I and a slit pattern that transmit all of the irradiated light so that only a part of the light is transmitted and a portion of the slit region II and all of the irradiated light are blocked. The blocking region III is provided to block the light, and only the light passing through the diffraction mask 280 is irradiated onto the photosensitive film 270.

Subsequently, after developing the photosensitive film 270 exposed through the diffraction mask 280, as shown in FIG. 7C, light is blocked or partially blocked through the blocking region III and the slit region II. The first photoresist film pattern 270A and the second photoresist film pattern 270B having a predetermined thickness remain in the region, and the photoresist film is completely removed in the transmission region I through which all the light is transmitted. Exposed.

In this case, the first photoresist pattern 270A formed in the blocking region III is formed to be thicker than the second photoresist pattern 270B formed through the slit region II. In addition, the photosensitive film is completely removed in the region where all the light is transmitted through the transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto, and a negative photoresist may be used.

Next, as shown in FIG. 7D, when the first photoresist film pattern 270A and the second photoresist film pattern 270B formed as a mask are selectively removed, the polycrystalline silicon thin film and the conductive film formed thereunder are selectively removed. The active pattern 224 ′ formed of the polycrystalline silicon thin film is formed on the substrate 210. At this time, the conductive layer pattern 230 ′ formed of the conductive layer and patterned in the same shape as the active pattern 224 ′ remains on the active pattern 224 ′.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 270A and the second photoresist pattern 270B is performed, as shown in FIG. 7E, an upper portion of the active pattern 224 ′ is formed. That is, the second photoresist layer pattern of the slit region II to which diffraction exposure is applied is completely removed to expose the surface of the conductive layer pattern 230 ′.

In this case, the first photoresist pattern may be a third photoresist pattern 270A 'having the thickness of the second photoresist pattern removed, and thus remain only above the region corresponding to the blocking region III.

7F, when a portion of the conductive film pattern 230 ′ is removed using the remaining third photoresist pattern 270A ′ as a mask, the storage electrode 230 ″ made of the conductive film is removed. ) Is formed.

As shown in FIG. 5B, a second gate insulating film 215a ′ and a first conductive film 250 are formed on the entire surface of the substrate 210.

The first conductive layer 250 includes aluminum (Al), aluminum alloy, tungsten (W), and copper (Cuper) to form a gate electrode, a gate line, a common line, and a data line. ), Chromium (Cr), molybdenum (Mo) and the like can be made of a low resistance opaque conductive material.

Next, as shown in FIG. 5C, after the entire n-channel TFT region of the pixel portion and the circuit portion and a predetermined region of the p-channel TFT region of the circuit portion are covered by the first blocking film 270 ′ made of photoresist ( 2), and selectively patterning the first conductive film under the mask using the first blocking film 270 'as a mask to form a circuit part gate electrode 221p made of the first conductive film in the p-channel TFT region of the circuit part. .

The p + source region 224pa and the drain region 224pb are formed by implanting high concentration p + ions into the p-channel TFT region of the circuit unit using the first blocking layer 270 'as a mask. Here, reference numeral 224pc denotes a p-channel region that forms a conductive channel between the p + source region 224pa and the drain region 224pb.

Subsequently, as shown in FIGS. 5D, 5E, and 6B, the entire p-channel TFT region of the circuit portion and a portion of the n-channel TFT region of the pixel portion and the circuit portion are covered by the second blocking film 270 '(third mask). Process) and patterning the first conductive layer under the mask using the second blocking layer 270 'as a mask to form the pixel portion gate electrode 221, the gate line 215, and the data lines 217 and 217', respectively. ) And circuit gate electrodes 221n and 221p, and a common line 208 is formed on the storage electrode 230 ".

As described above, when the data lines 217 and 217 'are formed during patterning of the gate lines, one mask process may be reduced, and the data lines 217 and 217' may be connected to the gate line 216 and the common line 208. The upper data line 217 and the lower data line 217 'which are disconnected up and down with respect to the area passing by).

In this case, the gate electrodes 221, 221n and 221p, the gate line 216, the data lines 217 and 217 ′, and the storage electrode 230 ″ may be over-etched by wet etching the first conductive layer. As a result, the width of the second blocking layer 270 ′ is reduced.

Here, the common line 208 of the pixel portion overlaps the lower storage electrode 230 ″ with the second gate insulating layer 215a ′ therebetween to form a first storage capacitor. In this case, The gate insulating layer may include a first gate insulating layer 215a and a second gate insulating layer 215a 'to form a thin layer of the second gate insulating layer 215a', thereby increasing the capacity of the first storage capacitor. Therefore, the area of the opaque storage area such as the storage electrode 230 ″ or the common line 208 can be reduced, thereby effectively increasing the aperture ratio.

Subsequently, n + source regions 224a and 224na and drain regions 224b and 224nb are formed by implanting high concentrations of n + ions into the n-channel TFT region of the pixel portion and the circuit portion using the second blocking layer 270 'as a mask. . Here, reference numerals 224c and 224nc denote n-channel regions that form conductive channels between the n + source regions 224a and 224na and the drain regions 224b and 224nb.

As shown in FIG. 5F, the second blocking layer is removed and a low concentration of n − ions is implanted into the entire surface of the substrate 210 to form the n + source regions 224a and 224na, the channel regions 224c and 224nc, and the n +. LED regions 224l and 224l are formed between the drain regions 224b and 224nb and the channel regions 224c and 224nc.

Next, as shown in FIGS. 5G and 6C, after depositing a second insulating film 215b on the entire surface of the substrate 210, the first gate insulating film 215a is formed through a photolithography process (fourth mask process). ) And first contact holes 240a, 240na, and 240pa exposing portions of the source regions 224a, 224na, and 224pa by removing portions of the second gate insulating layer 215a 'and the second insulating layer 215b. Second contact holes 240b, 240nb, and 240pb exposing portions of the drain regions 224b, 224nb, and 224pb are formed.

In addition, portions of the first gate insulating layer 215a, the second gate insulating layer 215a ′, and the second insulating layer 215b may be removed to remove the disconnected upper data line 217 and the lower data line 217 ′. The third contact hole 240c and the fourth contact hole 240d exposing a part thereof are formed.

The second insulating layer 215b may be a double layer of SiNx / SiO ₂ . In this case, an activation heat treatment may be performed after SiO ₂ deposition, and hydrogenation heat treatment may be performed after SiNx deposition. Alternatively, both SiNx / SiO ₂ may be hydrogenated and activated simultaneously through one heat treatment after deposition.

In addition, as the second insulating layer 215b, a single SiNx layer or a triple layer of SiO ₂ / SiNx / SiO ₂ may be used.

When the second contact hole 240b of the pixel portion is formed, the drain region 224b and a portion of the storage electrode 230 ″ of the pixel portion may be exposed together, and the drain region 224b and the storage electrode of the pixel portion may be exposed. Two second contact holes may be formed to expose a portion of the 230 ″, and may be connected to each other by a drain electrode.

Subsequently, as shown in FIGS. 5H and 6D, a second conductive film is formed on the entire surface of the substrate 210 and then patterned using a photolithography process (a fifth mask process) to form the first contact holes 240a, 240na, Source electrodes 222, 222n and 222p electrically connected to the source regions 224a, 224na and 224pa through 240pa, and the drain regions 224b through the second contact holes 240b, 240nb and 240pb. Drain electrodes 223, 223n and 223p electrically connected to the second and second electrodes 224nb and 224pb. In addition, a connection line 220 is formed to electrically connect the disconnected upper data line 217 and the lower data line 217 'through the third contact hole 240c and the fourth contact hole 240d. .

In this case, a portion of the source electrode 222 of the pixel portion extends in one direction to be connected to the connection line 220, and a portion of the drain electrode 223 of the pixel portion extends to the pixel region to extend the second insulating layer 215b. The second storage capacitor is formed by overlapping the common line 208 under the gap.

Next, as shown in FIGS. 5I and 6E, after depositing a third insulating film 215c on the entire surface of the substrate 210, the third insulating film 215c using a photolithography process (sixth mask process). ) Is formed to form a fifth contact hole 240e exposing a part of the drain electrode 223 of the pixel portion.

In this case, the third insulating layer 15c may be formed of a transparent organic material such as benzocyclobutene or acrylic resin for high opening ratio.

5J and 6F, after the third conductive film is formed on the entire surface of the substrate 210 on which the third insulating film 215c is formed, the photolithography process (seventh mask process) is used to form the third conductive film. By selectively patterning the third conductive film, the pixel electrode 218 is electrically connected to the drain electrode 223 of the pixel portion through the fifth contact hole 240e.

The third conductive layer may use a transparent conductive material having excellent transmittance such as indium tin oxide or indium zinc oxide to form the pixel electrode 218.

In this case, in the second embodiment, the pixel electrode 218 is formed to overlap the gate line 216 and a part of the data line 217 by forming a third insulating film 215c made of an organic material having a low dielectric constant. It becomes possible to have an effect which improves an aperture ratio substantially.

That is, referring to FIG. 8, the data line 217 of the second embodiment is formed on the same layer as the gate wiring, and the second insulating film 215b and the third insulating film 215c are formed thereon. In this case, the third insulating film 215c is formed of an organic insulating film having a low dielectric constant, so that the pixel electrode 218 can be formed to overlap with a part of the data line 217. As a result, the data line is the same as in the conventional case. Compared to the case where the pixel electrode 18 is formed by being spaced apart from the predetermined distance W by the predetermined distance W, the aperture ratio by the distance W is increased.

For reference, reference numerals 10, 11, 15a, and 15b sequentially indicate a conventional array substrate, a buffer layer, a first insulating film, and a second insulating film.

As described above, according to the second embodiment, an array substrate including both the TFT of the pixel portion and the n-channel TFT and the p-channel TFT of the circuit portion may be fabricated through a total of seven mask processes, wherein the source electrode and the drain electrode are patterned. By directly depositing a transparent conductive material thereon to form a pixel electrode, the contact hole mask process for contacting the pixel electrode can be eliminated, which will be described in detail with reference to the following third embodiment.

FIG. 9 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a third exemplary embodiment of the present invention. In particular, one pixel including a thin film transistor of a pixel portion is illustrated.

As shown in the figure, a gate line 316 and a data line 317 and 317 'are formed on the array substrate 310 of the third embodiment to be arranged horizontally and horizontally on the array substrate 310 to define a pixel region. have. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 316 and the data lines 317 and 317 ', and is connected to the thin film transistor in the pixel area, thereby forming a color filter substrate (not shown). A pixel electrode 218 for driving a liquid crystal (not shown) is formed together with the common electrode.

The thin film transistor includes a gate electrode 321 connected to the gate line 316, a source electrode 322 connected to the data lines 317 and 317 ′, and a drain electrode 323 connected to the pixel electrode 318. In addition, the thin film transistor includes an active pattern 324 ′ that forms a conductive channel between the source electrode 322 and the drain electrode 323 by a gate voltage supplied to the gate electrode 321.

In this case, a portion of the active pattern 324 'made of a polycrystalline silicon thin film extends to a pixel region, and a first gate insulating film (not shown) is interposed on the active pattern 324' extending to the pixel region. A storage electrode 330 " made of a conductive material is formed in the pixel region. In addition, a common line 308 is formed in the pixel area in substantially the same direction as the gate line 316, and the common line 308 is formed. ) Overlaps the lower storage electrode 330 ″ with a second gate insulating layer (not shown) therebetween to form a first storage capacitor.

The source electrode 322 and the drain electrode 323 may include a first contact hole 340a and a second contact hole 340b formed in the first gate insulating film, the second gate insulating film, and the second insulating film (not shown). Through the active pattern 324 'is electrically connected to the source region and the drain region. In addition, a part of the source electrode 322 extends in one direction to form a part of the data line 317, and a part of the drain electrode 323 extends toward the pixel area to be formed in the third insulating layer (not shown). The pixel electrode 318 is electrically connected to the pixel electrode 318 through the third contact hole 340c.

In this case, a part of the drain electrode 323 extending to the pixel region overlaps the common line 308 beneath the second insulating layer to form a second storage capacitor.

At this time, the data lines 317 and 317 'of the third embodiment are the same mask process using the same conductive material forming the gate line 316 and the common line 308 as in the second embodiment described above. The number of masks can be reduced by forming through. In addition, since the data lines 317 and 317 'are formed on the same layer as the gate line 316 and the common line 308, the data lines 317 and 317' are positioned on the basis of the region where the gate line 316 and the common line 308 pass. In this case, the upper data line 317 and the lower data line 317 'which are disconnected are connected to each other through the connection line 320 formed by the source electrode 322 extending. For reference, the upper data line 317 represents a data line 317 of a corresponding pixel, and the lower data line 317 'represents a data line 317' of a next pixel.

The array substrate 310 of the third embodiment configured as described above forms the source electrode 322 and the drain electrode 323 by using the first to fifth mask processes of the array substrate of the second embodiment. After depositing a transparent conductive material directly on the transparent conductive material by selectively removing the transparent conductive material in the region except the upper region and the pixel region of the source electrode 322 and the connection line 320 and the drain electrode 323 A source electrode pattern 322 ', a connection line pattern 320', and a drain electrode pattern 323 'are formed to cover and protect the source electrode 322, the connection line 320, and the drain electrode 323. At the same time, it is possible to form the pixel electrode 318 in the pixel region, which will be described in detail through the manufacturing method of the liquid crystal display.

10A to 10I are cross-sectional views sequentially illustrating a manufacturing process along line IX-IX ′ of the array substrate illustrated in FIG. 9, and FIGS. 11A to 11E are lines IX-IX ′ of the array substrate illustrated in FIG. 9. It is a top view which shows the manufacturing process according to this sequentially.

In this case, in general, the thin film transistor formed in the pixel portion may be both n-channel or p-channel, and both the n-channel TFT and the p-channel TFT are formed in the circuit portion to form a CMOS. The method of manufacturing an n-channel TFT and a p-channel TFT is shown, for example.

10A and 11A, a buffer layer 311 and a silicon thin film are formed on a substrate 310 made of a transparent insulating material such as glass, and then the silicon thin film is crystallized to form a polycrystalline silicon thin film.

Thereafter, a first gate insulating film 315a and a conductive film are formed on the entire surface of the substrate 310 on which the polycrystalline silicon thin film is formed, and then patterned by using a photolithography process (first mask process) to form the pixel array substrate 310. An active pattern 324 ′ and a storage electrode 330 ″ are formed, and an n-channel active pattern 324n and a p-channel active pattern 324p are formed on the circuit array substrate 310.

As described above, the active patterns 324 ′, 324 n and 324 p and the storage electrode 330 ″ may be formed through one mask process by using diffraction exposure.

As shown in FIG. 10B, a second gate insulating film 315a ′ and a first conductive film 350 are formed on the entire surface of the substrate 310.

Next, as shown in FIG. 10C, the entire area of the n-channel TFT region of the pixel portion and the circuit portion and the predetermined region of the p-channel TFT region of the circuit portion are covered with a first blocking film 370 'made of photoresist (second). 2), the first blocking layer 370 ′ is selectively patterned with a first conductive layer under the mask to form a gate portion of the circuit portion gate electrode 321p formed of the first conductive layer in the p-channel TFT region of the circuit portion. .

The p + source region 324pa and the drain region 324pb are formed by implanting high concentrations of p + ions into the p-channel TFT region of the circuit unit using the first blocking layer 370 'as a mask. Here, reference numeral 324pc denotes a p-channel region that forms a conductive channel between the p + source region 324pa and the drain region 324pb.

Then, as shown in FIGS. 10D, 10E, and 11B, the entire p-channel TFT region of the circuit portion and a portion of the n-channel TFT region of the pixel portion and the circuit portion are covered by the second blocking film 370 '(third mask). Process) and patterning the first conductive layer under the mask using the second blocking layer 370 'as a mask to form the pixel portion gate electrode 321, the gate line 315, and the data lines 317 and 317', respectively. ) And circuit gate electrodes 321n and 321p, and a common line 308 is formed on the storage electrode 330 ".

In this case, the data lines 317 and 317 'are connected to the upper data line 317 and the lower data line 317' which are disconnected up and down based on a region where the gate line 316 and the common line 308 pass. It is composed.

In this case, the gate electrodes 321, 321n and 321p, the gate line 316, the data lines 317 and 317 ′, and the storage electrode 330 ″ may be overetched by wet etching the first conductive layer. The width of the second blocking layer 370 ′ is reduced.

The common line 308 of the pixel portion overlaps the lower storage electrode 330 ″ with the second gate insulating layer 315a ′ therebetween to form a first storage capacitor.

Subsequently, n + source regions 324a and 324na and drain regions 324b and 324nb are formed by implanting high concentrations of n + ions into the n-channel TFT region of the pixel portion and the circuit portion using the second blocking layer 370 'as a mask. . Here, reference numerals 324c and 324nc denote n-channel regions that form conductive channels between the n + source regions 324a and 324na and the drain regions 324b and 324nb.

As shown in FIG. 10F, after removing the second blocking layer, low concentrations of n − ions are implanted into the entire surface of the substrate 310 to form the n + source regions 324a and 324na, the channel regions 324c and 324nc, and the n +. The LED regions 324l and 324l are formed between the drain regions 324b and 324nb and the channel regions 324c and 324nc.

Next, as shown in FIGS. 10G and 11C, after depositing a second insulating film 315b on the entire surface of the substrate 310, the first gate insulating film 315a is formed through a photolithography process (fourth mask process). ) And first contact holes 340a, 340na and 340pa exposing portions of the source regions 324a, 324na and 324pa by removing portions of the second gate insulating film 315a 'and the second insulating film 315b. Second contact holes 340b, 340nb, and 340pb exposing portions of the drain regions 324b, 324nb, and 324pb are formed.

In addition, partial regions of the first gate insulating layer 315a, the second gate insulating layer 315a ', and the second insulating layer 315b may be removed to remove the disconnected upper data line 317 and the lower data line 317'. The third contact hole 340c and the fourth contact hole 340d exposing a part are formed.

Thereafter, as shown in FIGS. 10H and 11D, the second contact layer is formed on the entire surface of the substrate 310 and then patterned using a photolithography process (a fifth mask process) to form the first contact holes 340a, 340na, Source electrodes 322, 322n and 322p are electrically connected to the source regions 324a, 324na and 324pa through 340pa, and the drain regions 324b through the second contact holes 340b, 340nb and 340pb. Drain electrodes 323, 323n and 323p electrically connected to 324nb and 324pb are formed. In addition, a connection line 320 is formed to electrically connect the disconnected upper data line 317 and the lower data line 317 'through the third contact hole 340c and the fourth contact hole 340d. .

In this case, a portion of the source electrode 322 of the pixel portion extends in one direction and is connected to the connection line 320, and a portion of the drain electrode 323 of the pixel portion extends into the pixel region to extend the second insulating film 315b. The second storage capacitor is formed by overlapping the common line 308 therebetween.

Next, as shown in FIGS. 10I and 11E, after forming a third conductive film on the entire surface of the substrate 310, by selectively patterning the third conductive film using a photolithography process (sixth mask process). The source electrode pattern 322 ', the connection line pattern 320', and the drain electrode pattern 323 of the third conductive layer are formed on the source electrode 322, the connection line 320, the drain electrode 323, and the pixel region. And the pixel electrode 318 are formed. In this case, the source electrode pattern 322 ′, the connection line pattern 320 ′, and the drain electrode pattern 323 ′ are patterned to completely cover the source electrode 322, the connection line 320, and the drain electrode 323. As a result, etching of the source electrode 322, the connection line 320, and the drain electrode 323 according to the etchant of the third conductive layer may be prevented.

The third conductive layer may use a transparent conductive material having excellent transmittance, such as indium tin oxide or indium zinc oxide, to form the pixel electrode 318. As described above, the third embodiment includes a pixel electrode contact. By forming the pixel electrode 318 so as to be directly connected to the drain electrode 323 without a contact hole, the mask process can be further reduced compared to the case of the second embodiment.

In addition, in the third embodiment, the pixel electrode 318 may be formed to overlap a portion of the gate line 316 and the data line 317, thereby substantially improving the aperture ratio.

That is, referring to FIG. 12, the data line 317 of the third embodiment is formed on the same layer as the gate wiring, and a second insulating film 315b is formed thereon. In this case, the pixel electrode 318 may be formed to overlap a part of the data line 317, and as a result, the pixel electrode 318 is spaced apart from the data line 17 by a predetermined distance W as in the conventional case. Compared to the case where (18) is formed, the opening ratio by the separation distance W is increased.

The array substrates of the first to third embodiments configured as described above are bonded to face the color filter substrate by sealants formed on the outer side of the image display area to form a liquid crystal display device, and the bonding of the array substrate and the color filter substrate is performed. Is achieved through a bonding key formed on the array substrate and the color filter substrate.

Although many details are set forth in the foregoing description, it should be construed as an illustration of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

As described above, in the method of manufacturing the liquid crystal display according to the present invention, the active pattern and the storage electrode can be formed in one mask process by using diffraction exposure. As a result, the number of masks used for manufacturing the thin film transistor is reduced, thereby reducing the manufacturing process and cost.

In addition, the manufacturing method of the liquid crystal display device according to the present invention patterning the data line at the same time when the gate wiring patterning, patterning the source electrode and the drain electrode and depositing a transparent conductive material directly on the pixel electrode to form a pixel electrode The reduction provides a more simplified manufacturing process.

In addition, the manufacturing method of the liquid crystal display according to the present invention provides an effect of increasing the luminance by improving the aperture ratio.

Claims (18)

Providing a first substrate divided into a pixel portion and a circuit portion of the first and second regions; Forming an active pattern made of a silicon thin film and a first gate insulating layer on the pixel portion and the circuit portion through one mask process, and forming a storage electrode made of a conductive material on a predetermined region of the active pattern of the pixel portion; Forming a second gate insulating film on the first substrate on which the active pattern, the first gate insulating film, and the storage electrode are formed; Forming a gate electrode on a circuit portion of the first region where the second gate insulating film is formed, and forming a p + source / drain region on a predetermined region of an active pattern of the circuit portion of the first region; A gate electrode and a gate line are formed in the pixel portion on which the second gate insulating film is formed and the circuit portion of the second region, and are disconnected to the upper and lower portions with the common line and the gate line and the common line interposed therebetween; Forming a lower data line; Forming an n + source / drain region in a predetermined region of an active pattern of the pixel portion and the circuit portion of the second region; Forming a second insulating film on the first substrate on which the n + source / drain region is formed; Partial regions of the first gate insulating layer, the second gate insulating layer, and the second insulating layer may be removed to form first and second contact holes exposing source and drain regions of the active pattern; Forming a third contact hole and a fourth contact hole to expose a portion of the disconnected upper data line and the lower data line by removing a partial area; Source and drain electrodes electrically connected to the source and drain regions of the active pattern through the first and second contact holes, and the upper data through the third and fourth contact holes. Forming a connection line electrically connecting the line and the lower data line; Providing a second substrate; And And attaching the first substrate and the second substrate to each other. delete delete delete The method of claim 1, wherein the gate electrode is formed in the circuit portion of the first region, and the p + source / drain region is formed in a predetermined region of an active pattern of the circuit portion of the first region. Forming a first conductive film on the first substrate on which the second gate insulating film is formed; Covering all of the pixel portion and the circuit portion of the second region and a portion of the circuit portion of the first region with a first blocking layer; Selectively removing the first conductive layer using the first blocking layer as a mask to form a gate electrode in a circuit portion of the first region; And And implanting a high concentration of p + ions into the circuit portion of the first region using the gate electrode as a mask to form a p + source / drain region in a predetermined region of the active pattern of the first region. Manufacturing method. 2. The drain line of claim 1, wherein the common line overlaps the lower storage electrode with the second gate insulating layer interposed therebetween to form a first storage capacitor, and the drain electrode therebetween is disposed with the second insulating layer interposed therebetween. A method of manufacturing a liquid crystal display device, wherein a second storage capacitor is formed to overlap with a portion. delete The semiconductor device of claim 5, wherein a gate electrode and a gate line are formed in a circuit portion of the pixel portion and the second region, and the image lines are disconnected up and down with a common line and the gate line and a common line interposed therebetween. Forming the lower data line Covering all of the circuit portion of the first region and a portion of the circuit portion of the pixel portion and the second region with a second blocking film; And Selectively removing the first conductive layer below the second blocking layer using a mask to form a gate electrode and a gate line formed of the first conductive layer in the circuit portion of the pixel portion and the second region, and common to the pixel portion. And forming upper and lower data lines, which are disconnected to the upper and lower sides with a line and the gate line and the common line interposed therebetween. 10. The method of claim 8, wherein the gate electrode, the gate line, the common line and the upper and lower data lines of the pixel portion and the circuit portion of the second region are over-etched with the first conductive layer by wet etching. The manufacturing method of the liquid crystal display device, characterized in that the width is reduced compared to the blocking film. 9. The method of claim 8, wherein after removing the second blocking film, a low concentration of n- ions are implanted using the gate electrode as a mask to form an LED region in a predetermined region of the active pattern of the pixel portion and the second region. A method of manufacturing a liquid crystal display device. The method of claim 1, wherein the second insulating layer is formed of a single layer of a silicon nitride layer or a double layer including a silicon nitride layer. delete The method of claim 1, wherein the second contact hole of the pixel portion simultaneously exposes a portion of the storage electrode and a portion of the drain region under the pixel portion. The method of claim 1, wherein after forming the source electrode, the drain electrode, and the connection line as a second conductive layer, forming a third insulating layer on the first substrate, and removing a portion of the third insulating layer to remove the pixel. And forming a fifth contact hole exposing a part of the negative drain electrode and forming a pixel electrode electrically connected to the drain electrode through the fifth contact hole. Manufacturing method. 15. The method of claim 14, wherein the pixel electrode overlaps a portion of the gate line and the data line. The method of claim 15, wherein the third insulating film is made of an organic material of benzocyclobutene or acrylic resin. The method of claim 1, further comprising: forming a third conductive film on an entire surface of the first substrate on which the source electrode and the drain electrode are formed, and forming a pixel electrode directly connected to the drain electrode by patterning the third conductive film. Method of manufacturing a liquid crystal display device comprising a. 18. The liquid crystal display of claim 17, further comprising patterning the third conductive layer to form a source electrode pattern, a drain electrode pattern, and a connection line pattern covering the source electrode, the drain electrode, and the connection line. Method of manufacturing the device.

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