KR20110016201A - Method of manufacturing liquid crystal display device - Google Patents

Abstract

PURPOSE: A method of manufacturing a liquid crystal display device is provided to form a contact hole forming process and a common electrode forming process which is exposed to a dram electrode through one mask process. CONSTITUTION: The first and the second active pattern are respectively formed on a P channel thin film transistor forming area and a N channel thin film transistor forming area of a substrate by using the first mask process. The first gate electrode(108d) is formed on P channel thin film transistor forming area of the substrate by using the second mask process. The second gate electrode is formed on an N channel thin film transistor forming area of the substrate by using the third mask process. The second contact hole which exposes an N drain area and a P drain area and the first contact hole which exposes an N source area and a P source area are formed by using the fourth mask process. An N source electrode and a P source electrode are formed to connect the N source area and the P source area and the N source electrode and the P source electrode are formed on connecting the N drain are and the P drain area by using the fifth mask process. The third contact hole and a common electrode are formed on the same time by using the sixth mask process. The fourth contact hole which exposes the N drain electrode and the P drain electrode is formed by using the seventh mask process. A pixel electrode is formed by using eighth mask process.

Description

Method of manufacturing liquid crystal display device

The present invention relates to a method of manufacturing a liquid crystal display device.

In today's information society, display is more important as a visual information transmission medium, and in order to preoccupy a major position in the future, it is necessary to satisfy requirements such as low power consumption, thinness, light weight, and high definition. Liquid Crystal Display (LCD), the flagship product of Flat Panel Display (FPD), has not only the ability to satisfy these conditions of the display but also mass production. It has been established as a core parts industry that can gradually replace the existing cathode ray tube (CRT).

In general, a liquid crystal display device displays a desired image by individually supplying data signals according to image information to liquid crystal cells arranged in a matrix form to adjust a light transmittance of the liquid crystal cells. to be.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be. In particular, the amorphous silicon thin film transistor has been actively used because it is possible to use a low-cost insulating substrate to enable a low temperature process.

However, the electrical mobility (˜1 cm 2 / V sec) of the amorphous silicon thin film transistor is limited to use in peripheral circuits requiring high-speed operation of 1 MHz or more. As a result, studies are being actively conducted to simultaneously integrate the pixel portion and the driving circuit portion on a glass substrate by using a polycrystalline silicon (poly-Si) thin film transistor having a larger field effect mobility than the amorphous silicon thin film transistor. It's going on.

Increasing the mobility may improve the operating frequency of the driving circuit unit that determines the number of driving pixels, thereby facilitating high definition of the display device. In addition, due to the reduction in the charging time of the signal voltage of the pixel, the distortion of the transmission signal may be reduced, thereby improving image quality.

In addition, the polycrystalline silicon thin film transistor can be operated at less than 10V compared to the amorphous silicon thin film transistor having a high driving voltage (~ 25V) has the advantage that the power consumption can be reduced.

FIG. 1 is a plan view schematically illustrating a structure of a general liquid crystal display device, and illustrates a driving circuit-integrated liquid crystal display device in which a driving circuit unit is integrated on an array substrate.

As shown in the figure, the liquid crystal display is largely composed of a color filter substrate 5 and an array substrate 10 and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10. .

The array substrate 10 includes a pixel portion 35, which is an image display area in which unit pixels are arranged in a matrix, and a data driving circuit portion 31 and a gate driving circuit portion 32 positioned outside the pixel portion 35. It consists of a driving circuit section (30).

In this case, although not shown in the drawing, the pixel portion 35 of the array substrate 10 is arranged on the substrate 10 vertically and horizontally to define a plurality of gate lines, data lines, the gate lines and the like. A thin film transistor, which is a switching element formed in an intersection region of a data line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching device that applies and cuts off a signal voltage to the pixel electrode and controls the flow of current by an electric field.

The driving circuit part 30 of the array substrate 10 is located outside the pixel portion 35 of the array substrate 10 protruding from the color filter substrate 5, and one side of the protruding array substrate 10. The data driving circuit part 31 is positioned at a long side, and the gate driving circuit part 32 is positioned at one end side of the protruding array substrate 10.

In this case, the data driving circuit 31 and the gate driving circuit 32 use a thin film transistor having a complementary metal oxide semiconductor (CMOS) structure, which is an inverter, in order to properly output an input signal.

For reference, the CMOS is an integrated circuit having an MOS structure which is used in a thin film transistor for driving circuits requiring high speed signal processing, and requires both an N-channel thin film transistor and a P-channel thin film transistor. It shows the intermediate form of PMOS.

The gate driving circuit unit 32 and the data driving circuit unit 31 are devices for supplying a scan signal and a data signal to the pixel electrode through the gate line and the data line, respectively, and are connected to an external signal input terminal (not shown). It controls the external signal input through the external signal input terminal to output to the pixel electrode.

In addition, a color filter (not shown) for implementing color and a common electrode (not shown), which is an opposite electrode of the pixel electrode formed on the array substrate 10, are formed in the pixel part 35 of the color filter substrate 5. have.

The color filter substrate 5 and the array substrate 10 configured as described above are provided with a cell gap so as to be uniformly spaced apart by a spacer (not shown), and formed on the outer side of the pixel portion 35. They are bonded together by a seal pattern (not shown) to form a unit liquid crystal display panel. At this time, the two substrates 5 and 10 are bonded to each other through a bonding key formed on the color filter substrate 5 or the array substrate 10.

The manufacturing process of the liquid crystal display device configured as described above basically requires a number of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor. There is a need for ways to reduce it.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as a photoresist coating, exposure, and development process. It has the disadvantage of dropping.

In particular, since the mask designed to form the pattern is very expensive, as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the number of masks used in the manufacture of a thin film transistor by forming a contact hole forming process for exposing a drain electrode and a common electrode forming process through a single mask process. To provide a method of manufacturing.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display device capable of improving side profile of a gate electrode during a gate electrode forming process.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method including providing a substrate divided into a P-channel thin film transistor forming region and an N-channel thin film transistor forming region, and using the first mask process. Forming first and second active patterns on the P-channel thin film transistor formation region and the N-channel thin film transistor formation region of the substrate; and forming a first insulating film and a first conductive film on the substrate on which the first and second active patterns are formed. And forming a first gate electrode formed of the first conductive layer in the P-channel thin film transistor forming region of the substrate using a second mask process, and forming a P drain region and a P source region in the first active pattern. Forming the P drain region, the P channel region, and the p-LDD region, and forming a N-channel thin film transistor of the substrate using a third mask process. Forming a second gate electrode formed of the first conductive layer in a region, and forming an N drain region, an N source region, the N drain region, an N channel region, and an n-LDD region in the second active pattern; And forming a second insulating film on the substrate on which the N drain region, the N source region, the N channel region, and the n-LDD region are formed, and selectively removing the first and second insulating layers using a fourth mask process. Forming a first contact hole exposing portions of the N source region and the P source region, and a second contact hole exposing portions of the N drain region and the P drain region, respectively; And forming a second conductive layer on the substrate on which the second contact hole is formed, and an N source electrode electrically connected to the N source region and the P source region through the first contact hole using a fifth mask process. And P Forming a drain electrode and forming an N drain electrode and a P drain electrode electrically connected to the N drain region and the P drain region through a second contact hole, and a substrate on which the N drain electrode and the P drain electrode are formed Forming a third insulating film and a third conductive film thereon, forming a third contact hole penetrating the third insulating film using a sixth mask process, and forming a common electrode on the third insulating film; Forming a fourth insulating film on the substrate on which the third contact hole and the common electrode are formed, and exposing the N drain electrode and the P drain electrode through the fourth insulating film by using a seventh mask process. Forming a fourth contact hole, forming a fourth conductive layer on the substrate on which the fourth contact hole is formed, and forming an N-drain electrode through the fourth contact hole using an eighth mask process. And forming a pixel electrode respectively connected to the P drain electrode, wherein the first gate electrode is formed, and a P drain region, a P source region, a P channel region, and a p-LDD region are formed in the first active pattern. The forming may include forming a first photoresist pattern formed on the first conductive layer through the second mask process, and dry etching the first photoresist pattern on the first conductive layer using an etching mask. Forming a gate electrode pattern, performing a wet etching process on the substrate on which the gate electrode pattern is formed, to form a first gate electrode, and using the first photoresist pattern as a mask on the entire surface of the substrate; Ion implantation to form the P drain region and the P source region in a predetermined region of the first active pattern, and between the P drain region and the P source region Forming a P channel region, removing the first photoresist pattern, implanting ions into the entire surface of the substrate using the first gate electrode as a mask, and forming the P channel region and the P drain of the first active pattern. Forming a p-LDD region between regions and between the P channel region and the P source region.

Forming the second gate electrode, and forming the P drain region, the P source region, the P channel region, and the p-LDD region in the second active pattern may include a second photoresist pattern formed through the third mask process. Forming a gate electrode pattern on the first conductive layer, performing a dry etching process on the first conductive layer using the second photoresist pattern as an etching mask, and forming the gate electrode pattern. Performing a wet etching process on a substrate to form a second gate electrode, implanting ions into the entire surface of the substrate using the second photoresist pattern as a mask, and forming the N drain region and the N in a predetermined region of the second active pattern. Forming a source region, forming the N channel region between the N drain region and the P source region, and removing the second photoresist pattern And forming an n-LDD region between the N channel region and the N drain region and between the N channel region and the N source region by implanting ions into the entire surface of the substrate using the second gate electrode as a mask. .

The forming of the third contact hole penetrating the third insulating film using the sixth mask process and forming the common electrode on the third insulating film may be performed on the substrate on which the third insulating film and the third conductive film are formed. Forming a third photoresist pattern using a sixth mask, and performing an exposure process on the substrate on which the third photoresist pattern is formed, penetrating through the third conductive layer, and exposing a portion of the third insulating layer to be exposed. Forming a region, removing the exposed third conductive film using the third photoresist pattern as a mask, and performing a developing process on a substrate on which the third conductive film from which the portion is removed is formed; Developing an exposure region of the insulating layer to form a third contact hole exposing the N drain electrode and the P drain electrode, respectively, and ashing the third photoresist pattern. A fourth step of forming a photoresist pattern, and the fourth photo-resist pattern as a mask and forming a common electrode by removing the exposed third conductive film.

The sixth mask is a diffraction mask including a transmissive region, a transflective region, which is a slit region, and a blocking region.

The blocking region is disposed in a region where the common electrode is to be formed, the transmission region is disposed in a region where the third contact hole is to be formed, and the transflective region is a region in which the common electrode is to be formed and a third contact hole. It is disposed in the region between the regions to be formed.

In the fourth photoresist pattern, photoresist remains only in a region where the common electrode is to be formed, and photoresist is removed in a region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed.

As described above, the manufacturing method of the liquid crystal display device according to the present invention reduces the number of masks used in the manufacture of the thin film transistor by forming the contact hole forming process and the common electrode forming process exposing the drain electrode through one mask process. It works.

In the method of manufacturing the liquid crystal display device according to the present invention as described above, the gate electrode is formed by sequentially performing a dry etching process and a wet etching process, so that a side profile of the gate electrode is improved, thereby providing a substrate 100. The CD of the gate electrode formed at the center of the gate electrode and the CD of the gate electrode formed at the edge portion are uniform, and staining is minimized due to the removal of the remaining conductive film.

Hereinafter, a manufacturing method of a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

2A to 2H are process flowcharts sequentially illustrating a method of manufacturing a liquid crystal display device according to the present invention, and FIGS. 3A to 3F are views illustrating a contact hole forming process and a common electrode forming process exposing the drain electrode shown in FIG. 2F. 4A through 4E are detailed flowcharts illustrating the process of forming the gate electrode, the drain region, the source region, and the lightly doped drain (LDD) region illustrated in FIGS. 2B and 2C.

2A to 2H and 3A to 3F are cross-sectional views sequentially illustrating a method of manufacturing an array substrate, and an example of a process of manufacturing an array substrate on which an N-channel thin film transistor and a P-channel thin film transistor are formed. . Meanwhile, the N-channel thin film transistor and the P-channel thin film transistor may be formed in both the driving circuit part and the pixel part.

In addition, although the embodiment of the present invention describes a liquid crystal display device of In Plane Switching (IPS) as an example, the present invention is not limited thereto.

As shown in FIG. 2A, a buffer layer 102 and a silicon thin film are formed on a substrate 100 made of a transparent insulating material such as glass, and then the silicon thin film is crystallized to form a polycrystalline silicon thin film.

The substrate 100 is defined as a thin film transistor forming region of an N channel and a thin film transistor forming region of a P channel.

In this case, the buffer layer 102 serves to block impurities such as sodium (natrium) from the substrate 100 from penetrating into the upper layer during the process.

In this case, the case where the polycrystalline silicon thin film is used as the semiconductor layer of the thin film transistor has been described, for example. However, the present invention is not limited thereto, and an amorphous silicon thin film may be used as the semiconductor layer of the thin film transistor.

In addition, the polycrystalline silicon thin film may be formed using various crystallization methods after depositing an amorphous silicon thin film on the substrate 100. This will be described below.

First, an amorphous silicon thin film may be formed by depositing in various ways. Representative methods of depositing the amorphous silicon thin film may include low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (Plasma Enhanced). Chemical Vapor Deposition (PECVD) method.

As a method of crystallizing the amorphous silicon thin film, there are largely a solid phase crystallization (SPC) method for heat treating the amorphous silicon thin film in a high temperature furnace and an excimer laser annealing (ELA) method using a laser. .

As the laser crystallization, an excimer laser annealing method using a pulse-type laser is mainly used, but in recent years, sequential lateral solidification (SLS) in which grains are grown in a horizontal direction to improve crystallization characteristics. The method is being studied.

In addition, a first photoresist pattern (not shown) is formed on the polycrystalline silicon thin film through a first mask process, and the polycrystalline silicon thin film is patterned using the same to form an N-channel thin film transistor forming region A of the substrate 100. First and second active patterns 104a and 104b are formed in the P-channel thin film transistor forming region B, respectively.

Subsequently, as illustrated in FIG. 2B, the first insulating layer 106 and the first conductive layer 108a are formed on the entire surface of the substrate 100 on which the first and second active patterns 104a and 104b are formed.

The first conductive layer 108a may be formed of aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), or the like to form a gate electrode. It may be made of a low resistance opaque conductive material such as molybdenum (Mo).

Subsequently, a second photoresist pattern (not shown) is formed through a second mask process, and the first conductive layer 108a is selectively patterned using the second photoresist pattern (not shown), thereby forming a P-channel thin film transistor formation region of the substrate 100. The first gate electrode 108d is formed in B), and the P drain region 105a, the P source region 105b, the P channel region 104bc1, and p− are formed using the first gate electrode 108d as a mask. LDD (Lightly Doped Drain) region 105c is formed.

Next, a method of forming the first gate electrode 108d, the P drain region 105a and the P source region 105b, the P channel region 104bc1, and the lightly doped drain (pLD) region 105c is described. 4A to 4E will be described in more detail.

First, as shown in FIG. 4A, the second photoresist pattern 201a formed through the second mask process is formed on the first conductive layer 108a and the second photoresist pattern 201a is etched. The gate electrode pattern 108b is formed by performing a dry etching process on the first conductive layer 108a.

Subsequently, as shown in FIG. 4B, the first gate electrode 108d is formed by performing a wet etching process on the substrate 100 on which the gate electrode pattern 108b is formed.

In this case, the dry etching process etches about 2/3 of the thickness to be etched, and the wet etching process etches about 1/3 of the thickness to be etched. Thus, after the dry etching process is etched by the main etching process to determine the shape of the gate electrode, the tail of the conductive film which may be generated during the dry etching process by the wet etching process by the sub etching process. The same remaining conductive film is etched and removed.

Therefore, when the dry etching process and the wet etching process are sequentially performed to form the gate electrode 108d, the side profile of the gate electrode is improved, so that the gate electrode is formed in various places of the substrate 100, that is, in the center. The CD of the gate electrode and the CD of the gate electrode formed at the edge portion become uniform, and staining is minimized due to the removal of the remaining conductive film.

Next, as shown in FIG. 4C, a high concentration of p + ions are implanted into the entire surface of the substrate 100 using the second photoresist pattern 201a as a mask to drain P in a predetermined region of the second active pattern 104b. The region 105a and the P source region 105b are formed. At this time, a P channel region 104bc1 forming a conductive channel is formed between the P drain region 105a and the P source region 105b.

Subsequently, as illustrated in FIG. 4D, a stripping process for removing the second photoresist pattern 201a is performed.

Next, as shown in FIG. 4E, a low concentration of p-ion is implanted onto the substrate 100 from which the second photoresist pattern 201a has been removed, thereby forming a gap between the P channel region 104bc1 and the P drain region 105a. And a p-LDD (Lightly Doped Drain) region 105c is formed between the P channel region 104bc1 and the P source region 105b.

In the ion implantation process of implanting the low concentration of p-ion, the gate electrode pattern 108c is used as an ion implantation mask by using the first gate electrode 108d having a line width smaller than the gate electrode pattern 108c as an ion implantation mask. A lightly doped drain (p-LDD) region 105c is formed in the second active pattern 104b that is formed inside the P drain region 105a and the P source region 105b.

Further, due to the first conductive layer 108a formed in the N-channel thin film transistor formation region A, the high concentration and low concentration of p + ions and p- ions implanted into the P-channel thin film transistor formation region B are N-channel. Injection into the thin film transistor forming region A is prevented.

Next, as shown in FIG. 2C, a third photoresist pattern (not shown) is formed through a third mask process, and the first conductive layer 108a formed in the N-channel thin film transistor formation region A is formed using the third photoresist pattern. Is formed to form a second gate electrode 108c in the N-channel thin film transistor formation region A of the substrate 100, and the N-drain region 107a is formed using the second gate electrode 108c as a mask. An N source region 107b, an N channel region 104bc2, and an n-LDD (Lightly Doped Drain) region 107c are formed. In this case, the second gate electrode 108c, the drain region 107a and the N source region 107b, the N channel region 104bc2, and the n-LDD (lightly doped drain) region 107c are illustrated in FIGS. 4A through 4E. In the same manner as the method of forming the first gate electrode 108d, the P drain region 105a and the P source region 105b, the P channel region 104bc1, and the lightly doped drain region p-LDD (105c). do.

Next, as shown in FIG. 2D, after the second insulating film 110 is formed on the entire surface of the substrate 100, a fourth photoresist pattern (not shown) is formed through the fourth mask process and then used. First contact holes 112a and N drains that selectively remove portions of the first and second insulating layers 106 and 110 to expose portions of the N source region 105b and the P source region 107b, respectively. Second contact holes 112b exposing portions of the region 105a and the P drain region 107a are formed.

The second insulating layer 110 may be a double layer of silicon nitride (SiNx) / silicon oxide layer (SiO ₂ ), and may be variously applied to a single layer of SiNx or a triple layer of SiO ₂ / SiNx / SiO ₂ . have.

Next, as shown in FIG. 2E, after forming the second conductive layer on the entire surface of the substrate 100 on which the first and second contact holes 112a and 112b are formed, the fifth photoresist pattern is formed through a fifth mask process. An N source electrode electrically connected to the N source region 105b and the P source region 107b through the first contact hole 112a by forming (not shown) and selectively patterning the second conductive layer using the same. 114 a) and a P source electrode 115 a, and the N drain electrode 114 b and the P drain electrode electrically connected to the N drain region 105 a and the P drain region 107 a through the second contact hole 112 b. Form 115b.

The second conductive layer may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, etc. to form the source and drain electrodes.

Next, as illustrated in FIG. 2F, a third insulating layer (not shown) may be formed on the substrate 100 on which the N source electrode 114a, the P source electrode 115a, the N drain electrode 114b, and the P drain electrode 115b are formed. 116, after sequentially forming the third conductive film, by forming a sixth photoresist pattern (not shown) through a sixth mask process and selectively patterning the third insulating film 116 and the third conductive film using the same, A third contact hole 117a penetrating through the third insulating layer 116 is formed, and a common electrode 118c is formed on the third insulating layer 116.

As the third insulating layer 116, an organic insulating material such as an acryl-based organic compound, BCB, or PFCB is used, and the third conductive layer may be formed of indium tin oxide or indium zinc oxide to form the common electrode. The same transmittance may be made of a transparent conductive material.

Next, a method of forming the third contact hole 117a and the common electrode 118c through the sixth mask process will be described in more detail with reference to FIGS. 3A through 3F.

First, as shown in FIG. 3A, the sixth photoresist pattern 200a is formed on the substrate 100 on which the third insulating layer 116 and the third conductive layer 118a are sequentially formed through a sixth mask process. .

In this case, the sixth photoresist pattern 200a is formed by a photo process using a sixth mask (not shown) after forming a photoresist on the third conductive layer 118a. In this case, the sixth mask is a diffraction mask having three different transmittances, including a transmissive region for transmitting light, a semi-transmissive region for transmitting a portion of light and blocking a portion of the light, and a blocking region for blocking light. Use The photoresist remains as it is in the blocking region. The photoresist remains in a semi-transmissive region at a thickness lower than that of the blocking region, and no photoresist remains in the transmissive region.

Therefore, in the sixth photoresist pattern 200a, the region where the common electrode is to be formed is disposed in the blocking region, so that the photoresist remains as it is, and the region in which the third contact hole is to be formed is disposed in the transmission region, so that the photoresist remains. As a result, the third conductive layer 118a is exposed, and the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed is disposed in the semi-transmissive region and thus remains at a thickness lower than that of the photoresist of the blocking region.

Subsequently, an exposure process is performed on the substrate 100 on which the sixth photoresist pattern 200a is formed to expose the third insulating layer 116 that passes through the third conductive layer, which is a transparent conductive layer, and corresponds to a region where a contact hole is to be formed. The exposure area R is formed.

3B, the exposed third conductive film 118a is removed using the sixth photoresist pattern 200a as a mask (the reference number of the third conductive film left after being removed is 118b).

Next, as illustrated in FIG. 3C, a developing process is performed on the substrate 100 from which a portion of the third conductive film 118a is removed to develop and remove the exposure area R of the third insulating film 116. As a result, a fourth contact hole 117a exposing the N drain electrode 105a and the P drain electrode 107a is formed.

Next, as shown in FIG. 3D, the sixth photoresist pattern 200a is ashed to form the seventh photoresist pattern 200b.

In the seventh photoresist pattern 200b, the photoresist remains only in the region where the common electrode is to be formed, and the photoresist is removed in the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed. to be. As a result, the third conductive layer 118b formed in the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed is exposed.

3E, the exposed third conductive film 118b is removed using the seventh photoresist pattern 200b as a mask (the reference number of the third conductive film remaining after removal is 118c, It becomes a common electrode).

Next, as shown in FIG. 3f, the seventh photoresist pattern 200b is removed through a strip process. As a result, the third contact hole 117a and the common electrode 118c may be simultaneously formed through a sixth mask process using three masks having three different transmittances.

Subsequently, as illustrated in FIG. 2G, a fourth insulating layer 120 is formed on the substrate 100 on which the third contact hole 117a and the common electrode 118 are formed, and the eighth photoresist is formed through a seventh mask process. By forming a pattern (not shown) and selectively removing the fourth insulating layer 120 by using the same, the agent exposing each of the N drain electrode 114b and the P drain electrode 115b through the fourth insulating layer 120. Five contact holes 117b are formed.

In the present embodiment, the fifth contact hole 117b is formed at the same position as that of the third contact hole 117a, and the size of the fifth contact hole 117b is the size of the third contact hole 117a. It is formed smaller. That is, since the fifth contact hole 117b is formed by selectively removing the fourth insulating layer 120 deposited inside the third contact hole 117a, the fifth contact hole 117b is different from the formation position of the third contact hole and at the same time the size of the third contact hole. If it becomes larger, since the third insulating film 116 as well as the fifth insulating film 120 must be removed, the process difficulty increases.

Next, as shown in FIG. 2H, after forming the fourth conductive layer on the entire surface of the substrate 100 on which the fifth contact hole 120 is formed, the ninth photoresist pattern (not shown) is formed through an eighth mask process. By forming and selectively patterning the fourth conductive layer using the same, the pixel electrode 120 electrically connected to the N drain electrode 114b and the P drain electrode 115b through the fifth contact hole 117b is formed.

In this case, the fourth conductive layer may be made of a transparent conductive material having excellent transmittance such as indium tin oxide or indium zinc oxide to form the pixel electrode.

The array substrate according to the embodiment of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outer side of the image display area. Black matrix to prevent leakage and color filter for red, green and blue color are formed.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

In this case, the present invention can be used not only in liquid crystal display devices, but also in other display devices manufactured using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is a plan view schematically showing the structure of a general liquid crystal display device

2A to 2H are process flowcharts sequentially illustrating a method of manufacturing a liquid crystal display device according to the present invention;

3A to 3F are process flowcharts showing in detail a contact hole forming process and a common electrode forming process exposing the drain electrode disclosed in FIG. 2F;

4A through 4E are flowcharts illustrating a method of forming a gate electrode, a drain region and a source region, a channel region, and a lightly doped drain (LDD) region according to the present invention.

Claims (6)

Providing a substrate divided into a P-channel thin film transistor forming region and an N-channel thin film transistor forming region; Forming first and second active patterns on each of the P-channel thin film transistor formation region and the N-channel thin film transistor formation region of the substrate using a first mask process; Forming a first insulating film and a first conductive film on the substrate on which the first and second active patterns are formed; A first gate electrode made of the first conductive layer is formed in the P-channel thin film transistor forming region of the substrate using a second mask process, and the P drain region, the P source region, and the P drain region are formed in the first active pattern. Forming a P channel region and a p-LDD region; A second gate electrode made of the first conductive layer is formed in an N-channel thin film transistor forming region of the substrate using a third mask process, and an N drain region, an N source region, and an N drain region in the second active pattern. Forming an N channel region and an n-LDD region; Forming a second insulating film on the substrate on which the N drain region, the N source region, the N channel region, and the n-LDD region are formed; A first contact hole exposing a portion of the N source region and the P source region by selectively removing the first and second insulating layers using a fourth mask process, and of the N drain region and the P drain region, respectively. Forming second contact holes each exposing a portion; Forming a second conductive film on the substrate on which the first and second contact holes are formed; A N source electrode and a P source electrode electrically connected to the N source region and the P source region through the first contact hole using a fifth mask process, and the N drain region and the second contact hole; Forming an N drain electrode and a P drain electrode electrically connected to the P drain region; Forming a third insulating film and a third conductive film on the substrate on which the N drain electrode and the P drain electrode are formed; Forming a third contact hole penetrating the third insulating film by using a sixth mask process and forming a common electrode on the third insulating film; Forming a fourth insulating film on the substrate on which the third contact hole and the common electrode are formed; Forming a fourth contact hole penetrating the fourth insulating layer to expose the N drain electrode and the P drain electrode by using a seventh mask process; Forming a fourth conductive film on the substrate on which the fourth contact hole is formed; Forming a pixel electrode connected to the N drain electrode and the P drain electrode through the fourth contact hole using an eighth mask process; Forming the first gate electrode and forming a P drain region, a P source region, a P channel region, and a p-LDD region in the first active pattern Forming a first photoresist pattern formed through the second mask process on the first conductive layer; Forming a gate electrode pattern by performing a dry etching process on the first conductive layer using the first photoresist pattern as an etching mask; Forming a first gate electrode by performing a wet etching process on the substrate on which the gate electrode pattern is formed; Ion implanting the entire surface of the substrate using the first photoresist pattern as a mask to form the P drain region and the P source region in a predetermined region of the first active pattern, and between the P drain region and the P source region. Forming a channel region, Removing the first photoresist pattern; Ion-implanting the entire surface of the substrate using the first gate electrode as a mask to form a p-LDD region between the P channel region and the P drain region of the first active pattern and between the P channel region and the P source region Method of manufacturing a liquid crystal display device comprising the step. The method of claim 1, wherein forming the second gate electrode and forming a P drain region, a P source region, a P channel region, and a p-LDD region in the second active pattern is performed. Forming a second photoresist pattern formed through the third mask process on the first conductive layer; Forming a gate electrode pattern by performing a dry etching process on the first conductive layer using the second photoresist pattern as an etching mask; Forming a second gate electrode by performing a wet etching process on the substrate on which the gate electrode pattern is formed; Ion implanting the entire surface of the substrate using the second photoresist pattern as a mask to form the N drain region and the N source region in a predetermined region of the second active pattern, and between the N drain region and the P source region. Forming a channel region, Removing the second photoresist pattern; Ion-implanting the entire surface of the substrate using the second gate electrode as a mask to form an n-LDD region between the N channel region and the N drain region and between the N channel region and the N source region. A method of manufacturing a liquid crystal display device. The method of claim 1, wherein forming a third contact hole penetrating the third insulating layer using the sixth mask process and forming a common electrode on the third insulating layer is performed. Forming a third photoresist pattern on the substrate on which the third insulating film and the third conductive film are formed by using the sixth mask; Performing an exposure process on the substrate on which the third photoresist pattern is formed to penetrate the third conductive layer and expose a portion of the third insulating layer to form an exposure region; Removing the exposed third conductive layer using the third photoresist pattern as a mask; Performing a developing process on a substrate on which the third conductive film is partially removed, thereby developing an exposure region of the third insulating film to form a third contact hole exposing the N drain electrode and the P drain electrode, respectively; Ashing the third photoresist pattern to form a fourth photoresist pattern; And removing the exposed third conductive layer using the fourth photoresist pattern as a mask to form a common electrode. The method of claim 3, wherein the sixth mask is A diffraction mask comprising a transmissive region, a transmissive region as a slit region, and a blocking region. 5. The method of claim 4, The blocking region is disposed in a region where the common electrode is to be formed, the transmission region is disposed in a region where the third contact hole is to be formed, and the transflective region is a region in which the common electrode is to be formed and a third contact hole. A method for manufacturing a liquid crystal display device, characterized in that disposed in the region between the region to be formed. The method of claim 3, wherein the fourth photoresist pattern is The photoresist remains only in the region where the common electrode is to be formed, and the photoresist is removed in the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed. .

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