KR101301520B1 - Method of fabricating liquid crystal display device - Google Patents

Abstract

The method for manufacturing a liquid crystal display device according to the present invention includes a mask for forming a semiconductor layer and a storage pattern, a mask for forming a gate electrode in a P-type TFT region, a mask for forming a gate electrode and an LDD layer in an N-type TFT region, a mask for opening a protective layer, and Only five masks, such as a source electrode and a drain electrode forming mask, are needed, which greatly simplifies the manufacturing process.

Liquid crystal, mask, storage, pixel electrode, LDD

Description

Liquid crystal display manufacturing method {METHOD OF FABRICATING LIQUID CRYSTAL DISPLAY DEVICE}

1 is a plan view briefly showing the structure of a conventional liquid crystal display.

2A to 2M are cross-sectional views showing a method for manufacturing a liquid crystal display device according to the present invention.

3 is a plan view showing the structure of a liquid crystal display device manufactured by a manufacturing method according to the present invention;

Description of the Related Art [0002]

110 substrate 116 semiconductor pattern

117: pixel electrode 119: barrier metal layer

113: source electrode 114: drain electrode

128: storage pattern

The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a liquid crystal display device by reducing the number of masks to simplify the manufacturing process and improve the yield.

In today's information society, display is more important as a visual information transmission medium, and in order to gain a major position in the future, it is necessary to satisfy requirements such as low power consumption, thinness, light weight, and high definition. Liquid Crystal Display (LCD), the flagship product of Flat Panel Display (FPD), has not only the ability to satisfy these conditions of the display but also mass production. It has been established as a core parts industry that can gradually replace the existing cathode ray tube (CRT).

In general, a liquid crystal display device displays a desired image by individually supplying data signals according to image information to liquid crystal cells arranged in a matrix form to adjust a light transmittance of the liquid crystal cells. to be.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

Amorphous silicon thin film transistor technology was established in 1979 by LeComber et al., UK, and was commercialized as a 3 "liquid crystal portable television in 1986. Recently, a large area thin film transistor liquid crystal display device of 50" or more has been developed. In particular, the amorphous silicon thin film transistor has been actively used because it is possible to use a low-cost insulating substrate to enable a low temperature process.

However, the electrical mobility (˜1 cm ² / Vsec) of the amorphous silicon thin film transistor is limited to use in peripheral circuits requiring high-speed operation of 1 MHz or more. As a result, studies are being actively conducted to simultaneously integrate the pixel portion and the driving circuit portion on a glass substrate by using a polycrystalline silicon (poly-Si) thin film transistor having a larger field effect mobility than the amorphous silicon thin film transistor. It's going on.

Polycrystalline silicon thin film transistor technology has been applied to small modules such as camcorders since liquid crystal color television was developed in 1982, and has the advantage of being able to manufacture driving circuits directly on the board because of its low sensitivity and high field effect mobility. .

Increasing the mobility may improve the operating frequency of the driving circuit unit that determines the number of driving pixels, thereby facilitating high definition of the display device. In addition, due to the reduction in the charging time of the signal voltage of the pixel portion, the distortion of the transmission signal may be reduced, thereby improving image quality.

In addition, the polycrystalline silicon thin film transistor can be driven at less than 10V compared to the amorphous silicon thin film transistor having a high driving voltage (˜25V) has the advantage that the power consumption can be reduced.

Hereinafter, the structure of the liquid crystal display will be described in detail with reference to FIG. 1.

1 is a plan view schematically illustrating a structure of a general liquid crystal display device, and illustrates a driving circuit-integrated liquid crystal display device in which a driving circuit unit is integrated on an array substrate.

As shown in the figure, the liquid crystal display is largely composed of a color filter substrate 5 and an array substrate 10 and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10. .

The array substrate 10 includes a pixel portion 35, which is an image display area in which unit pixels are arranged in a matrix, and a data driving circuit portion 31 and a gate driving circuit portion 32 positioned outside the pixel portion 35. It consists of a driving circuit section (30).

In this case, although not shown in the drawing, the pixel portion 35 of the array substrate 10 is arranged on the substrate 10 vertically and horizontally to define a plurality of gate lines and data lines, the gate lines and A thin film transistor, which is a switching element formed in an intersection region of a data line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching element that applies and cuts off a signal voltage to a pixel electrode and is a type of field effect transistor (FET) that controls the flow of current by an electric field.

The driving circuit part 30 of the array substrate 10 is located outside the pixel portion 35 of the array substrate 10 protruding from the color filter substrate 5, and one side of the protruding array substrate 10. The data driving circuit part 31 is positioned at a long side, and the gate driving circuit part 32 is positioned at one end side of the protruding array substrate 10.

In this case, the data driving circuit 31 and the gate driving circuit 32 use a thin film transistor having a complementary metal oxide semiconductor (CMOS) structure, which is an inverter, in order to properly output an input signal.

For reference, the CMOS is an integrated circuit having an MOS structure which is used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS requires both an n-channel thin film transistor and a p-channel thin film transistor. It shows the intermediate form of PMOS.

The gate driving circuit unit 32 and the data driving circuit unit 31 are devices for supplying a scan signal and a data signal to the pixel electrode through the gate line and the data line, respectively, and are connected to an external signal input terminal (not shown). It controls the external signal input through the external signal input terminal to output to the pixel electrode.

In addition, a color filter (not shown) for implementing color and a common electrode (not shown), which is an opposite electrode of the pixel electrode formed on the array substrate 10, are formed in the pixel part 35 of the color filter substrate 5. have.

The color filter substrate 5 and the array substrate 10 configured as described above are provided with a cell gap so as to be uniformly spaced apart by a spacer (not shown), and a seal formed at an outer portion of the pixel portion 35. The patterns are bonded by a seal pattern (not shown) to form a unit liquid crystal display panel. At this time, the two substrates 5 and 10 are bonded to each other through a bonding key formed on the color filter substrate 5 or the array substrate 10.

The driving circuit-integrated liquid crystal display device configured as described above has the advantage of excellent device characteristics, excellent image quality, high definition, and low power consumption because it uses polycrystalline silicon thin film transistors.

However, since the n-channel thin film transistor and the p-channel thin film transistor must be formed together on the same substrate, the driving circuit-integrated liquid crystal display device is more complicated in manufacturing process than the amorphous silicon thin film transistor liquid crystal display device forming only a single type channel. There are disadvantages.

As such, fabrication of an array substrate including the thin film transistor requires a plurality of photolithography processes.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development. As a result, many photolithography processes have many problems, such as lowering the production yield and increasing the probability of defects in the formed thin film transistors.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a liquid crystal display device which can simplify the manufacturing process.

In order to achieve the above object, the liquid crystal display device manufacturing method according to the present invention comprises the steps of preparing a substrate consisting of a P-type TFT region, an N-type TFT region and a storage region; Stacking a buffer layer, a semiconductor material and a metal on the substrate; Etching the semiconductor material and metal to form a semiconductor layer in a P-type TFT region and an N-type TFT region, and forming a semiconductor layer and a metal layer in a storage region; Forming a p ⁺ layer on the semiconductor layer of the P-type TFT region and forming a gate electrode thereon; Forming an LDD structure on the semiconductor layer of the N-type TFT region and forming a gate electrode thereon; Forming a protective layer and then etching to form a contact hole; Forming a barrier metal layer in the contact hole; And forming a source electrode and a drain electrode in the protective layer and the contact hole.

Hereinafter, a method of manufacturing a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2K are views showing a method of manufacturing a liquid crystal display device according to the present invention. In this case, the driving circuit region and the pixel region in which the driving circuit is formed are illustrated.

First, as shown in FIG. 2A, a substrate made of a transparent insulating material such as glass and including a P-type TFT region (driving circuit region), an N-type TFT region (pixel region) and a storage electrode region (pixel region) After preparing 110, an insulating material, a semiconductor material, and a metal are stacked on the substrate 110 to form a buffer layer 122, a semiconductor layer 116, and a metal layer 128a. In this case, the semiconductor layer 116 may be formed by laminating crystalline silicon with the crystallized semiconductor layer 116 or may be formed by laminating an amorphous semiconductor and crystallizing by applying heat or a laser.

Subsequently, as shown in FIG. 2B, a photoresist layer 140 is applied to the substrate 110 on which the buffer layer 122, the semiconductor layer 116, and the metal layer 128a are formed, and a diffraction mask or halftone is applied thereon. After irradiating ultraviolet rays such as ultraviolet rays in a state where the optical mask 150 such as a mask is positioned, the photoresist patterns 140a and 140b are formed as shown in FIG. 2C. In this case, since the intensity of the diffraction mask, the halftone mask or the transmitted light can be adjusted, the thicknesses of the photoresist patterns 140a and 140b can be adjusted. In the drawing, the thickness of the photoresist pattern in the P-type TFT region and the N-type TFT region is the same, whereas the photoresist pattern in the storage region is thicker than the photoresist pattern in the P-type TFT region and the N-type TFT region. Is formed. In addition, the metal layer 128a in some regions is exposed to the outside.

After that, as shown in FIG. 2C, when the etching liquid or the etching gas is applied while the metal layer 128a and the semiconductor layer 116 are blocked by the photoresist patterns 140a and 140b, the etching solution or the etching gas is shown in FIG. 2D. As described above, the metal layer 128a and the semiconductor layer 116 exposed to the outside are etched so that the metal layer 128a and the semiconductor layer 116 remain only under the photoresist patterns 140a and 140b. Subsequently, when the photoresist patterns 140a and 140b are ashed, the photoresist patterns of the P-type TFT region and the N-type TFT region are removed and only the photoresist pattern 140c of the storage region remains on the metal layer 128. Will be.

As shown in FIG. 2E, when the metal layer 128 is etched while the partial region of the metal layer 128 is locked with the photoresist pattern 140c, the photoresist pattern 140c is removed. As shown in FIG. 2F, only the semiconductor layer 116 remains in the P-type TFT region and the N-type TFT region, and the semiconductor layer 116 and the storage electrode 128 thereon remain in the storage region.

After that, as shown in FIG. 2G, the gate insulating layer 124 is formed over the entire substrate 110 on which the storage electrode 128 is formed. Then, a metal layer is stacked thereon and photo-etched using a mask. The first gate electrode 111a is formed in the P-type TFT region. The first gate electrode 111a serves as a gate electrode of the P-type TFT, and also acts as a mask layer forming the p ⁺ layer of the P-type TFT. That is, when p ⁺ ions are doped using the first gate electrode 111 a as a mask, an intrinsic semiconductor layer without impurities is formed under the first gate electrode 111 a and p ⁺ ions are formed on both sides thereof. A doped p ⁺ layer.

Meanwhile, when the p ⁺ ions are doped as described above, since the N type TFT region and the storage region are covered by the metal layer 111, p ⁺ ions are not doped in the N type TFT region and the storage region.

Subsequently, as shown in FIG. 2H, photoresist is deposited over the entire substrate 110 and then developed using a mask to develop photoresist patterns 141a and 141b on the metal layer 111 of the N-type TFT region and the storage region. Next, the metal layer 111 is etched using the photoresist patterns 141a and 141b to form a second gate electrode 111b and a metal layer 111c. At this time, the second gate electrode 111b of the N-type TFT region is over-etched to have a width smaller than that of the photoresist pattern 141a thereon. As described above, n ⁺ doping is performed over the substrate 110 on which the second gate electrode 111b, the metal layer 111c, and the photoresist patterns 141a and 141b are formed.

Since the P-type TFT region is blocked by the resist pattern during n ⁺ doping, n ⁺ ions are not doped, and in the N-type TFT region, the photoresist pattern is intrinsic to a region wider than the width of the second gate electrode 111b. The semiconductor layer is formed.

Subsequently, as shown in FIG. 2I, after the photoresist patterns 141a and 141b are removed, a low concentration of lightly doped drain (LDD) doping is performed on the entire substrate 110, and n ⁺ doped with high concentration of ions. The layers 116g and 116h and the p ⁺ layers 116b and 116c are not affected at all, but both sides (ie, the photoresist pattern 141a and the width and the bottom of the intrinsic semiconductor layer, ie, the second gate electrode 111b) are not affected. Low concentration LDD layers 116e and 116f are formed in the area corresponding to the difference in width of the two-gate electrode 111b. In other words, the semiconductor layer of the N-type TFT region is formed in a structure in which LDD layers 116e and 116f and n ⁺ layers 116g and 116h are disposed on both sides of the intrinsic semiconductor layer 116d.

Thereafter, as shown in FIG. 2J, an insulating layer is stacked over the entirety of the substrate 110 to form a protective layer 126, and then a contact hole is formed using a mask to open the electrode of the TFT. Then, as illustrated in FIG. 2K, the metal layer 119a is stacked over the entire substrate 110 having contact holes formed in the protective layer, and the photoresist layer 160 is formed thereon, as shown in FIG. 2L. When the photoresist layer 160 is ashed, the photoresist layer 160a remains only inside the contact hole and all of the protective layer 126 is removed. Therefore, when the metal layer 119a is etched using the photoresist layer 160a, the barrier metal layer 119 is formed in the contact hole. As described above, in the present invention, the mask process is not necessary when the barrier metal layer 119 is formed. The barrier metal layer 119 is to prevent the oxygen of the metal oxide from being combined with the metal electrode when the metal oxide such as ITO is in contact with the metal electrode to increase the contact resistance.

As described above, a metal layer and a transparent metal oxide, such as ITO or IZO, are continuously stacked on the entire substrate 110 formed over the substrate on which the barrier metal layer 119 is formed, and then a diffraction mask or a halftone mask is formed. When the metal oxide and the metal are etched, both the metal oxide and the metal are etched in the P-type TFT region and the N-type TFT region, so that the source electrodes 113a and 113b and the drain electrodes 114a and 114b are disposed on the metal oxide layer 117. Is formed. In the storage area, only the metal layer is etched and only the metal oxide layer 117 is exposed to the outside, and the metal oxide layer 117 in the storage area becomes the pixel electrode.

That is, by sequentially stacking the metal oxide layer and the metal layer, the source electrode, the drain electrode, and the pixel electrode can be formed by one mask process by diffraction etching. At this time, since the barrier metal layer 119 is formed between the metal oxide layer, the source electrodes 113a and 113b and the drain electrodes 114a and 114b, it is possible to prevent the contact resistance from increasing.

3 is a plan view of the liquid crystal display device formed by the method as described above, the structure of the liquid crystal display device according to the present invention with reference to this as follows. In this case, the driving circuit region is omitted and only the pixel region is illustrated for convenience of description.

In an actual liquid crystal display device, N gate lines and M data lines cross each other, and there are M × N pixels, but one pixel is shown in the figure for simplicity.

As shown in the figure, a gate line 216 and a data line 217 are formed on the substrate 110 to be vertically and horizontally arranged on the substrate 110 to define a pixel area. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 216 and the data line 217, and is connected to the thin film transistor in the pixel area and is connected to a common electrode of a color filter substrate (not shown). In addition, a pixel electrode 117 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 111b connected to the gate line 216, a source electrode 113b connected to the data line 217, and a drain electrode 114b connected to the pixel electrode 117. In addition, the thin film transistor may include active patterns 116e, 116f, and 116g which form a conductive channel between the source electrode 113b and the drain electrode 114b by a gate voltage supplied to the gate electrode 111b. 16h).

In this case, the active patterns 116e, 116f, 116g, and 16h may be formed of polysilicon thin films, and the active patterns 116e, 116f, 116g, and 16h may be partially extended to the pixel region and may be together with the common line 108. It is connected to the storage pattern 128 constituting the first storage capacitor. That is, the common line 111c is formed in the pixel area in substantially the same direction as the gate line 216, and the common line 111c has a first insulating layer (not shown) therebetween. The first storage capacitor overlaps with the storage pattern 128. In this case, the storage pattern 128 is formed through storage doping through a separate mask process on the polysilicon thin film forming the active patterns 116e, 116f, 116g, and 16h.

The source electrode 113b and the drain electrode 114b are connected to source regions of the active patterns 116e, 116f, 116g, and 16h through contact holes 140a formed in the first and second insulating layers (not shown). It is electrically connected to the drain region. In addition, a portion of the source electrode 113b extends in one direction to form a portion of the data line 217, and a portion of the drain electrode 114b extends toward the pixel region through a contact hole formed in the third insulating layer. It is electrically connected to the pixel electrode 117.

In this case, a part of the drain electrode 114b extending to the pixel region overlaps the common line 111c below the second insulating layer, thereby forming a second storage capacitor.

As described above, in the liquid crystal display of the present invention, a mask for forming a semiconductor layer and a storage pattern, a mask for forming a gate electrode in a P-type TFT region, a gate electrode for forming an N-type TFT region and a mask for forming an LDD layer, and a mask for opening a protective layer. And only five masks, such as a mask for forming the source electrode and the drain electrode, are greatly simplified.

Claims (7)

Preparing a substrate comprising a P-type TFT region, an N-type TFT region, and a storage region; Stacking a buffer layer, a semiconductor material and a metal on the substrate; Etching the semiconductor material and metal to form a semiconductor layer in a P-type TFT region and an N-type TFT region, and forming a semiconductor layer and a metal layer in a storage region; Forming a p ⁺ layer on the semiconductor layer of the P-type TFT region and forming a gate electrode thereon; Forming an LDD structure on the semiconductor layer of the N-type TFT region and forming a gate electrode thereon; Forming a protective layer and then etching to form a contact hole; Forming a barrier metal layer in the contact hole; And And forming a source electrode and a drain electrode in the protective layer and the contact hole. The method of claim 1, wherein the forming of the semiconductor layer and the metal layer comprises: Applying a photoresist on the buffer layer, the semiconductor material, and the metal stacked on the substrate; Placing a diffraction mask on the photoresist and then irradiating light to form a photoresist pattern; Etching metals and semiconductor materials using the photoresist pattern; Acing the photoresist pattern; Removing the metal on the semiconductor material using the aced photoresist pattern; And And removing the photoresist pattern on the metal. The method of claim 1, wherein the forming of the gate electrode and the p ⁺ layer in the P-type TFT region, Depositing a metal across the substrate; Etching the metal to form a gate electrode in the P-type TFT region and forming a metal layer in the N-type TFT region and the storage region; And p ⁺ doping using the gate electrode as a mask. The method of claim 3, wherein the N-type TFT region and the storage region are blocked by a metal layer during the p ⁺ doping. The method of claim 1, wherein the forming of the gate electrode and the LDD structure in the N-type TFT region, Forming a photoresist pattern for stacking and developing a photoresist on a metal layer formed in the N-type TFT region and the storage region; Forming a gate electrode having a width smaller than that of the photoresist pattern by overetching the metal layer of the N-type TFT region using the photoresist pattern; N ⁺ doping the semiconductor layer of the N-type TFT region using the photoresist pattern as a mask; And And removing the photoresist pattern and performing LDD doping using a gate electrode as a mask. The method of claim 1, wherein the forming of the barrier metal layer in the contact hole comprises: Depositing a barrier metal on the entire substrate and in the contact hole; Depositing a photoresist on the barrier metal; Acing the photoresist to form a photoresist pattern inside the contact hole; And And etching the barrier metal using the photoresist pattern. The method of claim 1, wherein the forming of the source electrode and the drain electrode in the protective layer and the contact hole, Forming a transparent conductive layer and a metal layer on the protective layer; Etching the transparent conductive layer and the metal layer of the P-type semiconductor region and the N-type semiconductor region by using a diffraction mask to form a source electrode and a drain electrode; And And forming a pixel electrode formed of a transparent conductive layer by etching the metal layer of the storage area.

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