KR101560415B1 - Method of manufacturing Liquid Crystal Display device - Google Patents

Abstract

The present invention relates to a method of manufacturing a liquid crystal display, and a method of manufacturing a liquid crystal display according to the present invention is a method of manufacturing a liquid crystal display using a first mask process, Forming a first gate electrode in a P-channel thin film transistor formation region of the substrate using a second mask process; and forming a second active pattern on the N-channel A first contact hole exposing the N source region and the P source region using a fourth mask process, and a second contact hole exposing the N drain region and the P drain region, respectively, Forming a second contact hole for exposing the N source region and the P source region using a fifth mask process; Forming an N-drain electrode and a P-drain electrode to be connected to the N-drain region and the P-drain region, forming a third contact hole and a common electrode simultaneously using a sixth mask process, Forming a fourth contact hole exposing the N-drain electrode and the P-drain electrode using a seventh mask process, and forming a pixel electrode using the eighth mask process.

Description

[0001] The present invention relates to a manufacturing method of a liquid crystal display device,

The present invention relates to a method of manufacturing a liquid crystal display device.

In recent information society, display has become more important as a visual information delivery medium. In order to prevail its major position in the future, it is necessary to meet requirements such as low power consumption, thinning, light weight, and high image quality. Liquid Crystal Display (LCD), which is the flagship product of Flat Panel Display (FPD), is not only capable of satisfying these conditions of display but also has mass productivity. Therefore, And has become a core parts industry that can gradually replace conventional cathode ray tubes (CRTs).

2. Description of the Related Art Generally, a liquid crystal display (LCD) displays a desired image by supplying a data signal according to image information individually to liquid crystal cells arranged in a matrix form and adjusting a light transmittance of the liquid crystal cells, to be.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be. Particularly, the amorphous silicon thin film transistor is actively used because a low-temperature process is possible and an inexpensive insulating substrate can be used.

However, the amorphous silicon thin film transistor has a limited electric mobility (~ 1 cm < 2 > / Vsec) for use in a peripheral circuit requiring a high-speed operation of 1 MHz or more. Accordingly, researches for simultaneously integrating a pixel portion and a driving circuit portion on a glass substrate using a polycrystalline silicon (poly-Si) thin film transistor having a field effect mobility larger than that of the amorphous silicon thin film transistor are actively performed It is progressing.

The increase of the mobility can improve the operating frequency of the driving circuit portion for determining the number of driving pixels, and the resulting high-definition display of the display device is facilitated. In addition, the distortion of the transmission signal is reduced due to the reduction of the charging time of the signal voltage for the pixels, and the image quality can be expected to be improved.

In addition, the polycrystalline silicon thin film transistor can be operated at less than 10V compared to an amorphous silicon thin film transistor having a high driving voltage (~ 25V), thereby reducing power consumption.

FIG. 1 is a plan view schematically showing the structure of a general liquid crystal display device, showing a liquid crystal display device integrated with a drive circuit in which a driver circuit portion is integrated on an array substrate.

As shown in the figure, a liquid crystal display device mainly comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 .

The array substrate 10 includes a pixel portion 35 which is an image display region in which unit pixels are arranged in a matrix form and a data driving circuit portion 31 and a gate driving circuit portion 32 located outside the pixel portion 35 And a driving circuit unit 30.

Although not shown in the figure, the pixel portion 35 of the array substrate 10 includes a plurality of gate lines and data lines arranged vertically and horizontally on the substrate 10 to define a plurality of pixel regions, A thin film transistor which is a switching element formed in a crossing region of the data line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching device for applying and blocking a signal voltage to the pixel electrode, and controls the flow of electric current by an electric field.

The driving circuit portion 30 of the array substrate 10 is located outside the pixel portion 35 of the array substrate 10 protruded from the color filter substrate 5, The data driving circuit portion 31 is located on the long side and the gate driving circuit portion 32 is located on one side (short) side of the protruded array substrate 10.

At this time, the data driving circuit portion 31 and the gate driving circuit portion 32 use a thin film transistor of a CMOS (Complementary Metal Oxide Semiconductor) structure, which is an inverter, to appropriately output an input signal.

The CMOS is a type of integrated circuit having a MOS structure used in a driving circuit thin film transistor requiring high-speed signal processing. The CMOS requires both an N-channel thin film transistor and a P-channel thin film transistor. PMOS < / RTI >

The gate driving circuit part 32 and the data driving circuit part 31 are connected to an external signal input terminal (not shown) for supplying a scanning signal and a data signal to the pixel electrode through a gate line and a data line, And controls an external signal inputted through an external signal input terminal to output the adjusted external signal to the pixel electrode.

A color filter (not shown) that implements color and a common electrode (not shown) that is an opposite electrode of the pixel electrode formed on the array substrate 10 are formed in the pixel portion 35 of the color filter substrate 5 have.

The color filter substrate 5 and the array substrate 10 having such a structure are provided with cell gaps to be spaced apart from each other by a spacer (not shown) (Not shown) to form a unit liquid crystal display panel. At this time, the two substrates 5 and 10 are attached to each other through a cemented key formed on the color filter substrate 5 or the array substrate 10.

Since a manufacturing process of a liquid crystal display device having such a structure basically requires a number of mask processes (that is, a photolithography process) in the fabrication of an array substrate including thin film transistors, the number of mask processes There is a need for a method of reducing the amount of water.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as a photoresist application, an exposure, and a development process. There is a drawback that it drops.

In particular, the mask designed to form the pattern is very expensive, so that the manufacturing cost of the liquid crystal display device increases proportionally as the number of masks applied to the process increases.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems described above and to provide a method of manufacturing a thin film transistor, which comprises forming a contact hole exposing a drain electrode and a common electrode forming process through a single mask process, And a method for producing the same.

It is another object of the present invention to provide a method of manufacturing a liquid crystal display device capable of improving a side profile of a gate electrode in a gate electrode forming process.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including: providing a substrate divided into a P-channel TFT forming region and an N-channel TFT forming region; Forming first and second active patterns on the P-channel thin film transistor forming region and the N-channel thin film transistor forming region of the first insulating film and the N-channel thin film transistor forming region, respectively; forming a first insulating film and a first conductive film on the substrate on which the first and second active patterns are formed Forming a first gate electrode made of the first conductive film in the P-channel thin film transistor forming region of the substrate using a second mask process; forming a P-type drain region, a P- , Forming the P-drain region, the P-channel region, and the p-LDD region, and forming the N-channel thin film transistor type Forming an N-type drain region, an N-type source region, the N-type drain region, an N-channel region, and an n- LDD region in the second active pattern; , Forming a second insulating film on the substrate having the N-type drain region, the N-type source region, the N-type channel region, and the n- LDD region formed thereon, and selectively removing the first and second insulating films using a fourth mask process A first contact hole exposing a portion of the N source region and the P source region, and a second contact hole exposing a portion of the N drain region and the P drain region, And forming a second conductive film on the substrate on which the second contact hole is formed; and forming an N-type source electrode electrically connecting the N source region and the P source region through the first contact hole using a fifth mask process, And P Forming an N-drain electrode and a P-drain electrode electrically connected to the N-drain region and the P-drain region through a second contact hole; Forming a third contact hole through the third insulating film by using a sixth mask process and forming a common electrode on the third insulating film; , Forming a fourth insulating film on the substrate on which the third contact hole and the common electrode are formed, exposing the N drain electrode and the P drain electrode through the fourth insulating film by using a seventh mask process, Forming a fourth conductive film on the substrate on which the fourth contact hole is formed, forming a fourth contact hole through the fourth contact hole using the eighth mask process, And forming a pixel electrode connected to the P drain electrode, wherein the first gate electrode is formed, and a P-type drain region, a P-source region, a P-channel region, and a p-LDD region are formed in the first active pattern Forming a first photoresist pattern formed on the first conductive film through the second mask process; performing a dry etching process on the first conductive film using the first photoresist pattern as an etching mask Forming a first gate electrode by performing a wet etching process on the substrate on which the gate electrode pattern is formed, and forming a gate electrode pattern on the entire surface of the substrate by using the first photoresist pattern as a mask Drain region and the P-source region in a predetermined region of the first active pattern to form the P-type drain region and the P- Channel region of the first active pattern and the P-channel region of the first active pattern by implanting ions into the entire surface of the substrate using the first gate electrode as a mask, forming a P-channel region, removing the first photoresist pattern, And forming a p-LDD region between the P-channel region and the P-source region.

Forming the second gate electrode, and forming the P-type drain region, the P-type source region, the P-type channel region, and the p-LDD region in the second active pattern, Forming a gate electrode pattern on the first conductive film by performing a dry etching process on the first conductive film using the second photoresist pattern as an etching mask; Forming a second gate electrode by performing a wet etching process on the substrate; implanting ions of the second photoresist pattern on the entire surface of the substrate by using the mask as a mask to form the N-type drain region and N Forming a source region, forming the N-channel region between the N-drain region and the P-source region, and removing the second photoresist pattern And implanting an n-LDD region between the N-channel region and the N-drain region and between the N-channel region and the N-source region by ion-implanting the second gate electrode on the entire surface of the substrate .

Forming a third contact hole through the third insulating film by using the sixth mask process and forming a common electrode on the third insulating film may include forming a third contact hole through the third insulating film on the substrate on which the third insulating film and the third conductive film are formed, Forming a third photoresist pattern using a sixth mask; performing an exposure process on the substrate on which the third photoresist pattern is formed to penetrate the third conductive film, expose a part of the third insulating film, Forming a third conductive layer on the third conductive layer; removing the exposed third conductive layer using the third photoresist pattern as a mask; and performing a developing process on the third conductive layer, Forming a third contact hole exposing the N-drain electrode and the P-drain electrode, respectively, by developing the exposed region of the insulating film; A fourth step of forming a photoresist pattern, and the fourth photo-resist pattern as a mask and forming a common electrode by removing the exposed third conductive film.

The sixth mask is a diffraction mask including a transmissive region, a semi-transmissive region which is a slit region, and a blocking region.

The transmissive region is disposed in a region where the third contact hole is to be formed and the semi-transmissive region is formed in a region where the common electrode is to be formed and a third contact hole is formed in the region where the common electrode is to be formed, Are arranged in the region between the regions to be formed.

In the fourth photoresist pattern, the photoresist remains only in the region where the common electrode is to be formed, and all the photoresist is removed in the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed.

As described above, the method of manufacturing a liquid crystal display according to the present invention can reduce the number of masks used in manufacturing a thin film transistor by forming a contact hole forming step of exposing a drain electrode and a common electrode forming step through a single mask process It is effective.

In the method of manufacturing a liquid crystal display device according to the present invention, the side profile of the gate electrode is improved by sequentially performing the dry etching process and the wet etching process to form the gate electrode, The CD of the gate electrode formed at the center portion of the gate electrode and the CD of the gate electrode formed at the edge portion are uniform and the occurrence of stain is minimized due to the removal of the remaining conductive film.

Hereinafter, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

FIGS. 3A to 3F are cross-sectional views illustrating a method of forming a contact hole and a common electrode forming process for exposing the drain electrode of FIG. 2F according to an embodiment of the present invention. 4A to 4E are process flow diagrams illustrating the gate electrode, drain region, source region, and LDD (Lightly Doped Drain) region formation process described in more detail in FIGS. 2B and 2C.

FIGS. 2A to 2H and FIGS. 3A to 3F are cross-sectional views sequentially illustrating a method of manufacturing an array substrate, illustrating a process of manufacturing an array substrate on which N-channel thin film transistors and P-channel thin film transistors are formed . On the other hand, the N-channel thin film transistor and the P-channel thin film transistor can be formed in both the driver circuit portion and the pixel portion.

In addition, although an embodiment of the present invention has been described by way of example of a liquid crystal display device of an in-plane switching system (IPS), the present invention is not limited thereto.

As shown in FIG. 2A, a buffer layer 102 and a silicon thin film are formed on a substrate 100 made of a transparent insulating material such as glass, and then the silicon thin film is crystallized to form a polycrystalline silicon thin film.

The substrate 100 is divided into N-channel thin film transistor forming regions and P-channel thin film transistor forming regions.

At this time, the buffer layer 102 serves to prevent impurities such as sodium (Na) present in the substrate 100 from penetrating into the upper layer during the process.

In this case, the polycrystalline silicon thin film is used as a semiconductor layer of a thin film transistor. However, the present invention is not limited thereto, and an amorphous silicon thin film may be used as a semiconductor layer of the thin film transistor.

In addition, the polycrystalline silicon thin film may be formed by depositing an amorphous silicon thin film on the substrate 100, and then forming the amorphous silicon thin film by various crystallization methods.

The amorphous silicon thin film may be deposited by various methods. Typical methods for depositing the amorphous silicon thin film include a low pressure chemical vapor deposition (LPCVD) method and a plasma enhanced chemical vapor deposition Chemical Vapor Deposition (PECVD).

As a method of crystallizing the amorphous silicon thin film, there are a solid phase crystallization (SPC) method of heat-treating an amorphous silicon thin film in a high temperature furnace and an excimer laser annealing (ELA) method using a laser .

Although the excimer laser annealing method using a pulse type laser is mainly used as the laser crystallization furnace, a sequential lateral solidification (SLS) method in which grains are grown in the horizontal direction to improve the crystallization characteristics, Methods are being studied.

Then, a first photoresist pattern (not shown) is formed on the polycrystalline silicon thin film through a first mask process, and the polycrystalline silicon thin film is patterned using the first photoresist pattern (not shown) to form the N-channel thin film transistor forming regions A and The first and second active patterns 104a and 104b are formed in the P-channel thin film transistor forming regions B, respectively.

Next, as shown in FIG. 2B, a first insulating layer 106 and a first conductive layer 108a are formed on the entire surface of the substrate 100 on which the first and second active patterns 104a and 104b are formed.

The first conductive layer 108a may be formed of a material selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium A low resistance opaque conductive material such as molybdenum (Mo) or the like.

Then, a second photoresist pattern (not shown) is formed through a second mask process, and the first conductive layer 108a is selectively patterned using the second photoresist pattern (not shown) to form a P-channel thin film transistor forming region The P-channel region 104bc1, and the p-channel region 104bc2 are formed by using the first gate electrode 108d as a mask and forming the P-type drain region 105a and the P-type source region 105b, Thereby forming an LDD (Lightly Doped Drain) region 105c.

The following describes how to form the first gate electrode 108d, the P drain region 105a, the P source region 105b, the P channel region 104bc1, and the p-LDD (lightly doped drain) region 105c , Will be described in more detail with reference to Figs. 4A to 4E.

4A, the second photoresist pattern 201a formed through the second mask process is formed on the first conductive film 108a, and the second photoresist pattern 201a is formed on the etching mask The first conductive layer 108a is subjected to a dry etching process to form a gate electrode pattern 108b.

4B, the first gate electrode 108d is formed by performing a wet etching process on the substrate 100 having the gate electrode pattern 108b formed thereon.

At this time, the dry etching process etches about 2/3 of the thickness to be etched, and the wet etching process etches about 1/3 of the thickness to be etched. Thus, after the dry etching process is etched in the main etching process to determine the shape of the gate electrode, the wet etching process can be performed in a sub-etching process, such as a tail of a conductive film that may be generated in a dry etching process The same remaining conductive film is etched away.

Accordingly, when the gate electrode 108d is formed by sequentially performing the dry etching process and the wet etching process, the side profile of the gate electrode is improved, and the gate electrode 108d formed at the central portion of the substrate 100, And CD of the gate electrode formed at the edge portion are made uniform and the occurrence of stain is minimized due to removal of the remaining conductive film.

Next, as shown in FIG. 4C, p + ions are implanted into the entire surface of the substrate 100 using the second photoresist pattern 201a as a mask to form a P-type drain region in a predetermined region of the second active pattern 104b. Regions 105a and P source regions 105b are formed. At this time, a P-channel region 104bc1 forming a conduction channel is formed between the P-drain region 105a and the P-source region 105b.

Next, as shown in FIG. 4D, a strip process for removing the second photoresist pattern 201a is performed.

Next, as shown in FIG. 4E, low-concentration p-ions are injected onto the substrate 100 from which the second photoresist pattern 201a has been removed to form a p-channel region 104bc1 between the P-type drain region 105a And a p-LDD (Lightly Doped Drain) region 105c is formed between the P-channel region 104bc1 and the P-source region 105b.

The first gate electrode 108d having a line width smaller than that of the gate electrode pattern 108c is used as an ion implantation mask in the ion implantation process for implanting the low concentration p- LDD (Lightly Doped Drain) region 105c is formed in the second active pattern 104b inside the P-type source region 105a and the P-type source region 105b formed by using the first active region 104a.

Due to the first conductive film 108a formed in the N-channel thin film transistor formation region A, the high concentration and low concentration p + ions and p-ions implanted into the P-channel thin film transistor formation region B are N-channel Is prevented from being injected into the thin film transistor formation region (A).

Next, as shown in FIG. 2C, a third photoresist pattern (not shown) is formed through a third mask process, and a first conductive film 108a formed in the N-channel thin film transistor formation region A is formed, The second gate electrode 108c is formed in the N-channel thin film transistor formation region A of the substrate 100 and the N-drain region 107a is formed using the second gate electrode 108c as a mask, N source region 107b, an N-channel region 104bc2, and an n-LDD (Lightly Doped Drain) region 107c. At this time, the second gate electrode 108c, the drain region 107a, the N source region 107b, the N channel region 104bc2, and the n-LDD (Lightly Doped Drain) region 107c are shown in Figs. 4A to 4E LDD (Lightly Doped Drain) region 105c are formed in the same manner as the first gate electrode 108d, the P-drain region 105a and the P-source region 105b, the P-channel region 104bc1, do.

Next, as shown in FIG. 2D, a second insulating layer 110 is formed on the entire surface of the substrate 100, a fourth photoresist pattern (not shown) is formed through a fourth mask process, A first contact hole 112a for selectively removing a portion of the first and second insulating films 106 and 110 to expose a portion of the N source region 105b and the P source region 107b, The second contact hole 112b exposing a part of the region 105a and the P drain region 107a is formed.

Here, the second insulating layer 110 may be a double layer of silicon nitride (SiNx) / silicon oxide (SiO ₂ ), and may be a SiNx single layer or a triple layer of SiO ₂ / SiN x / SiO ₂ . have.

Next, as shown in FIG. 2E, a second conductive layer is formed on the entire surface of the substrate 100 having the first and second contact holes 112a and 112b formed thereon, and then a fifth photoresist pattern And an N source electrode (not shown) electrically connected to the N source region 105b and the P source region 107b through the first contact hole 112a by selectively patterning the second conductive film using the second conductive film Drain electrodes 114a and 114a and a P source electrode 115a and an N drain electrode 114b electrically connected to the N drain region 105a and the P drain region 107a via the second contact hole 112b, (115b).

The second conductive layer may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or the like to form source and drain electrodes.

Next, as shown in FIG. 2F, a third insulating film (not shown) is formed on the substrate 100 on which the N source electrode 114a, the P source electrode 115a, the N drain electrode 114b, and the P drain electrode 115b are formed. 116, and a third conductive film are sequentially formed, and then a sixth photoresist pattern (not shown) is formed through a sixth mask process, and the third insulating film 116 and the third conductive film are selectively patterned using the sixth photoresist pattern (not shown) A third contact hole 117a penetrating the third insulating film 116 is formed and a common electrode 118c is formed on the third insulating film 116. [

An organic insulating material such as acryl based organic compound, BCB or PFCB is used for the third insulating film 116, and a third conductive film is formed using indium-tin-oxide or indium-zinc- And can be made of a transparent conductive material having excellent transmittance.

Next, a method of forming the third contact hole 117a and the common electrode 118c through the sixth mask process will be described in more detail with reference to FIGS. 3A to 3F.

First, as shown in FIG. 3A, a sixth photoresist pattern 200a is formed on the substrate 100 formed with the third insulating film 116 and the third conductive film 118a sequentially through a sixth mask process .

At this time, the sixth photoresist pattern 200a is formed by photolithography using a sixth mask (not shown) after forming a photoresist on the third conductive layer 118a. At this time, the sixth mask has a transmissive region for transmitting light, a semi-transmissive region, which is a slit region for transmitting a part of light and blocking a part of the light, and a blocking region for blocking light, Lt; / RTI > The photoresist remains as it is in the blocking region, and the photoresist remains in the transflective region at a lower thickness than the photoresist in the blocking region, and the photoresist does not remain in the transmissive region.

Accordingly, in the sixth photoresist pattern 200a, since the region where the common electrode is to be formed is disposed in the blocking region, the photoresist remains as it is, and the region where the third contact hole is to be formed is disposed in the transmissive region, The third conductive film 118a is exposed and the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed is disposed in the transflective region and thus remains at a lower thickness than the photoresist in the blocking region.

Next, an exposure process is performed on the substrate 100 on which the sixth photoresist pattern 200a is formed to expose the third insulating film 116 corresponding to the region where the contact hole is to be formed through the third conductive film as the transparent conductive film Thereby forming an exposure region R.

Next, as shown in FIG. 3B, the exposed third conductive layer 118a is removed using the sixth photoresist pattern 200a as a mask (reference numeral 118b denotes a third conductive layer left after the removal).

3C, a development process is performed on the substrate 100 from which a part of the third conductive film 118a has been removed to expose and remove the exposed region R of the third insulating film 116. Then, Thereby forming a fourth contact hole 117a exposing the N drain electrode 105a and the P drain electrode 107a, respectively.

Next, as shown in FIG. 3D, the sixth photoresist pattern 200a is etched to form a seventh photoresist pattern 200b.

The seventh photoresist pattern 200b is a pattern in which the photoresist remains only in the region where the common electrode is to be formed and the photoresist is removed in the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed to be. Thereby, the third conductive film 118b formed in the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed is exposed.

Next, as shown in FIG. 3E, the exposed third conductive layer 118b is removed using the seventh photoresist pattern 200b as a mask (reference numeral 118c denotes a third conductive layer left after being removed, Which becomes a common electrode).

Next, as shown in FIG. 3F, the seventh photoresist pattern 200b is removed through a strip process. As a result, the third contact hole 117a and the common electrode 118c can be simultaneously formed through the sixth mask process using the mask having three different transmittances.

2G, a fourth insulating layer 120 is formed on the substrate 100 on which the third contact hole 117a and the common electrode 118 are formed, and the seventh insulating layer 120 is formed through the seventh mask process. Drain electrodes 114b and the P drain electrodes 115b through the fourth insulating film 120 by selectively removing the fourth insulating film 120 by forming a pattern (not shown) 5 contact holes 117b.

The fifth contact hole 117b is formed at the same position as the third contact hole 117a and the size of the fifth contact hole 117b is equal to the size of the third contact hole 117a . That is, the fifth contact hole 117b is formed by selectively removing the fourth insulating film 120 deposited inside the third contact hole 117a. Therefore, the fifth contact hole 117b is different from the formation position of the third contact hole, It is necessary to remove not only the fifth insulating film 120 but also the third insulating film 116, so that the process difficulty is increased.

Next, as shown in FIG. 2H, a fourth conductive film is formed on the entire surface of the substrate 100 on which the fifth contact hole 120 is formed, and then a ninth photoresist pattern (not shown) is formed through an eighth mask process And the fourth conductive film is selectively patterned to form the pixel electrode 120 electrically connected to the N drain electrode 114b and the P drain electrode 115b through the fifth contact hole 117b.

In this case, the fourth conductive layer may be formed of a transparent conductive material having a high transmittance such as indium-tin-oxide or indium-zinc-oxide to form the pixel electrode.

The array substrate of the above-described embodiment of the present invention configured as described above is adhered to and opposed to the color filter substrate by a sealant formed on the outer periphery of the image display area. At this time, light is emitted from the color filter substrate to the thin film transistor, A black matrix for preventing leakage and a color filter for realizing red, green and blue colors are formed.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

At this time, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescence display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

1 is a plan view schematically showing a structure of a general liquid crystal display device

FIGS. 2A to 2H are process flow diagrams sequentially illustrating a method of manufacturing a liquid crystal display device according to the present invention,

FIGS. 3A to 3F are cross-sectional views illustrating a process of forming a contact hole exposing the drain electrode shown in FIG. 2F,

FIGS. 4A to 4E are cross-sectional views illustrating a process flow chart illustrating a method of forming a gate electrode, a drain region, a source region, a channel region, and an LDD (Lightly Doped Drain)

Claims (6)

Providing a substrate divided into a P-channel thin film transistor formation region and an N-channel thin film transistor formation region; Forming first and second active patterns in each of the P-channel thin film transistor forming region and the N-channel thin film transistor forming region of the substrate using a first mask process; Forming a first insulating film and a first conductive film on a substrate on which the first and second active patterns are formed, A first gate electrode made of the first conductive film is formed in a P-channel thin film transistor formation region of the substrate using a second mask process, and a P-type drain region, a P-type source region, , A P-channel region and a p-LDD region, A second gate electrode made of the first conductive film is formed in an N-channel thin film transistor formation region of the substrate using a third mask process, and an N-type drain region, an N-type source region, , An N-channel region and an n-LDD region, Forming a second insulating film on the substrate on which the N drain region, the N source region, the N channel region, and the n- LDD region are formed; A first contact hole exposing a portion of the N source region and the P source region by selectively removing the first and second insulating films using a fourth mask process; Forming a second contact hole exposing a portion of the first contact hole, Forming a second conductive film on the substrate on which the first and second contact holes are formed, Forming a N source electrode and a P source electrode electrically connected to the N source region and the P source region through the first contact hole using a fifth mask process and forming the N source electrode and the P source electrode through the second contact hole, Forming an N-drain electrode and a P-drain electrode electrically connected to the P-drain region; Forming a third insulating film and a third conductive film on the substrate on which the N drain electrode and the P drain electrode are formed; Forming a third contact hole through the third insulating film using a sixth mask process and forming a common electrode on the third insulating film; Forming a fourth insulating film on the substrate on which the third contact hole and the common electrode are formed, Forming a fourth contact hole which exposes each of the N drain electrode and the P drain electrode through the fourth insulating film using a seventh mask process; Forming a fourth conductive film on the substrate on which the fourth contact hole is formed, And forming a pixel electrode connected to the N-drain electrode and the P-drain electrode through the fourth contact hole using an eighth mask process, Forming the first gate electrode, and forming a P-drain region, a P-source region, a P-channel region, and a p-LDD region in the first active pattern Forming a first photoresist pattern formed through the second mask process on the first conductive film; Performing a dry etching process on the first conductive film using the first photoresist pattern as an etching mask to form a gate electrode pattern; Forming a first gate electrode by performing a wet etching process on the substrate having the gate electrode pattern formed thereon, Forming a P-type drain region and a P-type source region in a predetermined region of the first active pattern by ion-implanting ions on the entire surface of the substrate using the first photoresist pattern as a mask, Forming a channel region, Removing the first photoresist pattern; The p-LDD region is formed between the P-channel region and the P-drain region of the first active pattern and between the P-channel region and the P-source region by ion-implanting the entire surface of the substrate with the first gate electrode as a mask Wherein the step of forming the liquid crystal display panel comprises the steps of: The method of claim 1, wherein forming the second gate electrode and forming a P drain region, a P source region, a P channel region, and a p-LDD region in the second active pattern Forming a second photoresist pattern formed through the third mask process on the first electroconductive film; Performing a dry etching process on the first conductive film using the second photoresist pattern as an etching mask to form a gate electrode pattern; Performing a wet etching process on the substrate on which the gate electrode pattern is formed to form a second gate electrode; Forming an N-type drain region and an N-type source region in a predetermined region of the second active pattern by ion-implanting ions on the entire surface of the substrate using the second photoresist pattern as a mask; Forming a channel region, Removing the second photoresist pattern; And forming an n-LDD region between the N-channel region and the N-drain region and between the N-channel region and the N-source region by ion-implanting the second gate electrode as a mask on the entire surface of the substrate. Of the liquid crystal display device. The method of claim 1, further comprising: forming a third contact hole through the third insulating film using the sixth mask process; and forming a common electrode on the third insulating film Forming a third photoresist pattern on the substrate on which the third insulating film and the third conductive film are formed by using the sixth mask; Performing an exposure process on the substrate on which the third photoresist pattern is formed to penetrate the third conductive film and expose a portion of the third insulating film to form an exposure region; Removing the exposed third conductive film using the third photoresist pattern as a mask, Forming a third contact hole exposing the N-drain electrode and the P-drain electrode by developing the exposed region of the third insulating film by performing a developing process on the substrate on which the third conductive film is partially removed, Forming a fourth photoresist pattern by ashing the third photoresist pattern; And removing the exposed third conductive film using the fourth photoresist pattern as a mask to form a common electrode. The apparatus of claim 3, wherein the sixth mask A transmissive region, a semi-transmissive region which is a slit region, and a blocking region. 5. The method of claim 4, The transmissive region is disposed in a region where the third contact hole is to be formed and the semi-transmissive region is formed in a region where the common electrode is to be formed and a third contact hole is formed in the region where the common electrode is to be formed, Wherein the liquid crystal layer is disposed in a region between regions to be formed. The method of claim 3, wherein the fourth photoresist pattern Wherein the photoresist is left only in the region where the common electrode is to be formed and the photoresist is removed in the region between the region where the common electrode is to be formed and the region where the third contact hole is to be formed .

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