JP3127619B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate for a display device which performs display by driving using transistors.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display, which is a leading flat display, has been mass-produced. Flat displays occupy less space,
Because of its light weight, it is used for display devices of portable computers and display units of industrial machines. In the future, larger screens and higher definition are expected, and application of home television is expected. In the case of a liquid crystal display using a thin film transistor as a driving element, it is necessary to increase the aperture ratio of each pixel for high contrast and color reproducibility. In a conventional pixel layout, as shown in FIG. 6A, a pixel electrode 604 electrically connected to a drain region of a thin film transistor through a contact hole 606 is disposed between a gate line 602 and a data line 603 so as not to overlap in plan. At a certain distance from each other. In this conventional example, the pixel electrode 604 and the gate line 602 and the pixel electrode 6
Since there is a gap between the data line 04 and the data line 603, there is a problem that the pixel area, that is, the aperture ratio is reduced. A good example of the related art that overcomes the problem of a small aperture ratio is disclosed in Japanese Patent Laid-Open Publication No. 2-207222. FIG. 3 shows a pixel layout. This conventional active matrix type liquid crystal display device requires a transparent pixel electrode 604 and a gate line 6 in order to increase the aperture ratio.
02, and a thick organic thin-film interlayer insulating film 613 is formed between the pixel electrode 604 and the data line 603, and the pixel electrode 604 is formed so as to overlap both the gate line 602 and the data line 603.

FIGS. 7 and 8 are cross-sectional views taken along the lines AA 'and BB' of FIG. 6B.

FIG. 7A is a sectional view of a planar thin film transistor. A passivation film 708 for preventing diffusion of impurities is formed on a glass substrate, a source region 705, a drain region 706, and an active silicon layer 710 are continuously formed, and a gate insulating film 709 is formed on the active silicon layer 710. Formed and then an active silicon layer 710
There is a gate electrode 707 so as to overlap. Gate electrode 7
07, the first interlayer insulating film 711 and the second interlayer insulating film 7
Cover with 13. In addition, a source electrode connected to the source region 705 is provided between the first interlayer insulating film 711 and the second interlayer insulating film 713. Further, a contact hole is formed in the interlayer insulating film so as to reach the drain region 706,
The pixel electrode 704 is formed over the second interlayer insulating film 713. As shown in FIG. 7A, the pixel electrode 704 is formed so as to overlap with the gate electrode 707, and the pixel electrode 715 of an adjacent pixel also overlaps with the gate electrode 707. 7B, the pixel electrode 704 is formed so as to overlap the gate line 702.
Further, the pixel electrode 715 of the next pixel is also connected to the gate line 702.
Overlaps.

FIGS. 8 (a) and 8 (b) are cross-sectional views when an inverted stagger type thin film transistor is used as a switching element.
(B). The positional relationship between the pixel electrode 804, the gate electrode 807, and the gate line 802 is shown in FIGS.
Same as (b).

[0006]

However, the conventional method has the following problems.

[0007] Between the data line and the transparent pixel electrode, 40
With a silicon oxide film or silicon nitride film having a thickness of 0 nm or an organic thin film having a thickness of 1000 nm interposed therebetween, the data line and a part of the transparent pixel electrode, and the gate line and a part of the transparent pixel electrode are further divided Again,
Although the aperture ratio is improved, a large parasitic capacitance _Cm occurs between the gate line _Gm and the pixel electrode shown in the circuit diagram of FIG. 5, and a sufficient signal is not applied to the transparent pixel electrode. , Which is a drawback of so-called push-down. Furthermore, the capacitance C _n and C _{n + 1} that occurs between the data line S _n and S _{n + 1} and the pixel electrode becomes a cause of cross-talk due to delay or distortion of the data line of the signal, high-quality images obtained There was no problem.

[0008]

SUMMARY OF THE INVENTION The present invention comprises a plurality of gate lines, a plurality of data lines, a transistor connected to each gate line and each data line, and a pixel connected to the transistor on a substrate. In an active matrix substrate having an electrode, an interlayer insulating film interposed between the data line and the pixel electrode, the data line is arranged in a groove formed in the substrate, and the pixel electrode is planar with the data line. And the thickness of the interlayer insulating film located in the groove is formed to be thicker than the thickness of the interlayer insulating film in other portions. The present invention is characterized in that the interlayer insulating film formed between the pixel electrode and the gate line comprises a flattening film. The present invention, a plurality of gate lines on the substrate, a plurality of data lines, a transistor connected to each gate line and each data line,
In an active matrix substrate having a pixel electrode connected to the transistor and an interlayer insulating film interposed between the gate line and the pixel electrode, the gate line is disposed in a groove formed in the substrate, and the pixel electrode Are arranged so as to overlap the gate line in a plane, and the thickness of the interlayer insulating film located in the groove is formed to be thicker than the thickness of the interlayer insulating film in other portions.

[0009]

SUMMARY OF THE INVENTION In view of the above problems, the present invention reduces the parasitic capacitance generated between a gate line and a pixel electrode, which causes a pushdown, and forms a storage capacitor for mitigating the pushdown phenomenon. Accordingly, an object of the present invention is to provide a structure of an active matrix substrate constituting a liquid crystal display capable of obtaining a clear high-quality image.

Further, the present invention provides a structure of an active matrix substrate constituting a liquid crystal display capable of obtaining a clear and high quality image by reducing a parasitic capacitance generated between a wiring and a pixel electrode which causes crosstalk. Is what you do.

FIGS. 1A and 1B are plan views of a pixel according to an embodiment.

In FIG. 1A, a gate line 102 is arranged in a groove 101 of a glass substrate, and intersects a data line 103 in a lattice pattern. An insulating film is formed between the gate line 102 and the data line 103 and is electrically insulated. Gate line 102 and data line 103
A thin film transistor for switching the pixel electrode 104 is formed at the intersection of. The pixel electrode 104 is overlapped with the gate line 102 and the data line 103 in order to use all the regions other than the gate line 102, the data line 103, and the thin film transistor as the pixel region. The pixel electrode 104 includes a gate line 102 and a data line 103
Light from behind the glass substrate is transmitted through the pixel electrode 104 or the gate line 20.
2 and the data line 103, there is no light leakage from other than the pixel electrode. That is, the gate line 1032 and the data line 103 also serve as a light shielding film. In the embodiment of FIG. 1A, the source region 105 of the thin film transistor is formed in the region of the adjacent pixel electrode.
(B) shows the embodiment in which the thin film transistor and the pixel electrode which the thin film transistor switches are overlapped. A gate electrode 107 branched from the gate line 102 is also formed in the groove 101 of the glass substrate.

FIG. 2A is a cross-sectional view of the thin film transistor taken along line AA ′ of FIG. 1A when the planar thin film transistor of the embodiment of the present invention is used as a switching element.

A silicon oxide film or a nitride film 208 as a passivation film is applied over the entire surface of the glass substrate on which the groove is formed, and a patterned silicon film is provided in the groove.
A gate insulating film 209 is attached so as to cover the silicon film, and a gate electrode 207 is arranged so as to enter the trench. The source region 205 and the drain region 206 are
7 in a self-aligned manner. However, the source region 205 and the drain region 206 need not necessarily be arranged in a self-aligned manner with respect to the gate electrode 207. There is an active silicon layer 210 between the source region 205 and the drain region 206. The active silicon layer 210 is made of polycrystalline silicon, single crystal silicon, or amorphous silicon.

There is a first interlayer insulating film 211 made of silicon oxide or silicon nitride so as to cover the gate electrode 207. The first interlayer insulating film 211 and the gate insulating film 20
9, a source electrode 212 is formed by opening a contact hole. Further, a second interlayer insulating film 213 made of an organic thin film and having a thickness of 1 μm is deposited on the first interlayer insulating film, and a pixel electrode 204 is deposited on the second interlayer insulating film 213. Gate insulating film 209 and first interlayer insulating film 210
The pixel electrode 204 and the drain region are electrically connected through a contact hole penetrating the second interlayer insulating film.

In the case of FIG. 1A, the pixel electrode 204 is formed so as to overlap a part of the gate line.

FIG. 2B shows a cross-sectional structure of the gate line 202 along the line BB 'in FIG. 1B. A first interlayer insulating film and a second interlayer insulating film are provided over the gate line 202, and the pixel electrode 204 is arranged so as to overlap the gate line. For this reason, the effective pixel area through which light passes is maximized, and an image with a high contrast ratio is obtained.

The gate line 202 and the pixel electrode 204
Is also used in the data line. Further, not only the gate line 202 but also the data line may be arranged in the groove of the glass substrate.

The present invention can be applied not only to a planar type but also to an inverted stagger type thin film transistor. FIGS. 3A and 3B are cross-sectional views of the inverted staggered thin film transistor and the gate line of the invention, respectively.

In the examples of FIGS. 2A, 2B, 3A, and 3B, the present invention can be applied without the first interlayer insulating film.

Further, by further developing the embodiment of FIG. 1, the structure of the gate line is changed as shown in FIG. A gate line 407 or a part of a gate electrode is formed so as to be embedded in a groove of a glass substrate, and is covered with an interlayer insulating film 413 of an organic thin film. The organic thin film is formed so as to reduce the unevenness of the substrate, and the surface is flattened. Accordingly, the thickness d ₁ of the organic thin film of the organic thin film between the gate line 407 and the pixel electrode 404 overlaps, the parasitic capacitance _Cm decreases, and the organic thin film overlaps the gate line 407 and the adjacent pixel electrode 415. Since the thickness d _{2 of the} 413 becomes small, the storage capacity C
Since _m-1 is increased, reducing the parasitic capacitance C _m, represented in Figure 5, the holding capacitor C _m-1 is increased, to refer reducing distortion of the signal applied to the pixel electrode, a better Image display can be realized.

As shown in FIG. 4B, not only an active matrix substrate using a planar thin film transistor but also an inverted staggered thin film transistor,
This method can be applied.

[0023]

According to the present invention, the wiring is formed in the groove of the substrate, and the thickness of the interlayer insulating film located in the groove is made thicker than the thickness of the interlayer insulating film in the other portion. Since the parasitic capacitance with the wiring can be reduced, and the distortion of the signal applied to the pixel electrode by the transistor is significantly reduced, a bright, high-contrast ratio, high-quality image can be obtained with an extremely high aperture ratio. Can be

Further, when the data line is formed in the groove of the glass, the capacitance generated by the overlap of the data line and the pixel is reduced, and an accurate signal is transmitted from one end of the data line to the other. As a result, there has been no flicker, and a bright and high-quality image can be obtained with an extremely high aperture ratio.

Further, by forming the gate line so as to enter a part of the groove of the glass, the parasitic capacitance can be reduced.
In order to increase the storage capacitance, the distortion of the signal applied to the pixel electrode by the switching element is significantly reduced.
Bright and high-quality images can be obtained with an extremely high aperture ratio.

[Brief description of the drawings]

FIG. 1 is a plan view of an active matrix substrate of the present invention.

FIG. 2 is a cross-sectional view of the active matrix substrate of the present invention.

FIG. 3 is a cross-sectional view of the active matrix substrate of the present invention.

FIG. 4 is a cross-sectional view of the active matrix substrate of the present invention.

FIG. 5 is a circuit diagram of a pixel on an active matrix substrate.

FIG. 6 is a plan view of a conventional active matrix substrate.

FIG. 7 is a cross-sectional view of a conventional active matrix substrate.

FIG. 8 is a cross-sectional view of a conventional active matrix substrate.

[Explanation of symbols]

101, 201, 301, 401, 701, 801 ... groove 102, 202, 302, 402, 602, 702, 802 ... gate line 103, 603 ... data line 104, 204, 304, 404, 604, 704, 804 ... pixel electrodes 105, 205, 305, 405, 605, 705, 805 ... drain regions 106, 206, 306, 406, 606, 706, 806 ... source regions 107, 207, 307, 407, 607, 707, 807 ... gates Electrodes 208, 308, 408, 708, 808 ... passivation films 209, 309, 409, 709, 809 ... gate insulating films 210, 310, 410, 710, 810 ... active silicon layers 211, 311, 411, 711, 811 ... 1st interlayer insulating film 212, 312, 412, 712, 812 ... source electrode 213, 313, 413, 713, 813 ... second interlayer insulating film 214, 314, 414, 714, 814 ... stopper layer 215, 315, 415 , 715,815 ... adjacent pixel electrodes G _m-1 ... _m-1 th row of the gate lines G _m ... m-th row of gate line S _n ... n-th data line S n _{+ 1} ... n _{+ 1} column of data LCD line C _L ... pixel electrode The amount C _m-1 ... parasitic capacitance C _m ... holding capacitance C _n to make the pixel electrode and the adjacent gate lines generated by the pixel electrode and the gate line, the parasitic capacitance generated C n _{+ 1} ... pixel electrode and the data line

Claims (3)

(57) [Claims] A plurality of gate lines, a plurality of data lines, a transistor connected to each of the gate lines and each of the data lines, a pixel electrode connected to each of the transistors, In an active matrix substrate having an interlayer insulating film interposed between pixel electrodes, the data lines are arranged in grooves formed in the substrate, and the pixel electrodes are arranged so as to overlap the data lines in a plane. An active matrix substrate, wherein the thickness of the interlayer insulating film located in the groove is formed to be thicker than the thickness of the interlayer insulating film in another portion. 2. The active matrix substrate according to claim 1, wherein the interlayer insulating film formed between the pixel electrode and the gate line comprises a flattening film. 3. A plurality of gate lines, a plurality of data lines, a transistor connected to each gate line and each data line, a pixel electrode connected to the transistor, a pixel electrode connected to the transistor, In an active matrix substrate having an interlayer insulating film interposed between pixel electrodes, the gate line is disposed in a groove formed in the substrate, and the pixel electrode is disposed so as to overlap the gate line in a plane. An active matrix substrate, wherein the thickness of the interlayer insulating film located in the groove is formed to be thicker than the thickness of the interlayer insulating film in another portion.