KR100488925B1 - Liquid crystal display - Google Patents

Abstract

The present invention discloses a liquid crystal display device having an improved aperture ratio. The disclosed liquid crystal display device includes a gate line and a data line, each disposed at a constant equal interval and vertically intersecting with each other to define a unit pixel space, and the same direction as the long direction of the data line from the gate line. A protruding portion extending toward a next gate line and overlapping one side of the data line, a storage electrode pattern formed on the gate line, a drain electrode overlapping the other side of the protruding portion, and the unit pixel space A pixel electrode formed in the contact region, the pixel electrode contacting with the storage electrode pattern formed at a next stage of the gate line for selecting the drain electrode and the corresponding unit pixel space, and disposed to overlap the contacted storage electrode pattern; Is a corresponding gay that selects and drives the unit pixel space. And a gate line and a data line adjacent thereto, a gate insulating film is interposed between the gate line and the data line, between the gate line and the storage electrode pattern, and the pixel electrode and the data line; An organic insulating layer is interposed between the drain electrode and the pixel electrode and the storage electrode pattern.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having an improved aperture ratio.

Generally, a liquid crystal display includes a lower substrate having a plurality of pixel electrodes arranged in a matrix, and a liquid crystal interposed between an upper substrate and an upper and lower substrates having color filters correspondingly arranged in an arrangement state of pixel electrodes.

Here, as illustrated in FIG. 1, the gate line 2 and the data line 3 are alternately arranged on the lower substrate to define a unit pixel space. The thin film transistor TFT is disposed near the intersection point of the gate line 2 and the data line 3. The thin film transistor TFT includes a channel layer 4 disposed at a predetermined portion on the gate line 2, a source electrode S overlapping with one side of the channel layer 4 and extending from the data line 3, and a channel. The drain electrode D overlaps with the other side of the layer 4.

In each of the unit pixel spaces, the pixel electrode 5 is disposed of a transparent conductive material. In this case, the pixel electrode 5 is in contact with the drain electrode D of the thin film transistor TFT.

The storage electrode 6 is disposed under the pixel electrode 5 to form a storage capacitor.

On the other hand, a color filter (not shown) is arranged on the upper substrate (not shown) so as to vertically correspond to the pixel electrode 5. The edge of the color filter (not shown) is provided with a black matrix (not shown) that divides between the color filters and blocks leakage currents induced from the backlight. In this case, the black matrix includes a space between the gate line 2 and the data line 3, a space between the data line 3 and the pixel electrode 5 in which light leakage occurs severely, the gate line 2 and the pixel electrode 5. It is also arranged in the space between. In the drawing, the dotted line portion (corresponding to the outside of the pixel electrode with a dotted line) corresponds to the boundary of the black matrix.

A common electrode (not shown) for driving a liquid crystal is provided on the front surface of the color filter and the black matrix together with the pixel electrode.

In such a liquid crystal display, when any one of the gate lines 2 is selected and a signal is loaded on the data line 3, the thin film transistors TFT disposed at their intersections are turned on. Subsequently, the signal of the data line 3 passes through the thin film transistor TFT and is transmitted to the pixel electrode 5. Then, a predetermined electric field is formed between the pixel electrode 5 and the common electrode (not shown) to drive the liquid crystals.

However, in the above liquid crystal display device, since the black matrix for blocking the leakage current occupies a part of the edge of the pixel electrode 5, the opening area of the liquid crystal display device is reduced.

In addition, in the process of forming the black matrix, if a slight misalignment occurs, the alignment ratio of the liquid crystal display device is critically affected, and therefore, accurate alignment is required.

In addition, during the etching process for forming the black matrix, the etching residue of the black matrix remains in the opening portion of the light, thereby reducing the opening ratio.

Moreover, since the storage electrode 6 is arranged in the opening area of the pixel electrode 5, the opening ratio is further lowered.

Accordingly, an object of the present invention is to provide a liquid crystal display device which can improve the aperture ratio while minimizing light leakage without forming a black matrix.

In order to achieve the above object of the present invention, the present invention, a plurality of gate lines and data lines arranged vertically on the lower substrate to define a unit pixel, wherein the gate line overlaps one side of the data line Preferably having a first protrusion extending in the same direction as the long direction of the data line, the gate line comprising a second protrusion having a shape parallel to the gate line toward the next gate line; A drain electrode overlapping the other side of the protrusion of the gate line and extending in a direction parallel to the data line; And a pixel electrode disposed in the unit pixel space and in contact with one side of the drain and overlapping the second protrusion of the gate line.

According to the present invention, the gap between the gate line, the data line and the pixel electrode is eliminated, thereby minimizing the leakage space of light from the bottom surface of the lower substrate. Therefore, it is not necessary to provide a separate black matrix on the upper substrate.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view of the liquid crystal display according to the present invention, FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2, and FIG. 4 is a line taken along line IV-IV ′ of FIG. 2. It is a cross section.

In the present invention, a space in which light leaks is blocked by a gate line, a data line, a drain electrode, and the like, without forming a black matrix that reduces the aperture ratio by occupying the edge portion of the pixel electrode. Further, as the electrode for forming the storage capacitor, the opening area is further widened by using the gate line that comes next.

That is, referring to FIG. 2, a plurality of gate lines 11-1 and 11-2 are disposed on the lower substrate 10 at regular intervals, and data is disposed on the gate lines 11-1 and 11-2. Lines 12-1 and 12-2 are arranged to vertically intersect to define unit pixel space. In this case, the thin film transistor and the pixel electrode are formed in the unit pixel space. Here, the protrusions 11a are provided in the same direction as the long direction of the data lines so that the gate lines 11-1 and 11-2 overlap with one side of the data lines 12-1 and 12-2. In this case, the protrusion 11a may have the same width as the gate lines 11-1 and 11-2 and have a length slightly smaller than the spaced distance between the gate lines 11-1 and 11-2. In this way, the space between the protruding portion 11a and the gate line 11-2 of the next stage by a small interval prevents a short between the gate lines 11-1 and 11-2, and also a light leakage space. To minimize this. The protrusion 11a serves as a gate electrode and is disposed one by one for each unit pixel.

A channel layer (not shown) is formed on the protrusions 11a of the gate lines 11-1 and 11-2 to include the protrusions 11a. Therefore, the channel layer is interposed between the protrusion 11a and the portion where the data lines 12-1 and 12-1 overlap.

The drain electrode 13 is disposed at the other edge of the protrusion 11a. At this time as well, since the channel layer is disposed between the protrusion 11a and the drain electrode 13, the protrusion 11a, the channel layer, the data line (source electrodes: 12-1, 12-2), and the drain electrode 13 A thin film transistor TFT is formed.

Here, the storage electrode patterns 14 are formed on the gate lines 11-1 and 11-2. The storage electrode patterns 14 may be disposed in the gate lines 11-1 and 11-2 so as to be biased toward the previous gate lines 11-1 and 11-2.

In addition, the pixel electrode 15 is disposed in each unit pixel space. The pixel electrode 15 may be in contact with the drain electrode 13, and may coincide with the ends of the gate lines 11-1 and 11-2 that select the corresponding cell as shown in the drawing, or overlap a predetermined portion of the data. The ends may also coincide with the line 12-2 or overlap a predetermined portion. In this case, the pixel electrode 15 is disposed to overlap with the storage electrode pattern 14 provided on the gate line 11-2 which follows the corresponding gate lines 11-1 and 11-2. The pixel electrode 15 is in contact with the storage electrode pattern 14 to form the next gate line 11-1 and 11-2 and the storage capacitor. At this time, the dielectric constant between the gate lines 11-1 and 11-2 and the pixel electrode 15 and between the data lines 12-1 and 12-2 and the pixel electrode 15 is very low (? 4) an organic insulating film (not shown) having a degree of being interposed, and overlapping with the pixel electrode 15 and the gate lines 11-1 and 11-2 or the data lines 12-1 and 12-2. No parasitic capacitors are formed. However, the storage electrode pattern 14 that receives a signal from the pixel electrode 15 between the overlapped gate lines 11-1 and 11-2 with the storage electrode pattern 14 interposed therebetween. Used as this capacitor electrode, a storage capacitor is formed between the gate lines 11-1 and 11-2.

A cross-sectional view taken along line III-III 'of FIG. 2, wherein the protrusion 11a of the gate line is formed on the lower substrate 10, and the gate insulating layer 16 is formed on the portion including the protrusion 11a. . At this time, the protrusion 11a is formed at the same time as the gate lines 11-1 and 11-2 (see FIG. 2) although not shown in the drawing. Subsequently, the channel layer 17 is formed to include the protrusion 11a, and the ohmic layer 18 is formed on each of the upper sides of the channel layer 17 based on the center. The data line 12-1 serving as a source electrode is formed on the one ohmic layer 18, and the drain electrode 13 is formed on the other ohmic layer 18. Then, the organic insulating film 19 is coated on the top of the resultant with about 1 to 3 mu m. A contact hole is provided in the organic insulating layer 19 to expose the drain electrode 13, and the pixel electrode 15 is formed on the organic insulating layer 19 while being in contact with the contact hole. At this time, it is known that the organic insulating film 19 is relatively thickly coated to use the pixel electrode 15 on the organic insulating film 19 and the pixel electrode 15 and the organic insulating film 19 therebetween. This is to reduce the parasitic capacitors between the overlapping electrodes.

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 2, wherein a gate line 11 is formed on the lower substrate 10, and a gate is formed on the lower substrate 10 including the gate line 11. The insulating film 16 is formed. The storage electrode pattern 14 is formed on the gate insulating layer 16 including the gate line 11. In this case, the storage electrode pattern 14 is formed simultaneously with the data lines 12-1 and 12-2 (see FIG. 2) and the drain electrode 13 (see FIG. 2). The organic insulating layer 19 is formed on the lower substrate 11 on which the storage electrode pattern 14 is formed. The organic insulating layer 19 is provided with a contact hole for exposing a predetermined portion of the storage electrode pattern 14. The pixel electrode 15 is formed on the organic insulating layer 19 to be in contact with the storage electrode pattern 14 through the contact hole. In this case, the pixel electrode 15 ′ of the other cell may coincide with the boundary portion of the gate line 11 or may overlap a predetermined portion with the gate line 11.

According to the above configuration, a space in which the pixel electrode 15 is spaced apart from the gate lines 11-1 and 11-2 is eliminated, and a cell is disposed between the data line 12-1 and the pixel electrode 15 on one side. The gate line protrusion 11a and the drain electrode 13 each having a length equal to the long width of the gate line 11 are provided to block the light leakage space. In addition, the other end of the data line 12-2 and the pixel electrode 15 are formed so that their ends coincide with each other, or the pixel electrode 15 partially overlaps the data line 12-2. Here, since the width w of the thin film transistor has a length equal to the interval between the gate lines 11-1 and 11-2, the movement space of the electrons is increased, thereby improving mobility characteristics. The spaced space between the protrusion 11a and the gate line 11-1 may be neglected because of its very small size. Therefore, from the backlight (not shown) of the bottom surface of the lower substrate 10, light leakage may occur. There is no space to be generated, and there is no need to install a separate black matrix on the upper substrate.

As described in detail above, according to the present invention, the gap between the gate line, the data line, and the pixel electrode is eliminated, thereby minimizing the leakage space of light from the bottom surface of the lower substrate. Therefore, it is not necessary to provide a separate black matrix on the upper substrate.

Accordingly, since the black matrix is not provided, the opening area of the pixel electrode can be increased, and manufacturing cost can be reduced.

Furthermore, since the storage capacitor is not formed in the opening area and is generated at the portion overlapping with the gate line of the next stage, the opening ratio is further improved.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

1 is a plan view of a lower substrate of a conventional liquid crystal display.

2 is a plan view of a lower substrate of a liquid crystal display according to the present invention;

3 is a cross-sectional view taken along line III-III ′ of FIG. 2.

4 is a cross-sectional view taken along the line IV-IV 'of FIG.

(Explanation of symbols for the main parts of the drawing)

10: lower substrate 11-1, 11-2: gate line

12-1, 12-2: Data line 13: Drain electrode

14 storage electrode pattern 15 pixel electrode

Claims (6)

A gate line and a data line, each disposed at a predetermined equal interval and vertically intersecting with each other to define a unit pixel space; A protrusion extending from the gate line toward the next gate line in the same direction as the long direction of the data line and overlapping one side with the data line; A storage electrode pattern formed on the gate line; A drain electrode overlapping the other side of the protrusion; A pixel electrode formed in the unit pixel space, contacted with a storage electrode pattern formed at a next end of the drain electrode and a gate line for selecting the unit pixel space, and disposed to overlap the contacted storage electrode pattern; The unit pixel space may include a corresponding gate line and a data line for selecting and driving the unit pixel space, and a gate line and a data line adjacent thereto. A gate insulating film is interposed between the gate line and the data line, and between the gate line and the storage electrode pattern; And an organic insulating layer interposed between the pixel electrode, the data line, and the drain electrode, and between the pixel electrode and the storage electrode pattern. The liquid crystal display of claim 1, wherein a length of the protrusion is less than a distance between the gate lines. The liquid crystal display device of claim 1, wherein the drain electrode is equal to a length of the protrusion or an interval between the gate lines. The liquid crystal display of claim 1, wherein the storage electrode pattern is disposed to be biased toward a previous gate line. 2. The liquid crystal display of claim 1, wherein an end portion of the pixel electrode coincides with a gate line for selecting the corresponding unit pixel space or partially overlaps the gate line. 6. The liquid crystal display device according to claim 5, wherein the pixel electrode is coincident with a data line adjacent to a data line for driving the corresponding unit pixel space and an end thereof overlaps or overlaps a predetermined portion with the data line.

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