KR19990056771A - Liquid crystal display - Google Patents

Abstract

The present invention discloses a storage capacitor electrode structure of a liquid crystal display device capable of increasing the storage capacitor capacitance.

The disclosed invention includes: a gate bus line and a data bus line defining a unit cell space vertically intersecting on a lower substrate; A thin film transistor formed near an intersection point of the gate bus line and the data bus line; A pixel electrode connected to the thin film transistor and formed in the unit cell space; A storage capacitor electrode formed under the pixel electrode and forming a storage capacitor together with the pixel electrode; And a gate insulating film that insulates the gate bus line and the data bus line and insulates the pixel electrode from the storage capacitor electrode, wherein the gate insulating film is parallel to the gate bus line in the storage capacitor electrode. At least one long groove is provided to form a storage capacitor between the sidewall surface of the long groove and the pixel electrode.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device, and more particularly, to a storage capacitor electrode structure of a liquid crystal display device capable of increasing the storage capacitor capacitance.

1 is an equivalent circuit diagram of a liquid crystal display device.

The liquid crystal display includes a plurality of gate bus lines 1 on the substrate and a plurality of data bus lines 2 arranged and orthogonal to each gate bus line 1, and each bus line 1, Near each intersection of 2), a thin film transistor (hereinafter referred to as TFT: 3) as a switching element is provided.

The gate electrode g of each TFT 3 is connected with the gate bus line, and the drain electrode d is connected with the data bus line 1. In addition, the liquid crystal capacitor CLC and the storage capacitor CST are connected in parallel to the source electrode s of the TFT 3. Here, the liquid crystal capacitor CLC is formed of a pixel electrode, a common electrode, and a liquid crystal layer between the liquid crystal display device, and the storage capacitor CST is a storage capacitor electrode connected to the pixel electrode and the common electrode terminal. Is done.

2 is a plan view of a liquid crystal display disposed on a glass substrate. As shown in the drawing, the gate bus line 11 and the data bus line 12 are arranged on the glass substrate 10 to define a unit cell space. At this time, a gate insulating film (not shown) is interposed between the gate bus line 11 and the data bus line 12. The gate bus line 11 includes a predetermined protrusion 11a that protrudes into the unit cell space, which becomes the gate electrode of the thin film transistor. The data bus line 12 protrudes a predetermined portion so as to overlap the predetermined portion with the gate electrode 11a, and this portion becomes the drain electrode 12a of the thin film transistor. The source electrode 13 overlaps the gate electrode 11a at a portion symmetrical with the drain electrode 12a. The pixel electrodes 14 are disposed in the unit cell space, respectively. In this case, the pixel electrode 14 is in contact with the source electrode 13 overlapping the gate electrode 11a by a predetermined portion. The storage capacitor electrode 15 is provided under the pixel electrode 14. Here, a gate insulating film (not shown) is interposed between the pixel electrode 13 and the storage capacitor electrode 15 to form the storage capacitor Cst described above.

Although not described in detail in the drawings, the liquid crystal capacitor CLC is formed of the common electrode, the liquid crystal layer, and the pixel electrode 13 formed on the upper substrate.

However, in the above liquid crystal display device, parasitic capacitance Cgs is formed between the gate electrode 11a and the source electrode 13 (see FIG. 1). The parasitic capacitance Cgs is generated at the portion where the gate electrode and the source electrode overlap in the manufacturing process of the thin film transistor.

At this time, the parasitic capacitance Cgs changes the ΔVp value that degrades the image quality. Here, as shown in FIG. 3, the ΔVp value is the change in the pixel voltage (drain) that occurs when the gate voltage at the center of the high H value and the low L value of the gate voltage Vg is changed from high to low. Voltage VD-voltage Vpix applied to the pixel electrode, and when this ΔVp deviates from the reference value, flicker or afterimages are generated on the screen.

ΔVp is a function of capacitance as shown in the following equation.

ΔVp = VgCgs / (Cst + CLC + Cgs)

Accordingly, when the parasitic capacitance Cgs is increased, ΔVp is increased to deteriorate the image quality.

In order to reduce ΔVp, in the past, a technique for increasing the area of the storage capacitor electrode 15 has been proposed in order to increase the storage capacitor capacitance Cst. However, when the area of the storage capacitor electrode 15 is relatively increased, the aperture ratio of the liquid crystal display is reduced.

Therefore, an object of the present invention is to provide a storage capacitor electrode structure of a liquid crystal display device which can improve the storage capacitance by increasing the storage capacitance in a range not lowering the aperture ratio.

1 is an equivalent circuit diagram of a general liquid crystal display device

2 is a plan view of a conventional liquid crystal display device.

3 is a diagram for explaining ΔVp in a liquid crystal display.

4 is a plan view of a liquid crystal display according to Embodiment 1 of the present invention;

5 is a cross-sectional view taken along the line VV ′ of FIG. 4.

6 is a plan view of a liquid crystal display according to a second exemplary embodiment of the present invention.

7 is a cross-sectional view taken along the line VII-VII ′ of FIG. 6.

(Explanation of symbols for the main parts of the drawing)

10,20,30-Glass Substrate 11,21,31-Gate Bus Line

12,22,32-data bus line 14,24,34-pixel electrode

15,25,35-auxiliary capacitive electrode

In order to achieve the above object of the present invention, in accordance with one aspect of the present invention, a gate bus line and a data bus line defining a unit cell space vertically arranged on the lower substrate; A thin film transistor formed near an intersection point of the gate bus line and the data bus line; A pixel electrode connected to the thin film transistor and formed in the unit cell space; A storage capacitor electrode formed under the pixel electrode and forming a storage capacitor together with the pixel electrode; And a gate insulating film that insulates the gate bus line and the data bus line and insulates the pixel electrode from the storage capacitor electrode, wherein the gate insulating film is parallel to the gate bus line in the storage capacitor electrode. At least one long groove is provided to form a storage capacitor between the sidewall surface of the long groove and the pixel electrode.

In addition, according to another aspect of the invention, the gate bus line and the data bus line defining a unit cell space vertically arranged on the lower substrate; A thin film transistor formed near an intersection point of the gate bus line and the data bus line; A pixel electrode connected to the thin film transistor and formed in the unit cell space; A storage capacitor electrode formed under the pixel electrode and forming a storage capacitor together with the pixel electrode; And a gate insulating film which insulates the gate bus line from the data bus line and insulates the pixel electrode from the storage capacitor electrode, wherein the storage capacitor electrode has an uneven shape. A storage capacitor is also formed between the sidewall surface of the storage capacitor electrode and the pixel electrode.

According to the present invention, a groove is formed in the storage capacitor electrode, or the storage capacitor electrode is formed into an uneven shape to increase the surface area of the storage capacitor electrode. Thus, the aperture ratio is not reduced, and the storage capacitance is increased.

As a result, an increase in ΔVp due to parasitic capacitance can be prevented, thereby preventing deterioration in image quality of the liquid crystal display.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Example 1)

4 is a plan view of the liquid crystal display according to the first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line VV ′ of FIG. 4.

In this embodiment, by applying a principle in which the capacitance is proportional to the surface area of the electrode, grooves are formed in the capacitor electrode, thereby increasing the surface area of the electrode.

That is, as illustrated in FIG. 4, the plurality of gate bus lines 21 and the data bus lines 22 are arranged on the glass substrate 10 to define the unit cell space C1. In this case, one gate bus line 21 and one data bus line 22 are illustrated in the drawing. A gate insulating film (not shown) is interposed between the gate bus line 21 and the data bus line 22 to insulate the two lines 21 and 22.

The thin film transistor TFT is disposed near the intersection point of the gate bus line 21 and the data bus line 22. The thin film transistor TFT uses a predetermined protrusion 21a protruding from the gate bus line 21 into the unit cell space C1 as a gate electrode, and the gate electrode 21a and a predetermined portion from the data bus line 22. The part which protrudes a predetermined part is made into the drain electrode 22a so that it may overlap with. The source electrode 23 is formed to overlap the gate electrode 21a at a portion symmetrical with the drain electrode 22a. The pixel electrodes 24 are disposed in the unit cell space C1, respectively. In this case, the pixel electrode 24 is in contact with the source electrode 23. The storage capacitor electrode 25 is provided under the pixel electrode 24. Here, a gate insulating film (not shown) is interposed between the pixel electrode 24 and the storage capacitor electrode 25 as described above. Here, the storage capacitor electrode 25 is provided with at least one groove, for example, three grooves H1, H2, and H3 parallel to the gate bus line 21. In this case, the plurality of grooves H1, H2, and H3 are formed in the storage capacitor electrode 25 to increase the surface area of the storage capacitor electrode 25 and to increase the storage capacitance.

In more detail through the cross section, as shown in FIG. 5, the storage capacitor electrode 25 is disposed on the glass substrate. At this time, the storage capacitor electrodes 25 are spaced apart by the intervals of the grooves H1, H2, and H3. A gate insulating film 26 is formed over the gate insulating film 26, and a pixel electrode 24 is formed over the gate insulating film 26. Conventionally, the surface area of the storage capacitor electrode 15 (see FIG. 2) includes only the area of the upper surface and both side wall surfaces. However, in the present embodiment, as the grooves H1, H2, and H3 are provided, at least two sidewall areas are provided. 25a, for example, since eight sidewall areas are included in the surface area of the storage capacitor electrode 25, the surface area is increased. That is, since the insulating film is also disposed between the sidewall surfaces of the grooves H1, H2, and H3 and the upper pixel electrode 24, capacitance is formed.

Therefore, the storage capacitor capacitance is increased without increasing the area occupied by the storage capacitor electrode 25 in the pixel electrode.

(Example 2)

6 is a plan view of a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along the line VII-VII 'of FIG. 6.

In the present embodiment, the capacitance is proportional to the surface area of the electrode is applied to make the shape of the storage capacitor electrode an uneven shape, thereby increasing the surface area.

That is, as shown in FIG. 6, the plurality of gate bus lines 31 and the data bus lines 32 are arranged on the glass substrate 30 to define the unit cell space C2. In this case, one gate bus line 31 and one data bus line 32 are illustrated in the drawing. A gate insulating film (not shown) is interposed between the gate bus line 31 and the data bus line 32 to insulate the two lines 31 and 32.

The thin film transistor TFT is disposed near the intersection point of the gate bus line 31 and the data bus line 32. The thin film transistor TFT uses a predetermined protrusion 31a protruding from the gate bus line 31 into the unit cell space C2 as a gate electrode, and the gate electrode 31a and a predetermined portion from the data bus line 32. The part which protrudes a predetermined part is made into the drain electrode 32a so that it may overlap with. The source electrode 33 is formed to overlap the gate electrode 31a at a portion symmetrical with the drain electrode 32a. The pixel electrodes 34 are disposed in the unit cell space C2, respectively. In this case, the pixel electrode 34 is in contact with the source electrode 33. The storage capacitor electrode 35 is disposed under the pixel electrode 34. Here, a gate insulating film (not shown) is interposed between the pixel electrode 34 and the storage capacitor electrode 35 as described above. Here, the storage capacitor electrode 35 according to the present embodiment is formed in a concave-convex shape. In this case, when the storage capacitor electrode 35 is formed in an uneven form, a surface area in which the storage capacitor electrode 35 and the pixel electrode 34 overlap with each other is relatively increased. That is, since the storage capacitor electrode 35 is not only longer in length than the conventional storage capacitor electrode 15, the area of the sidewall portion is also increased in proportion to the length of the storage capacitor electrode 35. The overall surface area of the electrode 35 is increased.

In more detail through the cross section, as shown in FIG. 7, the storage capacitor electrode 35 is disposed on the glass substrate 30. At this time, the storage capacitor electrode 35 is shown in the form of a pattern spaced apart at regular intervals when viewed in cross-section, as the planar shape is a concave-convex shape. In this manner, as the storage capacitor electrode 35 is formed in the uneven form, the number of sidewall surfaces 35a of the storage capacitor electrode is also relatively increased. At this time, as described in the first embodiment, since the storage capacitor is formed on the sidewall surface 35a of the storage capacitor electrode 35, the storage capacitor capacitance is increased. Accordingly, the area occupied by the storage capacitor electrode 35 in the pixel electrode 34 can be reduced.

As described in detail above, according to the present invention, a groove is formed in the storage capacitor electrode, or the storage capacitor electrode is formed into an uneven shape to increase the surface area of the storage capacitor electrode. Thus, the aperture ratio is not reduced, and the storage capacitance is increased.

As a result, an increase in ΔVp due to parasitic capacitance can be prevented, thereby preventing deterioration in image quality of the liquid crystal display.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

A gate bus line and a data bus line defining unit cell spaces vertically arranged on the lower substrate; A thin film transistor formed near an intersection point of the gate bus line and the data bus line; A pixel electrode connected to the thin film transistor and formed in the unit cell space; A storage capacitor electrode formed under the pixel electrode and forming a storage capacitor together with the pixel electrode; And a gate insulating film that insulates the gate bus line and the data bus line and insulates the pixel electrode from the storage capacitor electrode. And at least one long groove parallel to the gate bus line in the storage capacitor electrode to form a storage capacitor between the sidewall surface of the long groove and the pixel electrode. A gate bus line and a data bus line defining unit cell spaces vertically arranged on the lower substrate; A thin film transistor formed near an intersection point of the gate bus line and the data bus line; A pixel electrode connected to the thin film transistor and formed in the unit cell space; A storage capacitor electrode formed under the pixel electrode and forming a storage capacitor together with the pixel electrode; And a gate insulating film that insulates the gate bus line and the data bus line and insulates the pixel electrode from the storage capacitor electrode. And the storage capacitor electrode has an uneven shape to form a storage capacitor between the sidewall surface of the storage capacitor electrode having the uneven shape and the pixel electrode.