KR20000021351A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to not change a kick-back voltage by overlapping a pixel electrode with a front gate bus and arranging the pixel electrode in a front unit pixel space at a same row. CONSTITUTION: Gate bus lines(11a,11b) and data bus lines(12a,12b) are crossed and arranged on a glass substrate(20) to limit a unit pixel space. A gate insulating film is inserted between gate bus lines(11a,11b) and data bus lines(12a,12b). A thin film transistor(TFT) is formed at a cross point of gate bus lines(11a,11b) and data bus lines(12a,12b). Pixel electrodes(15a,15b) are arranged in each unit pixel space for the connection to the thin film transistor(TFT). The pixel electrode(15b) is overlapped with the front gate bus line(11a) and forms a storage capacitance. The pixel electrode(15b) is separated with the pixel electrode(15a) by a certain distance.

Description

Liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can prevent a sudden change in kick-back voltage even when misalignment occurs.

In general, in the liquid crystal display, as shown in FIG. 1, the gate bus lines 1 and the data bus lines 2 are arranged on the glass substrate 10 to define a unit pixel space. At this time, a gate insulating film (not shown) is interposed between the gate bus line 1 and the data bus line 2. The gate bus line 1 includes protrusions 1a protruding one per unit pixel space. Here, the protrusion 1a becomes a gate electrode of the thin film transistor. Here, the storage on gate method is illustrated in this drawing, in which the storage electrode is integrated with the front gate bus line.

A channel layer (not shown) is disposed on the protrusion 1a, that is, the gate electrode 1a.

The data bus line 2 protrudes a predetermined portion so as to overlap the predetermined portion with the channel layer on the gate electrode 1a, and this portion becomes the source electrode 2a of the thin film transistor. The drain electrode 3 is disposed at a portion symmetrical with the source electrode 2a so as to overlap the channel layer.

Pixel electrodes 4 are disposed in respective unit pixel spaces. In this case, the pixel electrode 4 is in contact with the drain electrode 3 overlapping the gate electrode 1a by a predetermined portion. Here, the pixel electrode 4 overlaps the front gate bus line to form a storage capacitance Cst. Here, a gate insulating film (not shown) is interposed between the pixel electrode 4 and the storage electrode 1b.

In general, image quality characteristics of the liquid crystal display are determined by capacitances formed in the liquid crystal display.

That is, the kick-back voltage (ΔVp) affecting the flicker phenomenon such as flickering on the screen is expressed as a function of capacitance, as shown in Equation 1 below.

ΔVp = ΔVgCgs / (Cst + C _LC + Cgs)

ΔVg: change in gate voltage

Cgs: capacitance between gate electrode and source electrode in thin film transistor

Cst: storage capacitance

C _LC : Liquid Crystal Capacitance

It is preferable that such kickback voltage has a small value, and if this kickback voltage value is increased, flicker occurs.

However, in manufacturing a liquid crystal display device, due to misalignment due to several shot processes, the capacitance between the shot and the shot may be changed. In particular, in the case of the liquid crystal display using the front gate line method, even when a slight misalignment occurs in the formation of the pixel electrode, the area overlapping with the front gate bus line is greatly changed, so the change in the storage capacitance Cst is large.

As such, when a capacitance difference occurs between the shot and the shot, mura is generated at the shot boundary.

Here, cell 1 of FIG. 1 is a cell formed by the first shot process, and cell 2 is a cell formed by the second shot process. As shown in the figure, since the storage capacitance Cst of the cell 1 and the cell 2 is different, mura occurs at the interface between the cell 1 and the cell 2.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of minimizing a change in kickback voltage by preventing a sudden change in storage capacitance even when slight misalignment occurs. do.

1 is a plan view of a general liquid crystal display device.

2 is a plan view of a liquid crystal display device according to the present invention;

(Explanation of symbols for the main parts of the drawing)

11a, 11b-gate bus lines 12a, 12b-data bus lines

15-pixel electrode

In order to achieve the above object of the present invention, according to one aspect of the present invention, the present invention provides a plurality of gate bus lines arranged in a first direction on a lower substrate, and a second substantially perpendicular to the first direction. A plurality of data bus lines arranged in a direction to define a unit pixel space, thin film transistors disposed near intersections of the gate bus lines and the data bus lines, a gate insulating film insulated between the gate bus lines and the data bus lines; And a pixel electrode formed to contact the thin film transistor in the unit pixel space, wherein the pixel electrode is overlapped with a gate bus line arranged adjacent to a gate bus line for selecting the thin film transistor in the unit pixel space. It is arranged to extend to a predetermined portion of the unit pixel space of the front end, The pixel electrodes formed in the same column front end unit pixel space may be spaced apart from each other by a predetermined distance.

According to the present invention, the pixel electrodes are formed to overlap the front gate bus lines and to be arranged in the front unit pixel spaces in the same column. In this case, the pixel electrodes of the same column front end unit pixel space are formed to be spaced apart from each other by a predetermined distance.

Accordingly, even if some misalignment occurs, the area overlapping with the pixel electrode and the front gate bus line does not change, and therefore the kickback voltage hardly changes.

Therefore, shot mura does not occur.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view of the liquid crystal display according to the present invention.

First, as shown in FIG. 2, the gate bus lines 11a and 11b and the data bus lines 12a and 12b are alternately arranged on the glass substrate 20 to define a unit pixel space. At this time, a gate insulating film (not shown) is interposed between the gate bus lines 11a and 11b and the data bus lines 12a and 12b.

Here, region 1 is a portion formed by the first shot process, and region 2 is a portion formed by the second shot process.

The thin film transistor TFT is provided in a known manner near the intersection point of the gate bus lines 11a and 12b and the data bus lines 12a and 12b.

In each unit pixel space, pixel electrodes 15a and 15b are disposed to be connected to the thin film transistor TFT formed in the corresponding unit pixel space. In this case, for example, the pixel electrode 15b overlaps the front gate bus line 11a to form a storage capacitance. In the meantime, the pixel electrodes 15b are arranged to be spaced apart from the pixel electrodes 15a formed in the unit pixel spaces of the same column front end by a predetermined distance.

Then, as shown in the drawing, due to the misalignment between shots between the region 1 and the region 2, the pixel electrodes 15a and 15b are misaligned, and the area overlapping the pixel electrode 15b and the front gate bus line 11a is not changed. . Thus, storage capacitance does not change.

As described in detail above, according to the present invention, the pixel electrode is formed to be disposed in the same unit of front end unit pixel space while overlapping the front end gate bus line. In this case, the pixel electrodes of the same column front end unit pixel space are formed to be spaced apart from each other by a predetermined distance.

Accordingly, even if some misalignment occurs, the area overlapping with the pixel electrode and the front gate bus line does not change, and therefore the kickback voltage hardly changes.

Therefore, shot mura does not occur.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (1)

A plurality of gate bus lines disposed in a first direction on the lower substrate; Several data bus lines arranged in a second direction substantially perpendicular to the first direction to define a unit pixel space; Thin film transistors disposed near intersections of the gate bus lines and the data bus lines; A gate insulating film insulated between the gate bus line and the data bus line; And A pixel electrode formed to contact the thin film transistor in the unit pixel space; The pixel electrode overlaps with a gate bus line adjacent to a gate bus line for selecting a corresponding thin film transistor in a unit pixel space, and extends to a predetermined portion of the unit pixel space in the same column front end and in the unit column front unit pixel space. And a predetermined distance from the pixel electrode to be formed.